DETAILED ACTION
1. This Office action is in response to the amendment filed on 01/12/2026.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
4. Applicant's arguments filed 01/12/2026 have been fully considered but they are not persuasive:
Applicant(s) argues with respect to claims 1 - 20:
Applicant respectfully traverses the §102 rejection with regard to claims 18-20. Claim 18 recites, in part, "a capacitive voltage divider configured to generate a reduced voltage that is about half of a voltage input of the multistage power converter." To address this limitation, the Office cites to paragraph [0057] of Yan which discloses that "[w]hen operating in the steady state and when the hybrid converter 111 is stable, the flying capacitors hold a DC voltage equal to about 1/2 of Vin." A reproduction of a portion of Yan's FIG. 5 illustrating the flying capacitors (Cfly1 and Cfly2) in Yan's hybrid converter (111) is provided below.” It continues “A person of ordinary skill in the art would recognize that the claimed "capacitive voltage divider" includes at least two capacitors that can be coupled in series with each other. However, as clearly illustrated above in Yan's FIG. 5, the flying capacitors (Cfly1 and Cfly2) cannot be coupled in series with each other. Thus, Yan does not disclose, at least "a capacitive voltage divider [emphasis added] configured to generate a reduced voltage that is about half of a voltage input of the multistage power converter" recited in claim 18. For at least these reasons, Yan does not present a prima facie case of anticipation for claim 18. Claims 19 and 20 depend from claim 18, and thus incorporate the features recited therein, including the features noted above as being absent from Yan, as well as their own separately recited patentably distinct features. Accordingly, Applicant respectfully requests reconsideration and withdrawal of the § 102 rejection of claims 1, 2, 4-12, and 14-20.”
In response, as mentioned above about Claim 18 recites, in part, "a capacitive voltage divider configured to generate a reduced voltage that is about half of a voltage input of the multistage power converter.". To address this limitation, Yan et al was used which discloses in paragraph 0057 “When operating in the steady state and when the hybrid converter 111 is stable, the flying capacitors hold a DC voltage equal to about ½ of VIN.” which is functioning as a “capacitive voltage divider” by dividing the input voltage to about half. Additionally, as suggested in paragraph 0066 recites “As shown in FIG. 4A, power transistors Q2, Q4, Q5, and Q7 are turned on, while the remaining power transistors are turned off. Thus, the second flying capacitor Cfly2 and the first flying capacitor Cfly1 are connected in series between the input voltage VIN and ground”. Secondly, paragraph 0070 recites “As shown in FIG. 4C, power transistors Q1, Q3, Q6, and Q8 are turned on, while the remaining power transistors are turned off. Thus, the first flying capacitor Cfly1 and the second flying capacitor Cfly2 are connected in series between the input voltage VIN and ground.” Finally, paragraph 0055 recites “Moreover, the hybrid converter 111 operates with high efficiency, even when VO is a large step down voltage from VIN (for instance, when stepping down with a ratio of 4:1 or more, for instance, from 48V to 12V)”, which would imply that the hybrid converter can operate with a lower step down such as 48V to 24V and in fact would perform with higher efficiency. Therefore, the rejection is maintained.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 1 - 2, 4 - 12 and 14 - 21 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US Pub. No. 2022/0231618 A1; (hereinafter Yan et al), cited in previous Office Action.
Regarding claim 1, Yan et al [e.g., Figs. 4A, 4C and 5, -- Figs. 4A and 4C illustrate circuit during operation --] a system for power conversion [e.g., hybrid power conversion system 110], comprising: a multistage power converter [e.g., hybrid converter 111] including: a first stage circuit including a first pair of field-effect transistors (FETs) [e.g., -- refer to Fig.4A --, Q5 and Q4], a first output inductor [e.g., inductor L2], a first capacitor coupled between the first pair of FETs [e.g., Cfly2 coupled between Q5 and Q4. For examination purposes, the examiner will interpret the term “coupled” in its broadest sense to refer as electrical components that are connected directly or indirectly in a way that allows for the transfer of electrical energy or signals between them], and a first crossing FET [e.g., Q7], and a second stage circuit including a second pair of FETs [e.g., -- refer to Fig. 4C --, Q1 and Q8], a second output inductor [e.g., inductor L1], a second capacitor coupled between the second pair of FETs [e.g., Cfly1 coupled between Q1 and Q8], and a second crossing FET [e.g., Q3] coupled between a cathode terminal of the second capacitor and an anode terminal of the first capacitor [e.g., -- refer to Fig. 4C -- , Q3 coupled between cathode terminal of Cfly1 and anode of Cfly2 when Q6 is ON]; and a controller [e.g., PWM controller 102] configured to: turn on the first stage circuit during a first on-time to charge the first output inductor [e.g., -- refer to Fig. 4A --, L2 charge when Q2, Q4, Q5 and Q7 are ON, p. 0066 recites “As shown in FIG. 4A, power transistors Q2, Q4, Q5, and Q7 are turned on, while the remaining power transistors are turned off. Thus, the second flying capacitor Cfly2 and the first flying capacitor Cfly1 are connected in series between the input voltage VIN and ground. Additionally, the current through inductor L1 ramps down while the current through inductor L2 ramps up.”], turn on the first crossing FET during the first on-time [e.g., Q7 is ON], turn on the second stage circuit during a second on-time to charge the second output inductor[e.g., -- refer to Fig. 4C--, charges L1 when Q1, Q3, Q6 and Q8 are ON, p. 0070 recites “As shown in FIG. 4C, power transistors Q1, Q3, Q6, and Q8 are turned on, while the remaining power transistors are turned off. Thus, the first flying capacitor Cfly1 and the second flying capacitor Cfly2 are connected in series between the input voltage VIN and ground. Additionally, the current through inductor L1 ramps up while the current through inductor L2 ramps down.”], and turn on the second crossing FET during the second on-time [e.g., Q3 is ON], wherein the first crossing FET is coupled between the cathode terminal of the first capacitor and the anode terminal of the second capacitor [e.g., Q7 coupled between cathode terminal of Cfly2 and anode of Cfly1 when Q2 is ON].
Regarding claim 2, Yan et al [e.g., Fig. 5] discloses wherein a capacitance of the first capacitor is substantially equal to a capacitance of the second capacitor [e.g., p. 0079 recites "The simulation observes the transient response of the hybrid converter 111 under a load current step change (current step in ILOAD) in which the capacitances of the first flying capacitor Cfly1 and the second flying capacitor Cfly2 are equal and in which the inductances of the first inductor L1 and the second inductor L2 are equal, …"].
Regarding claim 4, Yan et al [e.g., Fig. 2 and 5,-- refer to Fig. 2D for timing diagram --] discloses wherein the controller is further configured to: turn on the second stage circuit before turning off the first stage circuit [e.g., Q1 (control signal A) turns ON before Q5 turns OFF (control signal B)], and then turn on the first stage circuit before turning off the second stage circuit [e.g., Q5 (control signal B) turns ON before Q1 turns OFF (control signal A)].
Regarding claim 5, Yan et al [e.g., Figs. 2 and 5 -- refer to Fig. 2D for timing diagram --] discloses wherein the controller is further configured to: operate the first stage circuit at a switching frequency, the first on-time, and a first phase [e.g., p. 0046 recites "This operation repeats periodically, and the switching period is TSW. The ratio of the on-time of top power transistor M1 over the switching period TSW is referred to as duty cycle"], and operate the second stage circuit at the switching frequency, the second on-time, and a second phase different than the first phase [e.g., duty cycle of Q1 (signal A) and Q5 (signal B) shown as the same with signal B shifted].
Regarding claim 6, Yan et al [e.g., Figs. 2 and 5, -- refer to Fig. 2D for timing diagram --] discloses wherein the first on-time is substantially equal to second on-time [e.g., ON time of Q1 (dTsw of signal A) shown substantially equal to ON time of Q5 (dTsw of signal B)].
Regarding claim 7, Yan et al [e.g., Fig. 5] discloses wherein the first pair of FETs includes: a first high-side FET coupled between a voltage input and the anode terminal of the first capacitor [e.g., Q5 coupled between Vin and anode of Cfly2], and a first low-side FET coupled between the cathode terminal of the first capacitor and a reference terminal [e.g., Q4 coupled between cathode of Cfly2 and ground], and wherein the second pair of FETs includes: a second high-side FET coupled between the voltage input and the anode terminal of the second capacitor [e.g., Q1 coupled between Vin and anode of Cfly1], and a second low-side FET coupled between the cathode terminal of the second capacitor and the reference terminal [e.g., Q8 coupled between cathode terminal of Cfly1 and ground].
Regarding claim 8, Yan et al [e.g., Fig. 5] discloses wherein the first output inductor is coupled between the cathode terminal of the first capacitor and a voltage output [e.g., inductor L2 coupled between cathode of Cfly2 and Vout], and wherein the second output inductor is coupled between the cathode terminal of the second capacitor the voltage output [e.g., inductor L1 coupled between cathode terminal of Cfly1 and Vout].
Regarding claim 9, Yan et al [e.g., Fig. 5] discloses wherein the voltage input is between 40 Volts and 60 Volts, and wherein the voltage output is about 12 Volts [e.g., p. 0055 recites "Moreover, the hybrid converter 111 operates with high efficiency, even when VO is a large step down voltage from VIN (for instance, when stepping down with a ratio of 4:1 or more, for instance, from 48V to 12V)"].
Regarding claim 10, Yan et al [e.g., Figs. 4A, 4C and 5, -- Figs. 4A and 4C illustrate circuit during operation --] discloses a multistage power converter [e.g., hybrid power conversion system 110] comprising: a first stage circuit [e.g., right half on circuit (Q5, Q6, Q7, Q8 and Cfly2)] including: a first capacitor [e.g., Cfly2],
a first high-side field-effect transistor (FET) coupled between a voltage input and an anode terminal of the first capacitor [e.g., Q5 coupled between Vin and anode of Cfly1, For examination purposes, the examiner will interpret the term “coupled” in its broadest sense to refer as electrical components that are connected directly or indirectly in a way that allows for the transfer of electrical energy or signals between them],
a first low-side FET [e.g., Q8] coupled between a cathode terminal of the first capacitor and a reference terminal [e.g., Q8 coupled between cathode of Cfly2 and ground], a first crossing FET [e.g., Q7], and a first output inductor coupled between the cathode terminal of the first capacitor and a voltage output [e.g., inductor L2 coupled between cathode of Cfly2 and Vout]; and a second stage circuit [e.g., left half on circuit (Q1, Q2, Q3, Q4 and Cfly1)] including: a second capacitor [e.g., Cfly1], a second high-side FET [e.g., Q1] coupled between the voltage input and an anode terminal of the second capacitor [e.g., Q1 coupled between Vin and anode of Cfly1], a second low-side FET [e.g., Q4] coupled between a cathode terminal of the second capacitor and the reference terminal [e.g., Q4 coupled between cathode of Cfly1 and ground], a second crossing FET [e.g., Q3] coupled between the cathode terminal of the second capacitor and the anode terminal of the first capacitor [e.g., -- refer to Fig. 4C --, Q3 coupled between cathode of Cfly1 and the anode of Cfly2 (when Q6 is conducting)], and configured to turn on when the second high-side FET and the first low-side FET are both turned on [e.g., -- refer to Fig. 4C --, Q3 ON when Q1 and Q8 are ON], and a second output inductor [e.g., inductor L1] coupled between the cathode terminal of the second capacitor and the voltage output [e.g., inductor L1 coupled between cathode of Cfly1 and Vout], wherein the first crossing FET coupled between the cathode terminal of the first capacitor and the anode terminal of the second capacitor [e.g., -- refer to Fig. 4A --, Q7 coupled between cathode of Cfly2 and the anode of Cfly1 (when Q2 is conducting)], and configured to turn on when the first high-side FET and the second low-side FET are both turned on [e.g., -- refer to Fig. 4A --, Q7 ON when Q5 and Q4 are ON].
Regarding claim 11, Yan et al [e.g., Figs. 4A, 4C and 5, -- Figs. 4A and 4C illustrate circuit during operation --] wherein a drain terminal of the first crossing FET [e.g., drain of Q7] is coupled to the anode terminal of the second capacitor [e.g., -- refer to Fig. 4A --, drain terminal of Q7 coupled to anode of Cfly1 when Q2 is ON], and wherein a drain terminal of the second crossing FET [e.g., drain terminal of Q3] is coupled to the anode terminal of the first capacitor [e.g., -- refer to Fig. 4C --, drain terminal of Q3 coupled to anode of Cfly2 when Q6 is ON].
Regarding claim 12, Yan et al [e.g., Figs. 4A, 4C and 5, -- Figs. 4A and 4C illustrate circuit during operation --] wherein a drain terminal of the first high-side FET is coupled to the voltage input [e.g., drain of Q5 coupled to Vin], wherein a drain terminal of the first low-side FET is coupled to the cathode terminal of the first capacitor [e.g., drain terminal of Q8 coupled to cathode of Cfly2], wherein a drain terminal of the second high- side FET is coupled to the voltage input [e.g., drain of Q1 connected to Vin], and wherein a drain terminal of the second low-side FET is coupled to the cathode terminal of the second capacitor [e.g., drain terminal of Q4 connected to cathode of Cfly1].
Regarding claim 14, Yan et al [e.g., Fig. 5] discloses wherein a capacitance of the first capacitor is substantially equal to a capacitance of the second capacitor [e.g., p. 0079 recites "The simulation observes the transient response of the hybrid converter 111 under a load current step change (current step in ILOAD) in which the capacitances of the first flying capacitor Cfly1 and the second flying capacitor Cfly2 are equal and in which the inductances of the first inductor L1 and the second inductor L2 are equal, …"].
Regarding claim 15, Yan et al [e.g., Figs. 4A, 4C and 5, -- Figs. 4A and 4C illustrate circuit during operation --] a method for operating a multistage power converter, comprising: turning on a first stage circuit [e.g., -- refer to Fig. 4A for first stage --] of the multistage power converter during a first on-time to charge a first output inductor of the multistage power converter [e.g., -- refer to Fig. 4A --, Q5 and Q4 charge inductor L2 when conducting, p. 0066 recites “As shown in FIG. 4A, power transistors Q2, Q4, Q5, and Q7 are turned on, while the remaining power transistors are turned off. Thus, the second flying capacitor Cfly2 and the first flying capacitor Cfly1 are connected in series between the input voltage VIN and ground. Additionally, the current through inductor L1 ramps down while the current through inductor L2 ramps up.”]; turning on a first crossing FET to couple a cathode terminal of a first capacitor to an anode terminal of a second capacitor during the first on-time [e.g., Q7 ON and coupled to cathode of Cfly2 with anode of Cfly1 via Q2, For examination purposes, the examiner will interpret the term “coupled” in its broadest sense to refer as electrical components that are connected directly or indirectly in a way that allows for the transfer of electrical energy or signals between them] to divide a voltage input of the multistage power converter [e.g., p. 0057 recites "When operating in the steady state and when the hybrid converter 111 is stable, the flying capacitors hold a DC voltage equal to about 1/2 of VIN”], wherein the first capacitor is coupled between a first pair of field-effect transistors (FETs) of the first stage circuit [e.g., Cfly2 coupled between Q5 and Q4]; turning on a second stage circuit [e.g., -- refer to Fig. 4C for second stage --] of the multistage power converter during a second on-time to charge a second output inductor of the multistage power converter [e.g., Q1 and Q8 charge inductor L1 when conducting, p. 0070 recites “As shown in FIG. 4C, power transistors Q1, Q3, Q6, and Q8 are turned on, while the remaining power transistors are turned off. Thus, the first flying capacitor Cfly1 and the second flying capacitor Cfly2 are connected in series between the input voltage VIN and ground. Additionally, the current through inductor L1 ramps up while the current through inductor L2 ramps down.”]; and coupling turning on a second crossing FET to couple a cathode terminal of the second capacitor to an anode terminal of the first capacitor during the second on-time [e.g., -- refer to Fig. 4C --, Q3 ON and coupled to cathode of Cfly1 with anode of Cfly2 when Q6 is ON] to divide the voltage input [e.g., p. 0057 recites "When operating in the steady state and when the hybrid converter 111 is stable, the flying capacitors hold a DC voltage equal to about 1/2 of VIN"], wherein the second capacitor is coupled between a second pair of FETs of the second stage circuit [e.g., Cfly1 coupled between Q1 and Q8], wherein the first crossing FET is coupled between the cathode terminal of the first capacitor and the anode terminal of the second capacitor [e.g., -- refer to Fig. 4A -- , Q7 coupled between cathode of Cfly2 and anode of Cfly1 when Q2 is ON], and wherein the second crossing FET is coupled between the cathode terminal of the second capacitor and the anode terminal of the first capacitor [e.g., -- refer to Fig. 4C --, Q3 coupled between cathode of Cfly1 and anode of Cfly2 when Q6 is ON].
Regarding claim 16, Yan et al [e.g., Figs. 2 and 5,-- refer to Fig. 2D for timing diagram --] discloses further comprising: turning on the first stage circuit before turning off the second stage circuit [e.g., Q5 (control signal B) turns ON before Q1 turns OFF (control signal A)]; and then turning on the second stage circuit and before turning off the first stage circuit [e.g., Q1 (control signal A) turns ON before Q5 turns OFF (control signal B)].
Regarding claim 17, Yan et al [e.g., Figs. 2 and 5 ,-- refer to Fig. 2D for timing diagram --] discloses further comprising: operating the first stage circuit at a switching frequency, the first on-time, and a first phase [e.g., p. 0046 recites "This operation repeats periodically, and the switching period is TSW. The ratio of the on-time of top power transistor M1 over the switching period TSW is referred to as duty cycle"]; and operating the second stage circuit at the switching frequency, the second on-time, and a second phase different than the first phase [e.g., duty cycle of Q1 (signal A) and Q5 (signal B) shown as the same with signal B shifted].
Regarding claim 18, Yan et al [e.g., Figs. 2, 4A, 4C and 5, -- refer to Fig. 2D for timing diagram, Figs. 4A and 4C illustrate circuit during operation --] discloses a system for power conversion [e.g., hybrid power conversion system 110], comprising: a multistage power converter [e.g., hybrid converter 111] including: a first stage circuit [e.g., -- refer to Fig. 4A --], a second stage circuit [e.g., -- refer to Fig. 4C --], a capacitive voltage divider configured to generate a reduced voltage that is about half of a voltage input of the multistage power converter [e.g., Cfly1 and Cfly2, p. 0057 recites "When operating in the steady state and when the hybrid converter 111 is stable, the flying capacitors hold a DC voltage equal to about 1/2 of VIN."], and a second order output filter [e.g., inductors L1 and L2] configured to use the reduced voltage to generate a voltage output of the multistage power converter [e.g., generates Vout]; and a controller [e.g., PWM controller 102] configured to generate driving signals that operate the first stage circuit and the second stage circuit with an interleaving phase shift [e.g., -- refer to Fig. 2D for timing diagram --, controls switching of converter 111 via signals (A, A', B, B', C and D)].
Regarding claim 19, Yan et al [e.g., Figs. 2, 4A, 4C and 5, -- refer to Fig. 2D for timing diagram, Figs. 4A and 4C illustrate circuit during operation --] discloses wherein the second order output filter includes: a first output inductor coupled between the first stage circuit and the voltage output [e.g., inductor L2 coupled between first stage -- refer to Fig. 4A -- and output voltage Vo], a second output inductor coupled between the second stage circuit and the voltage output [e.g., inductor L1 coupled between second stage -- refer to Fig. 4C -- and output voltage Vo], and an output capacitor coupled between the voltage output and a reference terminal [e.g., Cout coupled between output voltage Vo and ground].
Regarding claim 20, Yan et al [e.g., Figs. 2, 4A, 4C and 5, -- refer to Fig. 2D for timing diagram, Figs. 4A and 4C illustrate circuit during operation --] discloses wherein the first stage circuit [e.g., -- refer to Fig. 4A --], the second stage circuit [e.g., -- refer to Fig. 4C --], and the capacitive voltage divider [e.g., Cfly1 and Cfly2, p. 0057 recites "When operating in the steady state and when the hybrid converter 111 is stable, the flying capacitors hold a DC voltage equal to about 1/2 of VIN."] further include a plurality of field-effect transistors (FETs) [e.g., transistors Q1 - Q8] configured to block current flow through the plurality of FETs when the plurality of FETs are turned off [e.g., p. 0056 recites "… the first through eighth power transistors Q1-Q8 are controlled by control signals A, A', B, B', C and D, where A' is complimentary signal of A and B' is complimentary signal of B. Since this example implements the power transistors using n-type field-effect transistors (NFETs), when a given control signal is high, the corresponding power transistor is on"].
Regarding claim 21, Yan et al [e.g., Figs. 2, 4A, 4C and 5, -- Fig. 2D for timing diagram, Figs. 4A and 4C illustrate circuit during operation --] discloses wherein the capacitive voltage divider further includes: a first capacitor [e.g., Cfly1], and a second capacitor [e.g., Cfly1] coupled in series with the first capacitor [p. 0066 recites “As shown in FIG. 4A, power transistors Q2, Q4, Q5, and Q7 are turned on, while the remaining power transistors are turned off. Thus, the second flying capacitor Cfly2 and the first flying capacitor Cfly1 are connected in series between the input voltage VIN and ground.”].
Examiner’s Note
8. Examiner has cited particular paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
9. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
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