DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 09/17/2025, 03/04/2025 and 12/21/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 7, 8-12 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hasan et al. (PG Pub 2023/0197816; hereinafter Hasan).
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Regarding claim 1, refer to Fig. 3, Hasan teaches a semiconductor device 300 comprising:
a row of source/drain regions (not indexed; (para [0055-0061; discloses that the device is a “gate all around device” (GAA), i.e. a transistor with elements 312 being the channel regions; which implicitly discloses the existence of source/drain regions located in the direction perpendicular to the cross section shown in Fig. 3 on both sides and connected to the channel elements 312) delineating a frontside and a backside opposite the frontside of the semiconductor device;
a front gate cut 318 from the frontside of the semiconductor device (318 extends from the upper side of 316) the front gate cut having a depth that is less than a height of a gate structure 316 for the semiconductor device (see Fig. 3); and
a back gate cut 310 from the backside of the semiconductor device (310 extends into 316 from the bottom; see Fig. 3) contacting the front gate cut (see Fig. 3).
Regarding claim 5, refer to Fig. 3, Hasan teaches the back gate cut 310 extends through an isolation region 306 (see Fig. 3).
Regarding claim 7, refer to Fig. 3, Hasan teaches the back gate cut 310 has a height that is less than the height of the gate structure (the gate structure is the total height of 318 and 310) (see Fig. 3 above).
Regarding claim 8, refer to Fig. 3, Hasan teaches a semiconductor device 300 comprising:
a row of source/drain regions delineating a frontside and a backside opposite the frontside of the semiconductor device (para [0055-0061; discloses that the device is a “gate all around device” (GAA), i.e. a transistor with elements 312 being the channel regions; which implicitly discloses the existence of source/drain regions located in the direction perpendicular to the cross section shown in Fig. 3 on both sides and connected to the channel elements 312);
a front gate 318 cut from the frontside of the semiconductor device (318 extends from the upper side of 316), wherein the front gate cut having a depth that is less than a height of a gate structure for the semiconductor device (see Fig. 3);
a back gate 310 cut from the backside of the semiconductor device (310 extends into 316 from the bottom; see Fig. 3) which contacts the front gate cut (see Fig. 3).
and backside source/drain cut structures (see Fig. 3).
Regarding claim 9, refer to Fig. 3, Hasan teaches the backside source/drain cut structures are disposed between source/drain regions of the row of source/drain regions.
Regarding claim 10, refer to Fig. 3, Hasan teaches the front gate cut 318 and the back gate cut 310 together divide the gate structure 316 into first gate structure (316-right) for a first field effect transistor and a second gate structure(316-left) for a second field effect transistor (see Fig. 3).
Regarding claim 11, refer to Fig. 3, Hasan teaches at least one of the first field effect transistor and the second field effect transistor is a nanosheet device (para [0055]).
Regarding claim 12, refer to Fig. 3, Hasan teaches the back gate cut 310 extends through an isolation region 306 (see Fig. 3).
Regarding claim 14, refer to Fig. 3, Hasan teaches the back gate cut 310 has a height that is less than the height of the gate structure 316 (see Fig. 3).
Prior Art
2. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
a. Dewey et al. (PG Pub 2020/0105751) teaches a stacked transistor architecture
b. Zhou et al. (PG Pub 2020/0052125) teaches a semiconductor device.
Allowable Subject Matter
3. Claims 2-4, 6 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15-20 are allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 2, the front gate cut and the back gate cut together divide the gate structure into first gate structure for a first field effect transistor and a second gate structure for a second field effect transistor. Claim 3 would be allowable, because it depends on allowable claim 2.
Claim 4 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 4, source regions of the row of source/drain regions are separated from drain regions of the source/drain regions by backside source/drain cut structures.
Claim 6 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 6, at least one source/drain region from the row of source/drain regions is electrically contacted by a backside contact to a power distribution network.
Claim 13 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 13, at least one source/drain region from the row of source/drain regions is electrically contacted by a backside contact to a power distribution network.
Claim 15 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 15, a gate structure in contact with a first stack of nanosheets and a second stack of nanosheets; a front gate cut having a depth that is less than a height of the gate structure; and a back gate cut contacting the front gate cut, wherein the front gate cut in combination with the back gate cut together divide the gate structure into a first gate structure and a second gate structure.. Claims 16-20 would be allowable, because they depend on allowable claim 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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