Prosecution Insights
Last updated: April 19, 2026
Application No. 18/392,121

MICRO LIGHT EMITTING DIODE CHIP AND DISPLAY DEVICE

Non-Final OA §103
Filed
Dec 21, 2023
Examiner
SEVEN, EVREN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Xiamen Extremely Pq Display Technology Co. Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
82%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
532 granted / 723 resolved
+5.6% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
29 currently pending
Career history
752
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
51.9%
+11.9% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
20.3%
-19.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 723 resolved cases

Office Action

§103
Detailed Action The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 5-11, 15-17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20220316663 to Wildeson et al. (Wildeson) in view of U.S. Pat. Pub. No. 20210210664 to Huang et al. (Huang). Regarding Claim 1, Wildeson teaches a micro light emitting diode (micro-LED) chip, comprising an epitaxial structure; wherein the epitaxial structure comprises: a first doped type semiconductor layer 817, a second doped type semiconductor layer 816, and an active layer 815 disposed between the first doped type semiconductor layer and the second doped type semiconductor layer; wherein a light-emitting side of the first doped type semiconductor layer facing away from the active layer is provided with a patterned structure (see Fig. 9A); and wherein an elongated edge a of the micro-LED chip, a thickness b of the micro- LED chip, and a peak-valley height difference c of the patterned structure satisfy the following formula: 0.01<c/b<0.3 ([0051], see MPEP 2144.05(I)). Wildeson does not explicitly teach satisfying the formula 0.01<b/a<6. However, in analogous art, Huang teaches 0.01<b/a<6 in ([0062-0064], see again MPEP 2144.05(I)). It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Huang because Wildeson is silent regarding the width or length of the device, motivating those of ordinary skill to seek out such teachings to fully practice the invention of Wildeson. Regarding Claims 2 and 3, Wildeson and Huang teach the micro-LED chip according to claim 1, wherein the peak-valley height difference c of the patterned structure is greater than or equal to 0.1 um and less than 1 um ([0051], “about” 1 micron encompasses less than one micron). Regarding Claim 5, Wildeson and Huang teach the micro-LED chip according to claim 2, wherein the elongated edge a of the micro-LED chip is less than 100 pm, and the thickness b of the micro-LED chip is less than 20 pm (Huang, [0062-0064], see again MPEP 2144.05(I)). Regarding Claim 6, Wildeson and Huang teach the micro-LED chip according to claim 1, wherein the patterned structure is a two-dimensional photonic crystal structure (see Fig. 9A). Regarding Claim 7, Wildeson and Huang teach the micro-LED chip according to claim 1, wherein the peak-valley height difference c of the patterned structure is less than or equal to 1.5 um ([0051]). Regarding Claim 8, Wildeson and Huang teach the micro-LED chip according to claim 1, wherein the patterned structure is disposed on the light-emitting side of the first doped type semiconductor layer facing away from the active layer (see Fig., 9A) by performing a pattern transfer method on a growth substrate formed with the pattern structure (product by process limitations do not bear weight, see MPEP 2113). Regarding Claim 9, Wildeson and Huang teach the micro-LED chip according to claim 1, wherein the patterned structure is disposed on the light-emitting side of the first doped type semiconductor layer facing away from the active layer by using a dry etching method after performing a laser lift- off (LLO) processing on a growth substrate (product by process limitations do not bear weight, see MPEP 2113). Regarding Claim 10, Wildeson and Huang teach the micro-LED chip according to claim 1, wherein the elongated edge a of the micro-LED chip is a length along a horizontal direction (either dimension may be defined as required, Huang teaches either length or width may be a wide array of sizes). Regarding Claim 11, Wildeson and Huang teach the micro-LED chip according to claim 1, wherein the peak-valley height difference c of the patterned structure is a height difference between a upper end of the patterned structure facing away from the first doped type semiconductor layer and a lower end of the patterned structure facing towards the first doped type semiconductor layer along a vertical direction (see Fig., 9A). Regarding Claim 15, Wildeson and Huang teach a display device, comprising: a circuit substrate, wherein the circuit substrate is provided with a plurality of electrode structures, and each of the plurality of electrode structures comprises a first electrode and a second electrode disposed in pairs (shown in schematic in Fig. 5; anode cathode electrode pairs are inherent to displays); and a plurality of micro-LED chips, wherein each of the plurality of micro-LED chips is the micro-LED chip according to claim 1 (see above); and the plurality of micro-LED chips are disposed on the circuit substrate, and the plurality of micro-LED chips are electrically connected to the plurality of electrode structures, respectively (definition of a display). Regarding Claims 16 and 17, Wildeson and Huang teach the display device according to 15, wherein the peak-valley height difference c of the patterned structure is greater than or equal to 0.1 um and less than 1 um (see above). Regarding Claim 19, Wildeson and Huang teach the display device according to 16, wherein the elongated edge a of the micro- LED chip is less than 100 um, and the thickness b of the micro-LED chip is less than 20 um (see above). Regarding Claim 20, Wildeson and Huang teach the display device according to 15, wherein the peak-valley height difference c of the patterned structure is less than or equal to 1.5 pm (see above). Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Wildeson. Regarding Claim 12, Huang teaches a micro-LED chip, comprising: an epitaxial structure, wherein the epitaxial structure has no growth substrate and has no bonding substrate for supporting the epitaxial structure (See Fig. 1), and the epitaxial structure comprises: a first doped type semiconductor layer 210, a second doped type semiconductor layer 230, and an active layer 220 disposed between the first doped type semiconductor layer and the second doped type semiconductor layer; wherein a light-emitting side of the first doped type semiconductor layer facing away from the active layer is provided with a patterned structure 100; wherein an elongated edge a of the micro-LED chip is less than 100 um, and a thickness b of the micro-LED chip is less than or equal to 10 pm [0062-0064]. Huang does not teach a peak-valley height difference c of the patterned structure is less than 1 pm; and wherein the thickness b of the micro-LED chip and the peak-valley height difference c of the patterned structure satisfy the following formula: 0.01<c/b<0.3. However, in analogous art, Wildeson teaches that light extraction structures may be about 1 micron [0051], satisfying the formula in combination. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Wilderson as Huang does not specify a height for the structures 100, motivating those of ordinary skill to seek out such teachings. Regarding Claim 13, Huang and Wilderson teach the micro-LED chip according to claim 12, wherein the peak-valley height difference c of the patterned structure is greater than or equal to 0.1 um and less than 1 um ([0051], “about” 1 micron encompasses less than one micron). Allowable Subject Matter Claims 4, 14 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the cited prior art does not teach a structured surface of an LED, the structures having a height of less than 1um in context with the rest of the claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVREN SEVEN whose telephone number is (571)270-5666. The examiner can normally be reached Mon-Fri 8:00- 5:00 Pacific. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EVREN SEVEN/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Dec 21, 2023
Application Filed
Feb 09, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
82%
With Interview (+8.3%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 723 resolved cases by this examiner. Grant probability derived from career allow rate.

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