Prosecution Insights
Last updated: July 17, 2026
Application No. 18/392,194

Nonlinear Gate Vertical Transistor

Non-Final OA §103
Filed
Dec 21, 2023
Priority
Dec 22, 2022 — EU 22216008.7 +1 more
Examiner
SHAMSUZZAMAN, MOHAMMED
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nexperia B.V.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
738 granted / 911 resolved
+13.0% vs TC avg
Strong +55% interview lift
Without
With
+55.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
37 currently pending
Career history
935
Total Applications
across all art units

Statute-Specific Performance

§103
93.0%
+53.0% vs TC avg
§102
2.4%
-37.6% vs TC avg
§112
2.0%
-38.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 911 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Group I, claims 1-16 in the reply filed on 04/13/2026 is acknowledged. The traversal is on the ground(s) that search and examination of the entire application can be made without serious burden. This is not found persuasive because the claims of Group I and Group II require two separate searches in two separate fields and CPC symbols, the requirement is still deemed proper and is therefore made FINAL. Moreover the search require a different field of search (e.g., searching different subclasses or electronic resources or non patent language, or deploying different search queries); and/or the prior art applicable to one group would not likely be applicable to another group; and/or the groups are likely to raise different non-prior art issues under U.S.C. 101 and/or 35 U.S.C. 112, first paragraph. Claims 17-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 04/13/2026. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-16 are rejected under 35 U.S.C. 103 as being obvious over Shibib et al (US 2020/02343656 A1). Regarding claim 1: Shibib teaches in Fig. 6 about a trench transistor, comprising: PNG media_image1.png 656 700 media_image1.png Greyscale a gate region 111; an oxide region 625 adjacent to the gate region; a semiconductor region 620 adjacent to the oxide region (as shown); wherein the semiconductor region comprises a channel body region [0027] along a gate- oxide-semiconductor boundary, wherein the channel body region is configured to conduct current along the gate-oxide-semiconductor boundary when the transistor is turned on; and wherein the gate-oxide-semiconductor boundary has a nonlinear shape (as shown). The recitation of “wherein the channel body region is configured to conduct current along the gate-oxide-semiconductor boundary when the transistor is turned on” does not distinguish the present invention over the prior art of Shibib who teaches the structure as claimed. The Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP §2114. Regarding claim 2: Shibib teaches in Fig. 6 wherein the nonlinear shape comprises a piecewise linear shape (as shown 625 gas an upper linear piece and a lower linear piece). Regarding claim 3: Shibib teaches in Fig. 6 wherein the oxide region is immediately adjacent to the gate region. Regarding claim 4: Shibib teaches in Fig. 6 wherein the semiconductor region is immediately adjacent to the oxide region. Regarding claim 5: Shibib teaches in [0003] wherein the trench transistor is a trench gate power metal-oxide-semiconductor field effect transistor. Regarding claim 6: Shibib teaches in Fig. 6 wherein the semiconductor region is an epitaxial region. Regarding claim 7: Shibib teaches in Fig. 6 and [0028] wherein the trench transistor is a trench vertical transistor. Regarding claim 8: Shibib teaches in Fig. 6 wherein the piecewise linear shape is a periodic rectangular shape. Regarding claim 9: Shibib teaches in Fig. 6 wherein the oxide region is immediately adjacent to the gate region. Regarding claim 10: Shibib teaches in Fig. 6 wherein the semiconductor region is immediately adjacent to the oxide region. Regarding claim 11: Shibib teaches in [0003] wherein the trench transistor is a trench gate power metal-oxide-semiconductor field effect transistor. Regarding claim 12: Shibib teaches in Fig. 6 wherein the semiconductor region is an epitaxial region. Regarding claim 13: Shibib teaches in Fig. 6 and [0028] wherein the trench transistor is a trench vertical transistor. Regarding claim 14: Shibib teaches in Fig. 6 wherein the oxide region is immediately adjacent to the gate region. Regarding claim 15: Shibib teaches in Fig. 6 wherein the semiconductor region is immediately adjacent to the oxide region. Regarding claim 16: Shibib teaches in [0003] wherein the trench transistor is a trench gate power metal-oxide-semiconductor field effect transistor. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Dec 21, 2023
Application Filed
Jun 01, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+55.3%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 911 resolved cases by this examiner. Grant probability derived from career allowance rate.

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