DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites “the field-effect transistor has a signal-to-noise ratio of at least 0 dB up to at least 100 kHz.” The intended meaning of the limitation could not be determined.
Claim 14 recites “a cis reservoir; a trans reservoir; and a cis electrode and a trans electrode configured to generate a potential difference to translocate an analyte through the nanopore. The intended meaning of cis reservoir and trans reservoir are unclear.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 8-13, and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sauer et al. (U.S. Patent No. 8,232,582).
Regarding to claim 1, Sauer teaches a nanopore sensing device, comprising:
a nanopore having a first orifice and second orifice, and a length running from the first to the second orifice (Fig. 19, element 210, column 11, lines 47-49); and
one or more sensors for sensing an electric feature in the nanopore (Fig. 19, stack 192-206, column 11, lines 26-27);
wherein the nanopore sensing device comprises a plurality of sensing layers arranged along the length, each sensing layer is part of one of the sensors (Fig. 19), and each adjacent pair of sensing layers is separated by a respective isolating layer (column 11, lines 26-27, the oxide layer of the center transistor is isolating layer which separates the top and the bottom transistor), and wherein at least one of the sensors is a field-effect transistor (column 11, lines 26-27, three FETs).
Regarding to claim 2, Sauer teaches the field-effect transistor has a subthreshold swing at room temperature that is less than or equal to 150 mV/dec (column 16, lines 48-49).
Regarding to claim 4, Sauer teaches the field-effect transistor is at least one of a nanopore field-effect transistor or an extended-gate field-effect transistor (Fig. 23, nanopore field-effect transistor).
Regarding to claim 5, Sauer teaches at least two of the sensing layers have one or two contacts in common (Fig. 19, there transistors, 4 contacts).
Regarding to claim 8, Sauer teaches the nanopore has a width between 1 and 200 nm (column 10, lines 50-51).
Regarding to claim 9, Sauer teaches the nanopore has a section defined between an uppermost sensing layer and a lowermost sensing layer of the sensing layers, wherein the section has a substantially constant width and substantially uniform sidewalls (Fig. 19).
Regarding to claim 10, Sauer teaches the nanopore has a width above the uppermost sensing layer or below the lowermost sensing layer that is increased relative to the width of the nanopore between the uppermost sensing layer and the lowermost sensing layer (Fig. 19, width below the lowermost sensing layer that is increased relative to the width of the nanopore between the uppermost sensing layer and the lowermost sensing layer).
Regarding to claim 11, Sauer teaches a readout circuit having a bandwidth of at least 10 kHz (column 8, lines 44-45).
Regarding to claim 12, Sauer teaches the field-effect transistor has a signal-to-noise ratio of at least 0 dB up to at least 100 kHz (column 8, lines 44-46).
Regarding to claim 13, Sauer teaches a system comprising: the nanopore sensing device of claim 1 and a microfluidic system coupled to the nanopore of the sensing device (column 6, lines 6-15).
Regarding to claim 15, Sauer teaches the nanopore has a section defined between an uppermost sensing layer and a lowermost sensing layer of the sensing layers of the nanopore sensing device, wherein the section has a substantially constant width and substantially uniform sidewalls (Fig. 19).
Regarding to claim 16, Sauer teaches the nanopore has a width above the uppermost sensing layer or below the lowermost sensing layer that is increased relative to the width of the nanopore between the uppermost sensing layer and the lowermost sensing layer (Fig. 19, width below the lowermost sensing layer that is increased relative to the width of the nanopore between the uppermost sensing layer and the lowermost sensing layer).
Regarding to claim 17, Sauer teaches a method for sensing an analyte, comprising providing an analyte in the nanopore sensing device of claim 1; translocating the analyte through the nanopore of the nanopore sensing device; and sensing an electric feature of the nanopore as the analyte translocates therethrough (Fig. 1, Fig. 19, column 7, lines 22-26).
Regarding to claim 18, Sauer teaches based on the sensed electric feature, determining at least one of a speed or a length of the analyte longitudinal to the nanopore (column 7, lines 19-21, lines 48-52).
Regarding to claim 19, Sauer teaches the nanopore has a section defined between an uppermost sensing layer and a lowermost sensing layer of the sensing layers of the nanopore sensing device, wherein the section has a substantially constant width and substantially uniform sidewalls (Fig. 19).
Regarding to claim 20, Sauer teaches the nanopore has a width above the uppermost sensing layer or below the lowermost sensing layer that is increased relative to the width of the nanopore between the uppermost sensing layer and the lowermost sensing layer (Fig. 19, width below the lowermost sensing layer that is increased relative to the width of the nanopore between the uppermost sensing layer and the lowermost sensing layer).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sauer et al. (U.S. Patent No. 8,232,582), as applied to claims 1-2 above.
Regarding to claim 3, Sauer discloses the field-effect transistor has a subthreshold swing at room temperature (column 16, lines 41-43). Sauer does not disclose the subthreshold swing at room temperature is less than or equal to 60 mV/dec. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the subthreshold swing at room temperature to be less than or equal to 60 mV/dec in order to increase sensitivity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sauer et al. (U.S. Patent No. 8,232,582), as applied to claim 1 above, in view of Peng et al. (U.S. Patent No. 9,758,821).
Regarding to claim 6, Sauer does not disclose at least one of the sensing layers is a conductor layer. Peng discloses at least one of the sensing layers is a conductor layer (Fig. 4, element 104, column 4, line 27). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sauer in view of Peng to configure at least one of the sensing layers to be a conductor layer in order to increase range of detection.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Sauer et al. (U.S. Patent No. 8,232,582), as applied to claim 1 above.
Regarding to claim 7, Sauer discloses the isolating layers have respective thicknesses (Fig. 19). Sauer does not disclose the isolating layers have respective thicknesses between 2 nm and 100 nm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the isolating layers having respective thicknesses between 2 nm and 100 nm in order to reduce stress, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Sauer et al. (U.S. Patent No. 8,232,582), as applied to claims 1 and 13 above, in view of Peng et al. (U.S. Patent No. 9,758,821).
Regarding to claim 14, Sauer does not disclose a cis reservoir; a trans reservoir; and a cis electrode and a trans electrode configured to generate a potential difference to translocate an analyte through the nanopore. Peng discloses a cis reservoir (Fig. 4, element 211), a trans reservoir (Fig. 4, element 212); and a cis electrode (Fig. 4, element 215) and a trans electrode (Fig. 4, element 214) configured to generate a potential difference to translocate an analyte through the nanopore (Fig. 4, column 5, lines 3-6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sauer in view of Peng to configure a cis reservoir, a trans reservoir, and a cis electrode and a trans electrode for generating a potential difference to translocate an analyte through the nanopore in order to prevent leaking.
Pertinent Art
For the benefits of the Applicant, US-8828138-B2, US-11789006-B2, US-9285339-B2, US-9945836-B2, US-20150014752-A1, US-8698481-B2, and US-9034637-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose each adjacent pair of sensing layers is separated by a respective isolating layer, and wherein at least one of the sensors is a field-effect transistor, wherein the field-effect transistor has a subthreshold swing at room temperature that is less than or equal to 150 mV/dec.
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
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