Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 5-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee, US 2022/0139939.
Lee shows the invention as claimed including a semiconductor memory device comprising:
A pass gate (PAG);
A plurality of active pillars (DST or PAP) respectively disposed in a plurality of active holes included in the pass gate; and
A gate stack STA, the pass gate disposed over the gate stack in a first direction, wherein the gate stack includes a plurality of conductive patterns (CP1, CP2, CP3) spaced apart from each other in the first direction and stacked in the first direction (see. for example, fig. 1B and its description, particularly paragraphs 0024-0088).
With respect to dependent claim 2, note that Lee discloses a first pass gate insulating layer (see, for example, PL3) disposed between each of the plurality of active pillars and the pass gate.
Concerning dependent claim 5, note that the memory device further comprises a semiconductor pattern SML surrounding a sidewall of the pass gate at a level where the plurality of active pillars are disposed; and a second pass gate insulating layer (see side of DLa abutting layer SML) interposed between the semiconductor pattern and the pass gate (see fig. 1B).
Regarding dependent claim 6, note that Lee discloses wherein the gate stack includes a contact region (for example, WC1) overlapping the plurality of active pillars and a cell array region extending from the contact region, and the plurality of conductive patterns are formed in a stepped structure in the contact region of the gate stack (see fig. 1B).
With respect to dependent claim 7, note that Lee discloses wherein the gate stack includes a plurality of pad portions forming a stepped structure (see stepped portion on right hand side of STA in fig. 1B), and the plurality of pad portions are configured by an end of the plurality of conductive patterns and respectively overlap the plurality of active pillars (see, for example, PAP).
Concerning dependent claim 8, Lee discloses: a channel pillar CEP disposed in a channel hole of the gate stack; and a memory layer MEL between the channel pillar and the gate stack, wherein the gate stack includes a contact region (see, for example, WC1) overlapping the plurality of active pillars (see, for example, PEP) and a cell array region extending from the contact region in a second direction toward which a side of the plurality of active pillars faces, and the channel hole passes through the plurality of conductive patterns in the cell array region of the gate stack (see fig. 1B and paragraphs 0024-0088).
Allowable Subject Matter
Claims 3-4 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, particularly Lee, US 2022/0139939, either singly or in combination, fails to anticipate or render obvious, the limitations of, in combination with the additional claim limitations: a first junction facing the gate stack and a second junction facing a direction opposite to that of the first junction, as required by dependent claim 3. Moreover, the prior art, particularly Lee, US 2022/0139939. also fails to suggest, in combination with the additional claim limitations: wherein each of the plurality of gate contact plugs connects a corresponding active pillar among the plurality of active pillars to a corresponding conductive pattern among the plurality of conductive patterns, as required by dependent claim 4. Furthermore, the prior art, particularly Lee, US 2022/0139939. fails to suggest, in combination with the additional claim limitations: a doped semiconductor layer spaced apart from the pass gate in a second direction toward which a side of the plurality of active pillars faces; a channel pillar disposed between the peripheral circuit structure and the doped semiconductor layer, extending in the first direction, and connected to the doped semiconductor layer; and a memory layer surrounding a side of the channel pillar, wherein the plurality of conductive patterns extend between the doped semiconductor layer and the peripheral circuit structure to surround the memory layer, as required by dependent claim 9.
Claims 10-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, particularly Lee, US 2022/0139939, either singly or in combination, fails to anticipate or render obvious, the limitations of, in combination with the additional claim limitations: a doped semiconductor layer spaced apart from the peripheral circuit structure in the first direction and overlapping the second region of the peripheral circuit structure; a gate stack including a contact region between the first region of the peripheral circuit structure and the pass gate, and a cell array region extending from the contact region to overlap the second region of the peripheral circuit structure; a channel pillar connected to the doped semiconductor layer and passing through the cell array region of the gate stack; a memory layer between the channel pillar and the gate stack; and a gate contact plug connected to the active pillar and passing through the contact region of the gate stack, as required by independent 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2022/0077182, having a common assignee with the instant invention, discloses a vertically stacked semiconductor memory device (see abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
May 29, 2026
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