Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1, and 4-9 have been amended. Claims 1-16 remain pending and are ready for examination.. Claims 10-16 have been added.
Response to Amendment
This Office Action has been issued in response to amendment filed 07/13/2026.
Response to Arguments
Applicant's arguments filed 07/13/2026 have been carefully and fully considered. With respect to applicant’s argument of the remarks which recites:
“Berner has no concept of disabling a slave – every identified controller simply receives its operating program”
Examiner agrees and has withdrawn the 102 rejection, and based on amendments now rejections independent claim 1 over Berner et al. (US20010030101, herein Berner), in view of Liu et al. (US20080276258, herein Liu). Where Liu clearly discloses enabling and disabling devices.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, and 10-16 are rejected under 35 U.S.C. 103 as being unpatentable over Berner et al. (US20010030101, herein Berner), in view of Liu et al. (US20080276258, herein Liu).
Regarding claim 1, Berner teaches A semiconductor processing apparatus ([0007] FIG. 1 is an isometric view of the semiconductor workpiece processing tool), comprising: a plurality of process modules, each of them configured to process wafers ([0286] The workpiece process tool may comprise several different modules for performing a variety of manufacturing process steps on the workpiece or semiconductor wafer) ; and each of the plurality of process modules comprising: a plurality of slaves configured to receive and process wafers ([0016] FIG. 15 is a functional block diagram of a master/slave control configuration of an interface module control subsystem for controlling a workpiece cassette interface module of the processing tool, [0022] FIG. 21 is a functional block diagram of a slave processor of the workpiece processing module control subsystem shown in FIG. 18 coupled with components of a workpiece processing module of the processing tool, [0073] Each processing module 20, 22, 24 includes at least one semiconductor workpiece holder such as workpiece holder 810 located generally adjacent the workpiece conveyor 60. In particular, each of the workpiece transport units 62, 64 may deposit a semiconductor workpiece upon a semiconductor workpiece support 401 of the appropriate semiconductor processing module 20, 22, 24, [0078] workpiece transport unit 62 may travel along path 68 to a position adjacent an appropriate processing module 20, 22, 24 for depositing the semiconductor workpiece upon workpiece processing support 401 for processing of the semiconductor workpiece ); and a control unit comprising a processor and a memory, the control unit communicably connected to the plurality of slaves and the control unit configured to configure and control the plurality of slaves ([0022] FIG. 21 is a functional block diagram of a slave processor of the workpiece processing module control subsystem shown in FIG. 18 coupled with components of a workpiece processing module of the processing tool, [0118] The control system 100 is preferably arranged in a hierarchial configuration. The grand master controller 101 includes a processor electrically coupled with a plurality of subsystem control units as shown in FIG. 14. The control subsystems preferably control and monitor the operation of components of the corresponding apparatus (i.e., workpiece conveyor 60, processing modules 20, 22, 24, interface modules 38, 39, etc.). The control subsystems are preferably configured to receive instructional commands or operation instructions such as software code from a respective grand master control 101, 102. The control subsystems 110, 113-119 preferably provide process and status information to respective grand master controllers 101, 102); wherein the processor is configured to read at least one configuration data file from the memory ([0122] grand master controller 101 may write data to a memory location corresponding to master controller 130 and master controller 130 may simultaneously read the data. Alternatively, grand master controller 101 may read data from mapped memory device being written by the master controller 130. Utilizing memory mapped devices 160-161 provides data transfer at processor speeds. Memory mapped device 150 is preferably provided intermediate user interface 30 and the grand master controllers 101, 102 for transferring data therebetween), generate at least one configuration file of the status of the plurality of slaves based on the at least one configuration data file, enable/disable the plurality of slaves according to the generated at least one configuration file, and load applications to control the plurality of slaves ([0129] Upon powering up, the grand master controller 101, 102 may poll the corresponding master controllers 130-132 and download the appropriate operation instruction program to operate each master controller 130-132. Similarly, each master controller 130-132 may poll respective slave controllers 140-147 for identification. Thereafter, the master controller 130-132 may initiate downloading of the appropriate program from the grand master controller 101, 102 to the respective slave controller 140-147 via the master controller 130-132).
Berner does not teach one of the at least one configuration data file containing information of the status of the plurality of slaves… selectively enable and disable the plurality of slaves
Liu teaches one of the at least one configuration data file containing information of the status of the plurality of slaves… selectively enable and disable the plurality of slaves (Fig. 1, [0006] Based on the configuration file, the device model sets the enabled and disabled states of the devices in a guest OS corresponding to it. A guest OS searches hardware upon startup, obtaining device configuration information of the guest OS from a device model through a hypervisor, [0033] in the configuration file, there is a corresponding field to indicate the enabled and disabled states of devices in the description of each device… Upon startup of a device model, a device states field in the configuration file is read by the device model module, and the corresponding registration situation of the device is to be set)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Berner’s teaching semiconductor workpiece processing tool using a master/slave control configuration with Liu’s teaching of dynamically assigning device states. The combined teaching provides an expected result of semiconductor workpiece processing tool using a master/ slave control configuration dynamically assigning device states. Therefore, one of ordinary skill in the art would be motivated to provide more flexibility in the system by dynamically assigning devices and permitting configuration changes without having to reboot as shown in Liu [0008].
Regarding claim 2, the combination of Berner and Liu teach The apparatus according to claim 1, wherein one of the at least one configuration data file is configured to contain information of the status of the plurality of slaves (Berner, [0129] Upon powering up, the grand master controller 101, 102 may poll the corresponding master controllers 130-132 and download the appropriate operation instruction program to operate each master controller 130-132. Similarly, each master controller 130-132 may poll respective slave controllers 140-147 for identification. Thereafter, the master controller 130-132 may initiate downloading of the appropriate program from the grand master controller 101, 102 to the respective slave controller 140-147 via the master controller 130-132, [0118] The control subsystems 110, 113-119 preferably provide process and status information to respective grand master controllers 101, 102).
Regarding claim 3, Berner teaches The apparatus according to claim 1, wherein the processor is further configured to generate a topology of the plurality of slaves (Berner, Fig. 18, [0127] Referring to FIG. 15, the master/slave control subsystem for the interface module control 110 is illustrated. Each master and related slave configuration preferably corresponds to a single module (i.e., interface, conveyor, processing) within the processing tool 10. However, one master may control or monitor a plurality of modules. The master/slave configuration depicted in FIG. 15 and corresponding to the interface module control 110 may additionally apply to the other modular control subsystems 113, 114, 115, [0128] The master controller 130 is coupled with a plurality of slave controllers 140, 141, 142. Sixteen slave controllers may be preferably coupled with a single master controller 130-132 and each slave controller may be configured to control and monitor a single motor or process component, or a plurality of motors and process components, [0129] Upon powering up, the grand master controller 101, 102 may poll the corresponding master controllers 130-132 and download the appropriate operation instruction program to operate each master controller 130-132. Similarly, each master controller 130-132 may poll respective slave controllers 140-147 for identification. Thereafter, the master controller 130-132 may initiate downloading of the appropriate program from the grand master controller 101, 102 to the respective slave controller 140-147 via the master controller 130-132, [0289] general arrangements and configurations of the workpiece processing stations and their combination into a multi-workpiece processing station unit may be applied to a variety of processes used in manufacturing).
Regarding claim 4, Berner teaches The apparatus according to claim 1, wherein the control unit further comprises a first control unit and a second control unit; and wherein the second control unit communicably connected to the first control unit is communicably connected to the plurality of slaves in series or in parallel (Berner, Fig. 18, [0122] Each memory mapped device 150, 160-162 within the control system 100 is preferably a dual port RAM provided by Cypress for asynchronouosly storing data. In particular, grand master controller 101 may write data to a memory location corresponding to master controller 130 and master controller 130 may simultaneously read the data. Alternatively, grand master controller 101 may read data from mapped memory device being written by the master controller 130. Utilizing memory mapped devices 160-161 provides data transfer at processor speeds. Memory mapped device 150 is preferably provided intermediate user interface 30 and the grand master controllers 101, 102 for transferring data therebetween, [0129] the operation instructions or program code for operating each master controller 130-132 and slave controller 140-147 within the control system 100 may be advantageously stored within the memory of the corresponding grand master controller 101, 102. Upon powering up, the grand master controller 101, 102 may poll the corresponding master controllers 130-132 and download the appropriate operation instruction program to operate each master controller 130-132. Similarly, each master controller 130-132 may poll respective slave controllers 140-147 for identification. Thereafter, the master controller 130-132 may initiate downloading of the appropriate program from the grand master controller 101, 102 to the respective slave controller 140-147 via the master controller 130-132).
Regarding claim 5, Berner teaches The apparatus according to claim 4, wherein the first control unit comprises a first processor and a first memory, and the second control unit comprises a second processor, and wherein the first processor is configured to read at least one configuration data file from the first memory, (Berner, Fig. 18, [0122] Each memory mapped device 150, 160-162 within the control system 100 is preferably a dual port RAM provided by Cypress for asynchronouosly storing data. In particular, grand master controller 101 may write data to a memory location corresponding to master controller 130 and master controller 130 may simultaneously read the data. Alternatively, grand master controller 101 may read data from mapped memory device being written by the master controller 130. Utilizing memory mapped devices 160-161 provides data transfer at processor speeds. Memory mapped device 150 is preferably provided intermediate user interface 30 and the grand master controllers 101, 102 for transferring data therebetween) , generate at least one configuration file of the status of the plurality of slaves based on the at least one configuration data file, enable/disable the plurality of slaves according to the generated at least one configuration file, and load applications in the second processor to control the plurality of slaves ([0129] Upon powering up, the grand master controller 101, 102 may poll the corresponding master controllers 130-132 and download the appropriate operation instruction program to operate each master controller 130-132. Similarly, each master controller 130-132 may poll respective slave controllers 140-147 for identification. Thereafter, the master controller 130-132 may initiate downloading of the appropriate program from the grand master controller 101, 102 to the respective slave controller 140-147 via the master controller 130-132).
Regarding claim 10, the combination of Berner and Liu teach The apparatus according to claim 1,
Liu further teaches wherein the information of the status of the plurality of slaves comprises information indicating which of the plurality of slaves are enabled and which of the plurality of slaves are disabled (Fig. 1, [0006] Based on the configuration file, the device model sets the enabled and disabled states of the devices in a guest OS corresponding to it. A guest OS searches hardware upon startup, obtaining device configuration information of the guest OS from a device model through a hypervisor, [0033] in the configuration file, there is a corresponding field to indicate the enabled and disabled states of devices in the description of each device… Upon startup of a device model, a device states field in the configuration file is read by the device model module, and the corresponding registration situation of the device is to be set).
Regarding claim 11, the combination of Berner and Liu teach The apparatus according to claim 1,
Liu further teaches wherein the at least one configuration data file comprises a configuration raw file, and the generated at least one configuration file comprises a configuration matrix generated based on the configuration raw file ([0033] All the enabled and disabled states of hardware with respect to a corresponding guest OS are configured in a configuration file. Based on the configuration file, a device model module virtualizes all the hardware information, and sets the enabled and disabled states of devices in corresponding guest OS in the device state module… A device state module is added for realizing recordation of enabled and disabled states of devices and changing the registration situations of devices in the hardware space. In the configuration file, there is a corresponding field to indicate the enabled and disabled states of devices in the description of each device). (i.e. the configuration file is interpreted to be raw as it provides data which is then processed, and the model generated is interpreted as a matrix as it organizes configuration data on a device by device basis such as the enabled/disabled state of each device)
Regarding claim 12, the combination of Berner and Liu teach The apparatus according to claim 1,
Liu further teaches wherein, when one of the plurality of slaves becomes temporarily unavailable or unnecessary, the at least one configuration data file is updated to omit said one of the plurality of slaves, and the processor generates the at least one configuration file with said one of the plurality of slaves disabled ([0034] At the same time, the state of the device will be changed to be enabled in a corresponding configuration file. If a device is to be deleted through the command, the device is disabled in the device state module corresponding to the guest OS, that is, the registration of device in the hardware space will be cancelled. At the same time, the state of the device will be changed to be disabled in a corresponding configuration file).
Regarding claim 13, the combination of Berner and Liu teach The apparatus according to claim 1, wherein the at least one configuration data file further contains one or more additional file names for detailed information for configuring the process module ([0033] each guest OS being created, a corresponding configuration file and a device model are generated… In the configuration file, there is a corresponding field to indicate the enabled and disabled states of devices in the description of each device). (i.e. file name is interpreted as the identifier (device description/field in the file))
Regarding claim 14, the combination of Berner and Liu teach The apparatus according to claim 11, wherein the configuration matrix comprises a final configuration matrix generated by transforming an empty configuration matrix based on the configuration raw file ([0033] As each guest OS being created, a corresponding configuration file and a device model are generated. All the enabled and disabled states of hardware with respect to a corresponding guest OS are configured in a configuration file. Based on the configuration file, a device model module virtualizes all the hardware information, and sets the enabled and disabled states of devices in corresponding guest OS in the device state module… Upon startup of a device model, a device states field in the configuration file is read by the device model module, and the corresponding registration situation of the device is to be set). (i.e. the initial generated device model is interpreted as the empty configuration matrix as the operative device-state configuration has not been generated, and reading the configuration file and setting the states is interpreted as transforming the initial matrix into the final configuration matrix).
Regarding claim 15, the combination of Berner and Liu teach The apparatus according to claim 12, wherein the processor is configured to automatically generate the at least one configuration file and selectively enable and disable the plurality of slaves in response to the update of the at least one configuration data file ([0033] As each guest OS being created, a corresponding configuration file and a device model are generated. All the enabled and disabled states of hardware with respect to a corresponding guest OS are configured in a configuration file. Based on the configuration file, a device model module virtualizes all the hardware information, and sets the enabled and disabled states of devices in corresponding guest OS in the device state module… Upon startup of a device model, a device states field in the configuration file is read by the device model module, and the corresponding registration situation of the device is to be set, [0017] The dynamic assigning device command program can change a configuration file and the states of the input/output devices in the device state module simultaneously, [0022] The operations of configuration files of the guest operating systems are performed by the dynamic assigning device command simultaneously, so as to modify the enabled and disabled states of the corresponding devices).
Regarding claim 16, the combination of Berner and Liu teach The apparatus according to claim 12, wherein the processor updates configuration of the plurality of slaves by reading the updated at least one configuration data file from the memory, generating the at least one configuration file based on the updated at least one configuration data file, and selectively enabling and disabling the plurality of slaves according to the generated at least one configuration file ([0033] As each guest OS being created, a corresponding configuration file and a device model are generated. All the enabled and disabled states of hardware with respect to a corresponding guest OS are configured in a configuration file. Based on the configuration file, a device model module virtualizes all the hardware information, and sets the enabled and disabled states of devices in corresponding guest OS in the device state module… Upon startup of a device model, a device states field in the configuration file is read by the device model module, and the corresponding registration situation of the device is to be set… a dynamic assigning device command program which changes the states of devices. After startup of the system, the states of devices in the configuration file and the registration situations of devices in the device state module can be changed directly through the command program… devices can be assigned to a guest OS dynamically at run time by changing the enabled and disabled states of the devices at any time).
Claim(s) 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Berner et al. (US20010030101, herein Berner), in view of Liu et al. (US20080276258, herein Liu), and in further view of Inuo et al. (US20090300324A1, herein Inuo).
Regarding claim 6, the combination of Berner and Liu teach A semiconductor processing apparatus (Berner, [0007] FIG. 1 is an isometric view of the semiconductor workpiece processing tool), comprising: a plurality of process modules, each of them configured to process wafers ([0286] The workpiece process tool may comprise several different modules for performing a variety of manufacturing process steps on the workpiece or semiconductor wafer); and each of the plurality of process modules comprising: a plurality of slaves configured to receive and process wafers ([0016] FIG. 15 is a functional block diagram of a master/slave control configuration of an interface module control subsystem for controlling a workpiece cassette interface module of the processing tool, [0022] FIG. 21 is a functional block diagram of a slave processor of the workpiece processing module control subsystem shown in FIG. 18 coupled with components of a workpiece processing module of the processing tool, [0073] Each processing module 20, 22, 24 includes at least one semiconductor workpiece holder such as workpiece holder 810 located generally adjacent the workpiece conveyor 60. In particular, each of the workpiece transport units 62, 64 may deposit a semiconductor workpiece upon a semiconductor workpiece support 401 of the appropriate semiconductor processing module 20, 22, 24, [0078] workpiece transport unit 62 may travel along path 68 to a position adjacent an appropriate processing module 20, 22, 24 for depositing the semiconductor workpiece upon workpiece processing support 401 for processing of the semiconductor workpiece; and a control unit comprising a processor and a memory, and the control unit communicably connected to the plurality of slaves in series or in parallel, the control unit configured to configure and control the plurality of slaves ([0022] FIG. 21 is a functional block diagram of a slave processor of the workpiece processing module control subsystem shown in FIG. 18 coupled with components of a workpiece processing module of the processing tool, [0118] The control system 100 is preferably arranged in a hierarchial configuration. The grand master controller 101 includes a processor electrically coupled with a plurality of subsystem control units as shown in FIG. 14. The control subsystems preferably control and monitor the operation of components of the corresponding apparatus (i.e., workpiece conveyor 60, processing modules 20, 22, 24, interface modules 38, 39, etc.). The control subsystems are preferably configured to receive instructional commands or operation instructions such as software code from a respective grand master control 101, 102. The control subsystems 110, 113-119 preferably provide process and status information to respective grand master controllers 101, 102), wherein the processor is configured to read configuration information from the memory ([0122] grand master controller 101 may write data to a memory location corresponding to master controller 130 and master controller 130 may simultaneously read the data. Alternatively, grand master controller 101 may read data from mapped memory device being written by the master controller 130. Utilizing memory mapped devices 160-161 provides data transfer at processor speeds. Memory mapped device 150 is preferably provided intermediate user interface 30 and the grand master controllers 101, 102 for transferring data therebetween),
Berner does not teach generate a pointer table according to the configuration information and a link table based on the plurality of slaves connected to the control unit in the memory, and connect pointers from the link table to the pointer table according to the configuration information.
Inuo teaches generate a pointer table according to the configuration information and a link table based on the plurality of slaves connected to the control unit in the memory, and connect pointers from the link table to the pointer table according to the configuration information ([0081] Status managing unit 105 also generates each instruction pointer for a plurality of processor elements 107 and a plurality of switching elements 108 in line with the instruction codes in instruction memory 140, [0101]-[0102] Task pointer 154 is a pointer indicative of a task which is currently executed by array type processor 100. Operation start control unit 152 controls the operation start of a task. In this event, operation start control unit 152 selects an executable task from task table 153 to set the selected task in task pointer 154, acquires an intermediate state of processor core 102 from task table 153 to set the intermediate state in status managing unit 105 and data path unit 106, and thereafter outputs an operation start event to status managing unit 105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Berner’s teaching semiconductor workpiece processing tool using a master/slave control configuration with Inuo’s teaching of generating pointer instructions and connects to a table. The combined teaching provides an expected result of semiconductor workpiece processing tool using a master/ slave control configuration generating pointer instructions and connecting to a table. Therefore, one of ordinary skill in the art would be motivated to improve efficiency in fault recovery and as shown in Inuo [0149] improve the availability rate of the processor elements.
Regarding claim 7, the combination of Berner, Liu, and Inuo teach The apparatus according to claim 6, wherein the control unit comprises a first control unit and a second control unit; and the second control unit is communicably connected to the first control unit and communicably connected to the plurality of slaves in series or in parallel (Berner, Fig. 18, [0122] Each memory mapped device 150, 160-162 within the control system 100 is preferably a dual port RAM provided by Cypress for asynchronouosly storing data. In particular, grand master controller 101 may write data to a memory location corresponding to master controller 130 and master controller 130 may simultaneously read the data. Alternatively, grand master controller 101 may read data from mapped memory device being written by the master controller 130. Utilizing memory mapped devices 160-161 provides data transfer at processor speeds. Memory mapped device 150 is preferably provided intermediate user interface 30 and the grand master controllers 101, 102 for transferring data therebetween, [0129] the operation instructions or program code for operating each master controller 130-132 and slave controller 140-147 within the control system 100 may be advantageously stored within the memory of the corresponding grand master controller 101, 102. Upon powering up, the grand master controller 101, 102 may poll the corresponding master controllers 130-132 and download the appropriate operation instruction program to operate each master controller 130-132. Similarly, each master controller 130-132 may poll respective slave controllers 140-147 for identification. Thereafter, the master controller 130-132 may initiate downloading of the appropriate program from the grand master controller 101, 102 to the respective slave controller 140-147 via the master controller 130-132).
Regarding claim 8, the combination of Berner, Liu, and Inuo teach The apparatus according to claim 6, wherein the control unit further comprises a first control unit and a second control unit, and the second control unit comprises a second processor and a second memory (Berner, Fig. 18, [0122] Each memory mapped device 150, 160-162 within the control system 100 is preferably a dual port RAM provided by Cypress for asynchronouosly storing data. In particular, grand master controller 101 may write data to a memory location corresponding to master controller 130 and master controller 130 may simultaneously read the data. Alternatively, grand master controller 101 may read data from mapped memory device being written by the master controller 130. Utilizing memory mapped devices 160-161 provides data transfer at processor speeds. Memory mapped device 150 is preferably provided intermediate user interface 30 and the grand master controllers 101, 102 for transferring data therebetween, [0129] the operation instructions or program code for operating each master controller 130-132 and slave controller 140-147 within the control system 100 may be advantageously stored within the memory of the corresponding grand master controller 101, 102. Upon powering up, the grand master controller 101, 102 may poll the corresponding master controllers 130-132 and download the appropriate operation instruction program to operate each master controller 130-132. Similarly, each master controller 130-132 may poll respective slave controllers 140-147 for identification. Thereafter, the master controller 130-132 may initiate downloading of the appropriate program from the grand master controller 101, 102 to the respective slave controller 140-147 via the master controller 130-132).
Regarding claim 9, the combination of Berner, Liu, and Inuo teach The apparatus according to claim 8, wherein the second processor is configured to receive configuration information from the first control unit, the plurality of slaves connected to the second control unit in the second memory (Berner, Fig. 18, [0122] Each memory mapped device 150, 160-162 within the control system 100 is preferably a dual port RAM provided by Cypress for asynchronouosly storing data. In particular, grand master controller 101 may write data to a memory location corresponding to master controller 130 and master controller 130 may simultaneously read the data. Alternatively, grand master controller 101 may read data from mapped memory device being written by the master controller 130. Utilizing memory mapped devices 160-161 provides data transfer at processor speeds. Memory mapped device 150 is preferably provided intermediate user interface 30 and the grand master controllers 101, 102 for transferring data therebetween, [0129] the operation instructions or program code for operating each master controller 130-132 and slave controller 140-147 within the control system 100 may be advantageously stored within the memory of the corresponding grand master controller 101, 102. Upon powering up, the grand master controller 101, 102 may poll the corresponding master controllers 130-132 and download the appropriate operation instruction program to operate each master controller 130-132. Similarly, each master controller 130-132 may poll respective slave controllers 140-147 for identification. Thereafter, the master controller 130-132 may initiate downloading of the appropriate program from the grand master controller 101, 102 to the respective slave controller 140-147 via the master controller 130-132).
Inuo further teaches generate a pointer table according to the configuration information and a link table based on…, and connect pointers from the link table to the pointer table according to the configuration information ([0081] Status managing unit 105 also generates each instruction pointer for a plurality of processor elements 107 and a plurality of switching elements 108 in line with the instruction codes in instruction memory 140, [0101]-[0102] Task pointer 154 is a pointer indicative of a task which is currently executed by array type processor 100. Operation start control unit 152 controls the operation start of a task. In this event, operation start control unit 152 selects an executable task from task table 153 to set the selected task in task pointer 154, acquires an intermediate state of processor core 102 from task table 153 to set the intermediate state in status managing unit 105 and data path unit 106, and thereafter outputs an operation start event to status managing unit 105).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Fisch (US20190333550) discloses a master/slave configuration data enabling and disabling voltage blocks.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YVONNE T FOLLANSBEE whose telephone number is (571)272-0634. The examiner can normally be reached Monday - Friday 1pm - 9pm.
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/YVONNE TRANG FOLLANSBEE/Examiner, Art Unit 2117
/ALICIA M. CHOI/Primary Patent Examiner, Art Unit 2117
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