DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on April 7th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Election/Restrictions
Applicant's election with traverse of Species I directed to Fig. 11 (claims 1-8 and 10-15) in the reply filed on April 7th, 2026 is acknowledged. The traversal is on ground that the Office fails to identify any generic claims. This is not found persuasive because there is no such requirement for the Office to identify the generic claim for specific. Furthermore, the Office already provided evidence all species are distinct and would be burden to examine all species in the previous office action.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by STUBER (Pub. No.: US 2016/0254231 A1).
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Regarding claim 1, STUBER discloses a semiconductor device in Fig. 12, comprising: a plurality of transistors (active devices 1113 and 1114) in an active layer (semiconductor layer 1101) (see [0055]); a plurality of top vias (vias 1117 and 1118 and a left upper conductive 1115 as shown in Fig. 12 above) in electrical contact between top surfaces of the plurality of transistors and overlying frontside back-end-of-line (BEOL) layers (remaining upper conductive lines 1115 and upper conductive lines 1116) (see [0056]); a local interconnect (a lower conductive line 116) in electrical contact between transistors of the plurality of transistors underneath the plurality of transistors (connecting 3 transistors of active devices 1114) (see [0061]); and a plurality of bottom vias (plurality of lower vias 1118) in electrical contact between bottom surfaces of the plurality of transistors and underlying backside BEOL layers (lower conductive lines 1115).
Regarding claim 2, STUBER discloses the semiconductor device of claim 1, wherein the plurality of bottom vias are electrically isolated from the local interconnect (see annotated Fig. 12 above).
Regarding claim 3, STUBER discloses the semiconductor device of claim 1, further comprising a dielectric cap (insulating layer 1102) formed between the local interconnect and the active layer (see annotated Fig. 12 above and [0055]).
Regarding claim 5, STUBER discloses the semiconductor device of claim 1, wherein a first via of the plurality of top vias (left via 1117 and portion of upper conductive line 1115 as shown in Fig. 12 above), connected to a first transistor of the plurality of transistors (left active device 1113), includes a horizontal part (left upper conductive line 1115) that extends laterally over a second transistor of the plurality of transistors (the adjacent active device 1113) (see Fig. 12 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over STUBER (Pub. No.: US 2016/0254231 A1) as applied to claim 1 above, and further in view of Dyer et al. (Pub. No. US 2008/0054313 A1), hereinafter as Dyer
Regarding claim 8, STUBER discloses the semiconductor device of claim 1, wherein each of the plurality of bottom vias (each of plurality of lower vias 1118) have has a first portion (upper portion) proximate to the active layer (semiconductor layer 1101) with a first width (width of the upper portion) and a second portion (lower portion) with a second width (width of the lower portion) farther away from the active layer (see Fig. 12 above).
STUBER fails to disclose the second width is greater than the first width.
Dyer discloses a semiconductor device in Fig. 16 comprising each of a plurality of bottom vias (back contacts 71 and 77) have has a first portion (upper portions) proximate to the active layer (semiconductor device layer 12) with a first width (width of the upper portions) and a second portion (lower portions) farther away from the active layer with a second width (width of the lower portions) greater than the first width (back contacts 71 and 77 has taper shape) (see [0030-0031] and [0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the shape and dimension of each of the plurality of bottom vias of STUBER to have the second width greater than the first width as same as the semiconductor device of Dyer because the modified structure often caused by the method of etching and the modified structure also provide a more uniform conductive via with less airgap or void.
Claims 10-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over STUBER (Pub. No.: US 2016/0254231 A1) as applied to claim 1 above, and further in view of Dyer et al. (Pub. No. US 2008/0054313 A1), hereinafter as Dyer
Regarding claim 10, STUBER discloses a semiconductor device in Fig. 12, comprising: a plurality of transistors (active devices 1113 and 1114) in an active layer (semiconductor layer 1101) (see [0055]); a plurality of top vias (vias 1117 and 1118 and a left upper conductive 1115 as shown in Fig. 12 above) in electrical contact between top surfaces of the plurality of transistors and overlying frontside back-end-of-line (BEOL) layers (remaining upper conductive lines 1115 and upper conductive lines 1116) (see [0056]); a local interconnect (a lower conductive line 116) in electrical contact between transistors of the plurality of transistors underneath the plurality of transistors (connecting 3 transistors of active devices 1114) (see [0061]); a dielectric cap (insulating layer 1102) formed between the local interconnect and the active layer (see annotated Fig. 12 above and [0055]); and a plurality of bottom vias (plurality of lower vias 1118) in electrical contact between bottom surfaces of the plurality of transistors and underlying backside BEOL layers (lower conductive lines 1115); each of the plurality of bottom vias (each of plurality of lower vias 1118) have has a first portion (upper portion) proximate to the active layer (semiconductor layer 1101) with a first width (width of the upper portion) and a second portion (lower portion) with a second width (width of the lower portion) farther away from the active layer (see Fig. 12 above).
STUBER fails to disclose the second width is greater than the first width.
Dyer discloses a semiconductor device in Fig. 16 comprising each of a plurality of bottom vias (back contacts 71 and 77) have has a first portion (upper portions) proximate to the active layer (semiconductor device layer 12) with a first width (width of the upper portions) and a second portion (lower portions) farther away from the active layer with a second width (width of the lower portions) greater than the first width (back contacts 71 and 77 has taper shape) (see [0030-0031] and [0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the shape and dimension of each of the plurality of bottom vias of STUBER to have the second width greater than the first width as same as the semiconductor device of Dyer because the modified structure often caused by the method of etching and the modified structure also provide a more uniform conductive via with less airgap or void.
Regarding claim 11, the combination of STUBER and Dyer discloses the semiconductor device of claim 10, wherein the plurality of bottom vias are electrically isolated from the local interconnect (see annotated Fig. 12 of STUBER above).
Regarding claim 13, the combination of STUBER and Dyer discloses the semiconductor device of claim 10, wherein a first via of the plurality of top vias (left via 1117 and portion of upper conductive line 1115 as shown in Fig. 12 above), connected to a first transistor of the plurality of transistors (left active device 1113), includes a horizontal part (left upper conductive line 1115) that extends laterally over a second transistor of the plurality of transistors (the adjacent active device 1113) (see Fig. 12 above).
Allowable Subject Matter
Claims 4, 6-7, 12 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
Further comprising a backside interlayer dielectric between the underlying backside BEOL layers and the local interconnect, wherein the dielectric cap is formed from a first dielectric material and the backside interlayer dielectric is formed from a second dielectric material different from the first dielectric material as in claims 4 and 12.
Wherein the first via is in electrical contact with a source/drain structure of the first transistor and the local interconnect is in electrical contact with a source/drain of the second transistor as recited in claims 6 and 14.
Wherein the first via is in electrical contact with a gate of the first transistor and the local interconnect is in electrical contact with a source/drain structure of the second transistor as recited in claims 7 and 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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