DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 6-17 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected related products, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/17/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fei Zhou et al. (US 20170125305 A1) hereinafter referred to as “Zhou”, further in view of Hui-Chi Chen et al. (US 20220384260 A1) hereinafter referred to as “Chen”.
Regarding Claim 1, Zhou teaches
A semiconductor device (Fig 18), comprising:
a substrate (400) including a core region (core region II, Para. [0027]) and a peripheral region (peripheral region I, Para. [0027]);
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a first conductive pattern (right side of Fig. 18 or see diagrams) including a first stacked structure comprising a first gate layer (second interface layer 426) and a first gate electrode (429) over the substrate of the core region (II), and including a first high-k layer (427 Para. [0111]) interposed at an interface between the first gate layer (426) and the first gate electrode (429 Fig. 18); and
a second conductive pattern (left of Fig. 18 or see diagrams) including a second stacked structure comprising a second gate dielectric layer (470 Para. [0077]) and a second gate electrode (419) over the substrate of the peripheral region, and including a second high-k layer (417 Para. [0111]) interposed at an interface between the second gate dielectric layer (470) and the second gate electrode (419) and covering sidewalls (417 includes portions covering the sidewalls of 419) of the second gate electrode.
Zhou is not relied upon to teach that the first gate layer (Zhou second interface layer 426) is explicitly a first gate dielectric layer
Chen teaches an interface layer where it is a first gate dielectric layer (Fig. 1C element 12 Para. [0011])
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Zhou such that the first gate layer is explicitly a first gate dielectric layer, as described in Chen because dielectric material is a known substitution that serve the same function of an interface layer. (Chen Para. [0011])
Regarding Claim 2 Zhou in view of Chen teach the semiconductor device of claim 1,
Zhou further teaches wherein the first conductive pattern (right side of Fig. 18) further includes a first dipole layer (work function layer 428 ) interposed at an interface between the first high-k layer(427) and the first gate electrode (429).
Since a work function layer and a dipole layer complete the same function of controlling the threshold voltage the layers are therefore interchangeable. (Zhou Para. [0115])
Regarding Claim 3 Zhou in view of Chen teaches the semiconductor device of claim 1,
Zhou further teaches wherein the first conductive pattern (right side of Fig. 18) further includes a dipole layer (428)suitable for covering an interface between the first high-k layer(427) and the first gate electrode (429) and covering the sidewalls of the first gate electrode.(428 does cover the sidewalls of 429 Fig. 18)
Since a work function layer and a dipole layer complete the same function of controlling the threshold voltage the layers are therefore interchangeable. (Zhou Para. [0115])
Regarding Claim 4 and claim 5 Zhou in view of Chen teaches the semiconductor device of claim 1,
Zhou further explicitly teaches the limitations of claim 5
wherein the second conductive pattern (Left side of Fig. 18) further includes a second dipole layer (418) interposed between the second high-k layer (417) and the second gate electrode (419) to cover a bottom surface and the sidewalls of the gate electrode.(418 covers the bottom and side walls of 419).
And of claim 4 Zhou explicitly teaches
wherein the second conductive pattern further includes a second dipole layer (418)
Although Zhou does not explicitly teach the following the limitations are obvious design choice
a second dipole layer interposed at an interface between the second high-k layer and the second gate dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Zhou in view of Chen such that the second dipole layer is interposed at an interface between the second high-k layer and the second gate dielectric layer, because the modification is an obvious matter of design choice.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lin; Chih-Hao (US-10453848-B2), Chen; Chang-Yih (US-20250142815-A1), LEE; Jeonil (US-20230178634-A1)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Thursday, 7:30a.m. - 5:00p.m. ET..
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/JAIME LYNN SPRENGER/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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