DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20130001403 (Yamakawa).
Concerning claim 11, Yamakawa discloses a light detecting device comprising (Figs. 3 and 9-13): a first pixel (41-1) including: a first photoelectric conversion region (51-1); a first charge holding region (57) coupled to the first photoelectric conversion region via a first transfer transistor (52-1); a first switch transistor (56-1) configured to couple the first charge holding region to a second charge holding region (58) ([0063]); and a reset transistor (55) coupled to the first charge holding region ([0069]); a second pixel (41-2) including: a second photoelectric conversion region (51-1); and a third charge holding region (59) coupled to the second photoelectric conversion region via a second transfer transistor (52-2); and a pixel connection circuit (33) coupled to the second charge holding region and the third charge holding region (Figs. 11-12 and [0126]).
Continuing to claim 12, Yamakawa discloses wherein the reset transistor is configured to discharge a charge held by the first charge holding region and the second charge holding region by turning on the first switch transistor ([0069]).
Considering claim 13, Yamakawa discloses wherein the reset transistor is configured to discharge a charge held by the third charge holding region by turning on the pixel connection circuit ([0070]-[0071]).
Referring to claim 14, Yamakawa discloses the second pixel does not include a reset transistor (Fig. 9).
Regarding claim 15, Yamakawa discloses wherein the second pixel further comprises a second switch transistor (56-2).
Pertaining to claim 16, Yamakawa discloses wherein the pixel connection circuit comprises a third switch transistor (53).
As to claim 17, Yamakawa discloses wherein, in a top view :a gate of the reset transistor and a gate of the first switch transistor are adjacent to one another in a first direction; and a gate of the second switch transistor and a gate of the third switch transistor are adjacent to one another in the first direction (Fig. 12 and [0126]).
Concerning claim 18, Yamakawa discloses wherein, in the top view, the gates of the reset transistor and the first switch transistor are spaced apart from the gates of the second switch transistor and the third switch transistor in a second direction perpendicular to the first direction ([0124]).
Continuing to claim 19, Yamakawa discloses wherein, in the top view, part of the first pixel is between the gates of the reset transistor and the first switch transistor and the gates of the second switch transistor and the third switch transistor (Fig. 12).
Considering claim 20, Yamakawa discloses wherein the part of the first pixel includes a part of the first photoelectric conversion region (Fig. 12).
Referring to claim 21, Yamakawa discloses wherein, in the top view, part of the first photoelectric conversion region is between the gates of the reset transistor and the first switch transistor and the gates of the second switch transistor and the third switch transistor (Fig. 12).
Regarding claim 22, Yamakawa discloses an electronic apparatus, comprising (Fig. 3): a processing circuit (34); and a light detecting device comprising (Figs. 9-13): a first pixel (41-1) including: a first photoelectric conversion region (51-1); a first charge holding region (57) coupled to the first photoelectric conversion region via a first transfer transistor (52-1); a first switch transistor (56-1) configured to couple the first charge holding region to a second charge holding region (58) ([0063]); and a reset transistor (55) coupled to the first charge holding region ([0069]); a second pixel (41-2) including: a second photoelectric conversion region (51-1); and a third charge holding region (59) coupled to the second photoelectric conversion region via a second transfer transistor (52-2); and a pixel connection circuit (33) coupled to the second charge holding region and the third charge holding region (Figs. 11-12 and [0126]).
Pertaining to claim 23, Yamakawa discloses wherein the reset transistor is configured to discharge a charge held by the first charge holding region and the second charge holding region by turning on the first switch transistor ([0069]).
As to claim 24, Yamakawa discloses wherein the reset transistor is configured to discharge a charge held by the third charge holding region by turning on the pixel connection circuit ([0070]-[0071]).
Concerning claim 25, Yamakawa discloses the second pixel does not include a reset transistor (Fig. 9).
Continuing to claim 26, Yamakawa discloses wherein the second pixel further comprises a second switch transistor (56-2).
Considering claim 27, Yamakawa discloses wherein the pixel connection circuit comprises a third switch transistor (53).
Referring to claim 28, Yamakawa discloses wherein, in a top view :a gate of the reset transistor and a gate of the first switch transistor are adjacent to one another in a first direction; and a gate of the second switch transistor and a gate of the third switch transistor are adjacent to one another in the first direction (Fig. 12 and [0126]).
Regarding claim 29, Yamakawa discloses wherein, in the top view, the gates of the reset transistor and the first switch transistor are spaced apart from the gates of the second switch transistor and the third switch transistor in a second direction perpendicular to the first direction ([0124]).
Pertaining to claim 30, Yamakawa discloses wherein, in the top view, part of the first pixel is between the gates of the reset transistor and the first switch transistor and the gates of the second switch transistor and the third switch transistor (Fig. 12).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20100230579 discloses an imaging device (Fig. 1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/VALERIE N NEWTON/Examiner, Art Unit 2897 02/21/26