Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed February 17, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 8, 14
b. Pending: 1-20
Claims 1-20 have been amended.
Response to Arguments
Applicant's arguments filed February 17, 2026 have been fully considered but while the argument concerning the 103 rejection is persuasive, the argument concerning the 102 rejection is not persuasive. On p.24, Applicant argues that Dutta does not correct the deficiencies of Lin, referring to the argument that Lin does not teach adjusting the bit line voltage based on two metrics. Examiner agrees that Dutta does not teach this. However, Examiner disagrees with the argument on p.23 that Lin does not teach adjusting the bit line voltage based on two metrics. Throughout para. [0164], Lin provides multiple examples of how “The bit line voltages that are applied during predictive programming depend on whether the Vt of the memory cell was between the verify low reference level and the verify high reference level or was above the verify high reference level”. The first metric in each subsequent example in para. [0164] is “whether the Vt of the memory cell was between the verify low reference level and the verify high reference level” and the second metric is whether the Vt of the memory cell was “above the verify high reference level”. If the Applicant were to argue that the comparison of Vt to two different reference level ranges is only one metric, Examiner also points to paras. [0083] and [0133], which indicate that the bit line voltage depends on the state of the latches, which may adjust the program enable voltage applied to the bit lines. This is a second metric. Alternatively, para. [0074] states, “the program enable voltages during predictive programming have a state dependent average magnitude. The number of program pulses during predictive programming, and hence the number of program enable voltages, depends on the target state”, which indicates that the bit line voltages depend on two metrics, the state-dependent magnitude of the program enable voltages and the target-state-dependent number of program enable voltages.
Regardless, Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection relies on newly found references along with previously used references applied in the prior rejection of record. New grounds of rejection are made in view of Kim et al. (US Pub. 20120170373 A1; “Kim”). Kim para. [0047] and Fig. 3 are relevant to claims 1, 8, and 14.
Drawings
The drawings were received on February 17, 2026. These drawings are acceptable.
Specification
The amendments to the Specification have been reviewed and are accepted by the Examiner. The objections to the Specification are withdrawn.
Claim Objections
Claims 11 and 13 are objected to because of the following informality: these claims are marked as “(Original)” but this should be changed to “(Currently Amended)”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US Pub. 20200234768 A1) in view of Kim (US Pub. 20120170373 A1).
Regarding independent claim 1, Lin discloses a memory apparatus (Fig. 1: memory system 100; [0052]), comprising:
memory cells ([0058]: In one embodiment, memory structure 126 comprises a three-dimensional memory array of non-volatile memory cells) configured to store a threshold voltage corresponding to one of a plurality of data states ([0051]: The read voltages are set at levels which are expected to be between the threshold voltage levels of adjacent data states. Examiner concludes that data states correspond to stored threshold voltages); and
a control means (controller 122; [0053]) configured to:
program checkpoint ones and non-checkpoint ones of the memory cells associated with a checkpoint state (in reference to Fig. 5, per [0136]: In step 548, a memory cell may be locked out after the memory cell has been verified (by a test of the Vt) that the memory cell has reached its target state. Such memory cells are referred to as checkpoint memory cells or CP memory cells, in one embodiment. Some memory cells undergo predictive programming after the memory cell's Vt has been verified as having reached a checkpoint state. Such memory cells are referred to herein as non-checkpoint memory cells or “non-CP memory cells.” Examiner notes that step 546, which occurs prior to step 548, is a program pulse application step) of the plurality of data states ([0157]: FIG. 8B depicts programming of the memory cells from the checkpoint states 802, 804, 806, 808 to their respective target states) to at least one of a verify low voltage (Fig. 8B: verify low verify reference level VclA; [0160]) and a verify high voltage (verify high verify reference level VchA; [0160]) for the checkpoint state (CP state 802; [0158]) during a plurality of initial program loops (Fig. 5: step 546; [0132]: In step 546, a program pulse of the program signal Vpgm is applied to the selected word line (the word line selected for programming); [0134]: In step 546, the program pulse is concurrently applied to all memory cells connected to the selected word line so that all of the memory cells connected to the selected word line are programmed concurrently (unless they are inhibited from programming); [0140]: After step 560, the process loops back to step 542 and another program pulse is applied to the selected word line so that another iteration (steps 542-560) of the programming process of FIG. 5 is performed. Examiner concludes that there are a plurality of initial program loops),
adjust a bit line voltage applied to one of a plurality of bit lines coupled to the memory cells being programmed ([0164]: The bit line voltages that are applied during predictive programming depend on whether the Vt of the memory cell was between the verify low reference level and the verify high reference level or was above the verify high reference level, in one embodiment. For example, the bit line voltage during predictive programming of a memory cell being programmed to state S2 or S3 depends on whether the Vt of the memory cell was between VclA to VchA or was above VchA (when the memory cell was verified to have reached its checkpoint state); [0136]: During step 546, the magnitude of the program enable voltage applied to the bit lines of such non-checkpoint memory cells depends on the state to which the non-checkpoint memory cells are being programmed, in one embodiment) and a subsequent quantity of subsequent program loops based on a combination of at least two metrics associated with the memory cells being programmed having the threshold voltage exceeding the at least one of the verify low voltage and the verify high voltage for the checkpoint state associated therewith ([0139]: In step 556, it is determined whether the count from step 554 is less than or equal to a predetermined limit…In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program-erase cycles performed or other criteria; [0140]: If the number of failed memory cells is not less than the predetermined limit, than the programming process continues at step 558 and the program counter PC is checked against the program limit value (PL)…If the program counter PC is less than the program limit value PL, then the process continues at step 560 during which time the Program Counter PC is incremented by 1…After step 560, the process loops back to step 542. Examiner concludes that the number of loops depends on the count of failed cells, or cells that have not achieved their target state, and the predetermined limit of failed cells may change based on errors already counted, which depends on threshold voltage values),
and program the checkpoint ones and the non-checkpoint ones of the memory cells to respective checkpoint states and non-checkpoint states of the plurality of data states by applying each of a plurality of program pulses to each of the memory cells while applying the bit line voltage to one of the plurality of bit lines associated with a given memory cell in each of the subsequent program loops ([0164]), the non-checkpoint ones of the memory cells not verified to determine whether the non-checkpoint ones of the memory cells have reached their respective non-checkpoint states ([0042]: a non-CP memory cell receives one or more additional program pulses to program the memory cell to its target state without verifying that memory cell has reached its target state).
Lin does not explicitly disclose:
adjust a bit line voltage applied to one of a plurality of bit lines coupled to the memory cells being programmed based on a combination of at least two metrics associated with the memory cells being programmed having the threshold voltage exceeding the at least one of the verify low voltage and the verify high voltage for the checkpoint state associated therewith,
However, Kim teaches:
adjust a bit line voltage applied to one of a plurality of bit lines coupled to the memory cells being programmed based on a combination of at least two metrics associated with the memory cells being programmed having the threshold voltage exceeding the at least one of the verify low voltage and the verify high voltage for the checkpoint state associated therewith (in reference to Fig. 3, per [0047]: After A4, a program loop is performed by applying the program permission voltage 0 V, the program inhibition voltage Vcc, or a program suppression voltage, having a level between the program permission voltage 0 V and the program inhibition voltage Vcc, to the bit lines corresponding to memory cells having the threshold voltages reached the first temporary level PV1', the first verification level PV1, the second temporary level PV2', the second verification level PV2, or the third verification level PV3 until the threshold voltages of the selected memory cells reach the first verification level PV1, the second verification level PV2, or the third verification level PV3 (that is, the target levels). Examiner asserts that the at least two metrics are, for example, (1) which threshold voltage level range the memory cells belong to and (2) the target level),
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Kim to Lin
wherein a control means is configured to adjust a bit line voltage applied to one of a plurality of bit lines coupled to the memory cells being programmed based on a combination of at least two metrics associated with the memory cells being programmed having the threshold voltage exceeding the at least one of the verify low voltage and the verify high voltage for the checkpoint state associated therewith in order to suppress an increase in memory cell threshold voltage distribution by performing a verification operation at a higher verification level and adjusting the number of verification levels (Kim, [0007]).
Regarding claim 2, Lin and Kim together disclose the limitations of claim 1, and further through Lin:
wherein the metrics associated with the memory cells being programmed having the threshold voltage exceeding the at least one of the verify low voltage and the verify high voltage for the checkpoint state associated therewith ([0164]) include an initial quantity of the initial program loops needed for one of the memory cells to have the threshold voltage exceeding the verify low voltage and include the threshold voltage of the one of the memory cells relative to the verify high voltage when exceeding the verify low voltage ([0139]-[0140]), and the control means (Fig. 1: 122) is further configured, for each of the memory cells, to:
determine the initial quantity of the initial program loops needed for the one of the memory cells to have the threshold voltage exceeding the verify low voltage ([0139]-[0140]);
determine the threshold voltage of the one of the memory cells relative to the verify high voltage when exceeding the verify low voltage (see explanation of step 1404 below); and
adjust the bit line voltage applied to the one of the plurality of bit lines coupled to the memory cells being programmed (step 1404; [0195]: Step 1404 includes setting an initial state dependent magnitude of the bit line program enable voltage for the memory cell. Examiner asserts that the controller must determine the threshold voltage of the memory cells in order to set a state-dependent bit line voltage) and the subsequent quantity of subsequent program loops based on the initial quantity of the initial program loops needed for the one of the memory cells to have the threshold voltage exceeding the verify low voltage and based on the threshold voltage of the one of the memory cells relative to the verify high voltage when exceeding the verify low voltage ([0139]-[0140]).
Lin does not disclose:
wherein the at least two metrics associated with the memory cells being programmed having the threshold voltage exceeding the at least one of the verify low voltage and the verify high voltage for the checkpoint state associated therewith
However, Kim teaches:
wherein the at least two metrics associated with the memory cells being programmed having the threshold voltage exceeding the at least one of the verify low voltage and the verify high voltage for the checkpoint state associated therewith ([0047])
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Kim to modified Lin wherein the at least two metrics associated with the memory cells being programmed having the threshold voltage exceeding the at least one of the verify low voltage and the verify high voltage for the checkpoint state associated therewith in order to suppress an increase in memory cell threshold voltage distribution by performing a verification operation at a higher verification level and adjusting the number of verification levels (Kim, [0007]).
Regarding claim 3, Lin and Kim together disclose the limitations of claim 1. The first part of claim 3 through “checkpoint state associated therewith” is exactly the same as the first part of claim 2, and is thus rejected for the same reasons. Further, through Lin:
include an initial quantity of the initial program loops needed for one of the memory cells to have the threshold voltage exceeding the verify high voltage ([0139]-[0140]; [0135]: In step 548, memory cells that have reached their target states are locked out from further programming. Step 548 may include performing verifying…the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage. The verify reference voltage is at a lower tail of the target state; [0136]: In step 548, a memory cell may be locked out…Such memory cells are referred to as checkpoint memory cells or CP memory cells. Examiner concludes based on the above and Fig. 8B that the “lower tail of the target state” is equivalent to the verify high reference level, e.g. VchA).
Regarding claim 4, Lin and Kim together disclose the limitations of claim 1. The first part of claim 4 through “checkpoint state associated therewith” is exactly the same as the first part of claims 2 and 3, and is thus rejected for the same reasons. Further, through Lin:
include a status of an analog bitscan operation for the memory cells targeted for one of the plurality of data states associated with one of the memory cells using the verify high voltage for the checkpoint state associated with the one of the plurality of data states ([0089]: The data latches identify when an associated memory cell has reached certain mileposts in a program operation. For example, latches may identify that a memory cell's Vt is below a particular verify voltage…An LDL latch is flipped (e.g., from 0 to 1) when a lower page bit is stored in an associated memory cell. An MDL or UDL latch is flipped when a middle or upper page bit, respectively, is stored in an associated memory cell. This occurs when an associated memory cell completes programming; [0130]: the group of memory cells selected to be programmed (referred to herein as the selected memory cells) are programmed concurrently and are all connected to the same word line (the selected word line); [0135]: the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached the appropriate verify reference voltage. Examiner asserts that a bitscan operation is seen as an equivalent operation to a verification operation of every programmed bit of a selected word line. Thus, Lin discloses a bitscan operation).
Regarding claim 5, Lin and Kim together disclose the limitations of claim 1. The first part of claim 5 through “targeted for one of the plurality of data states” is exactly the same as the first part of claim 4, and is thus rejected for the same reasons. Further, through Lin:
one of the plurality of data states associated with one of the memory cells using the verify low voltage for the checkpoint state associated with the one of the plurality of data states and include the threshold voltage of the one of the memory cells relative to the verify high voltage when exceeding the verify low voltage ([0139]-[0140]), and the control means (Fig. 1: 122) is further configured, for each of the memory cells, to:
determine the status of the analog bitscan operation for the memory cells targeted for the one of the plurality of data states associated with the one of the memory cells using the verify low voltage for the checkpoint state associated with the one of the plurality of data states ([0089]; [0139]-[0140]); and
determine the threshold voltage of the one of the memory cells relative to the verify high voltage when exceeding the verify low voltage ([0195]); and
adjust the bit line voltage applied to the one of the plurality of bit lines coupled to the memory cells being programmed ([0164]; [0087]: processor 192 monitors the read back memory state relative to the desired memory state. When the two are in agreement, the processor 192 sets the bit line in a program inhibit mode such as by updating its latches. Examiner concludes that the bitscan involving latches affects the adjustment of the bit line voltage) and the subsequent quantity of subsequent program loops ([0139]-[0140]. Examiner asserts that per [0089], the indication from the bitscan regarding the “mileposts in a program operation” affect further programming and can therefore determine whether additional program loops are needed) based on the status of the analog bitscan operation for the memory cells targeted for the one of the plurality of data states associated with the one of the memory cells using the verify low voltage for the checkpoint state associated with the one of the plurality of data states ([0089]; [0139]-[0140]) and based on the threshold voltage of the one of the memory cells relative to the verify high voltage when exceeding the verify low voltage ([0195]).
Regarding claim 6, Lin and Kim together disclose the limitations of claim 1. Claim 6 recites substantially the same limitations as claim 4, with an additional mention of an “initial quantity of the initial program loops needed for one of the memory cells to have the threshold voltage exceeding the verify high voltage” from claim 3, and henceforth is rejected for the same reasons as claims 3 and 4.
Independent claims 8 and 14 are substantially the same in claimed subject matter as claim 1 except claim 8 is drafted to focus on the controller, and claim 14 is drafted in method format instead of device format. Independent claims 8 and 14 are thus rejected for the same reasons as independent claim 1.
Regarding claims 9 and 15, Lin and Kim together disclose the limitations of claims 8 and 14, respectively. Claims 9 and 15 recite substantially the same limitations as claim 2, and henceforth are rejected for the same reasons.
Regarding claims 10 and 16, Lin and Kim together disclose the limitations of claims 8 and 14, respectively. Claims 10 and 16 recite substantially the same limitations as claim 3, and henceforth are rejected for the same reasons.
Regarding claims 11 and 17, Lin and Kim together disclose the limitations of claims 8 and 14, respectively. Claims 11 and 17 recite substantially the same limitations as claim 4, and henceforth are rejected for the same reasons.
Regarding claims 12 and 18, Lin and Kim together disclose the limitations of claims 8 and 14, respectively. Claims 12 and 18 recite substantially the same limitations as claim 5, and henceforth are rejected for the same reasons.
Regarding claims 13 and 19, Lin and Kim together disclose the limitations of claims 8 and 14, respectively. Claims 13 and 19 recite substantially the same limitations as claim 6, and henceforth are rejected for the same reasons.
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US Pub. 20200234768 A1) and Kim (US Pub. 20120170373 A1) as applied to claims 1 and 14 above, and further in view of Dutta et al. (US Pub. 20110122692 A1; “Dutta”) .
Regarding claim 7, Lin and Kim together disclose the limitations of claim 1. Kim discloses “at least two metrics” per claims 1-6 above. Further through Lin:
wherein the at least two metrics associated with the memory cells being programmed having the threshold voltage exceeding the at least one of the verify low voltage and the verify high voltage for the checkpoint state associated therewith ([0164]) include determination of a status of an analog bitscan operation for the memory cells targeted for the one of the plurality of data states associated with the one of the memory cells ([0089]), the control means is further configured, as part of an analog bitscan operation, to:
count the memory cells targeted for the one of the plurality of data states associated with the one of the memory cells and having the threshold voltage above a verify level associated with the one of the plurality of data states (Fig. 5: step 550; [0137]: If, in 550, it is determined that all of the memory cells have reached their target threshold voltages (pass), the programming process is complete and successful because all selected memory cells were programmed and verified to their target states. A status of “PASS” is reported in step 552. Otherwise if, in 550, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 554);
determine the status of the analog bitscan operation to be pass in response to the count being less than a bitscan pass fail threshold and determine the status of the analog bitscan operation to be fail in response to the count being greater than a bitscan pass fail threshold (Fig. 5: steps 554 and 556; [0139]: In step 556, it is determined whether the count from step 554 is less than or equal to a predetermined limit. Examiner asserts that the predetermined limit is analogous to a bitscan pass fail threshold);
Lin does not disclose:
measure a busy time necessary to determine whether the status of the analog bitscan operation is one of the pass and the fail; and
determine a magnitude of the one of the pass and the fail based on the busy time.
However, Dutta teaches:
measure a busy time necessary to determine whether the status of the analog bitscan operation is one of the pass and the fail ([0145]: a sampling technique may be used in which a bit scan is performed only on a limited number of storage elements (NAND strings)…The number of storage elements detected can be used as an indication of the total number of storage elements on the entire selected word line (or page) that is above or below the verify level. This can minimize the bit-scan time and hence reduce the performance impact; [0117]: When the condition of FIG. 14c is met, the A-state storage elements are considered to have a status of "pass," indicating that programming of these storage elements has been successfully completed; referring to Fig. 14c and a determination of the threshold voltage level as above or below a target level, [0115] teaches: A bit scan technique discussed further below can be used to determine if either of these conditions is met. Examiner asserts that the bitscan sampling duration must be measured in order to draw conclusions about an entire word line or page); and
determine a magnitude of the one of the pass and the fail based on the busy time ([0145]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Dutta to modified Lin wherein the control means is configured to: measure a busy time necessary to determine whether the status of the analog bitscan operation is one of the pass and the fail; and determine a magnitude of the one of the pass and the fail based on the busy time in order to increase programming speed while decreasing threshold voltage distribution width (Dutta, [0008]).
Regarding claim 20, Lin and Kim together disclose all the limitations of claim 14. Claim 20 recites substantially the same limitations as claim 7, and henceforth is rejected for the same reasons.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.A./Examiner, Art Unit 2824
5/30/2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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