DETAILED ACTION
This Office action responds to Applicant’s election filed on 05/22/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The Applicant’s response on 05/22/2026 in reply to the restriction mailed on 03/24/2026 has been entered. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-34.
Election/Restriction
The Applicant’s response on 05/22/2026 in reply to the restriction/election requirements mailed on 03/24/2026 has been entered. Applicant’s election without traverse of Species 1 corresponding to fig. 3A, and Modification A1 corresponding to figs. 6 and 7B, is acknowledged. Applicant considers that claims 1-2, 4-5, 8-11, 13, 15-19, 21, and 24-28 correspond to Species A1 and Modification A1. Examiner agrees. Claim 16 is withdrawn by corresponding to non-elected species. Claims 3, 6-7, 12, 14, 20, 22-23, and 29-34 are cancelled by the Applicant.
Claim 16 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/22/2026.
Information Disclosure Statement (IDS)
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Specification Objection
The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-5, and 8-10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by or, in alternative, under 35 U.S.C. 103 as obvious over by Edathil (US 2022/0188496).
Regarding claim 1, Edathil shows (see, e.g., Edathil: figs. 1, 3A, 4B, and 5C) all aspects of an integrated circuit 404B, comprising:
A plurality of first power rails GND extending in a first horizontal direction and configured to provide a first power supply voltage that is applied thereto (see MPEP 2112.01 and MPEP 2114.I/2114.II) (MPEP 2114.II: Apparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim)
Initially, and with respect to claim 1, note that a limitation in a claim with respect to the manner in which a claimed device is intended to be used does not differentiate the claimed device from a prior-art device, if the prior-art device teaches all structural limitations in the claim and the limitations are found to be inherent in the prior-art device. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See Hewlett-Packard Co. v. Bausch & Lomb Inc. and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a device claim, and not the patentability of its functions (909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990)). As stated in Best,
Where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Note that the applicant has burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990)
A plurality of second power rails PPWR extending in the first horizontal direction and configured to provide a second power supply voltage that is applied thereto (see MPEP 2112.01 and MPEP 2114.I/2114.II) (MPEP 2114.II: Apparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim)
A power line SPWR in a switch cell area (see, e.g., Edathil: par. [0020]) and extending in the first horizontal direction the power line SPWR being configured to provide a global power supply voltage that is applied thereto (see MPEP 2112.01 and MPEP 2114.I/2114.II) (MPEP 2114.II: Apparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim)
wherein:
The plurality of first power rails GND and the plurality of second power rails PPWR are alternately arranged in a second horizontal direction vertical to the first horizontal direction
The plurality of first power rails GND, the plurality of second power rails PPWR, and the power line SPWR form a front-side pattern on a same layer
The power line SPWR is provided between two second power rails PPWR adjacent to each other in the first horizontal direction, among the plurality of second power rails PPWR
In reference to the language in claim 1 referring to the structure of the device, it is noted that Edathil shows all structural aspects of the package structure according to the instant invention (see paragraph 11 above), and that providing different first and second power supply voltage when the integrated circuit is at different running speeds does not affect the function of the final device. Furthermore, Edathil’s device is configured of performing the claimed functions since the performing function interaction corresponding to content tested would involve a mere manipulation of the structure of the circuit structure.
As to the grounds of rejection of claim 1 under section 103, see MPEP § 2112, which discusses the handling of functional language in the claims and recommends the alternative (§ 102/ § 103) grounds of rejection.
Regarding claim 2, Edathil shows (see, e.g., Edathil: figs. 1, 3A, 4B, and 5C) that the switch cell area (see, e.g., Edathil: par. [0020]) is adjacent to a logic cell area (see, e.g., Edathil: par. [0020]) in which logic cells 414 are provided, and wherein the switch cell area comprises a break region 408 electrically separating the switch cell area from the logic cell area.
Regarding claim 4, Edathil shows (see, e.g., Edathil: figs. 1, 3A, 4B, and 5C) that:
A global back-side pattern (see, e.g., Edathil: par. [0019] - [0023]) configured to provide the global power supply voltage thereto (see MPEP 2112.01 and MPEP 2114.I/2114.II)
A global via structure electrically connecting the power line to the global back-side pattern (see, e.g., Edathil: par. [0019] - [0023])
Regarding claim 5, Edathil shows (see, e.g., Edathil: figs. 1, 3A, 4B, and 5C) that:
A first back-side pattern (see, e.g., Edathil: par. [0019] - [0023]) configured to provide the first power supply voltage (see MPEP 2112.01 and MPEP 2114.I/2114.II)
A second back-side pattern (see, e.g., Edathil: par. [0019] - [0023]) configured to provide the second power supply voltage (see MPEP 2112.01 and MPEP 2114.I/2114.II)
A first via structure electrically connecting the plurality of first power rails to the first back-side pattern (see, e.g., Edathil: par. [0019] - [0023])
A second via structure electrically connecting the plurality of second power rails to the second back-side pattern (see, e.g., Edathil: par. [0019] - [0023])
Regarding claim 8, Edathil shows (see, e.g., Edathil: figs. 1, 3A, 4B, and 5C) that the global back-side pattern, the first back-side pattern, and the second back-side pattern extend in the first horizontal direction (see, e.g., Edathil: fig. 7C).
Regarding claim 9, Edathil shows (see, e.g., Edathil: figs. 1, 3A, 4B, and 5C) that the global back-side pattern, the first back-side pattern, and the second back-side pattern extend in the second horizontal direction (see, e.g., Edathil: fig. 7C).
Regarding claim 10, Edathil shows (see, e.g., Edathil: figs. 1, 3A, 4B, and 5C) that the global via structure and the first via structure are aligned in the second horizontal direction (see, e.g., Edathil: par. [0025]).
Claims 13, 15, 18-19, 21, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Edathil in view of Tsai (US 2023/0069137).
Regarding claim 13, Edathil shows (see, e.g., Edathil: figs. 1, 3A, 4B, and 5C) all aspects of an integrated circuit 404B, comprising:
A plurality of logic cell areas, each of the plurality of logic cell areas comprising a logic cell 414 (see, e.g., Edathil: par. [0020])
A switch cell area between the plurality of logic cell areas (see, e.g., Edathil: par. [0020])
A plurality of first power rails GND extending in a first horizontal direction and configured to provide a first power supply voltage that is applied thereto (see MPEP 2112.01 and MPEP 2114.I/2114.II)
A plurality of second power rails PPWR extending in the first horizontal direction and configured to provide a second power supply voltage that is applied thereto (see MPEP 2112.01 and MPEP 2114.I/2114.II)
wherein:
The switch cell area comprises: a switch cell comprising:
A power line SPWR configured to provide a global power supply voltage that is applied thereto (see MPEP 2112.01 and MPEP 2114.I/2114.II)
A plurality of P-type transistors connected to the plurality of first power rails (see, e.g., Edathil: par. [0080] – [0081], P-type transistors in N-wells)
A switch dummy cell electrically separating the logic cell 414 from the switch cell, and wherein two second power rails adjacent to each other in the first horizontal direction, among the plurality of second power rails, are cut off in the switch cell area.
However, Edathil fails (see, e.g., Edathil: figs. 1, 3A, 4B, and 5C) to show a power tap cell. Tsai, in a similar device to Lee, shows (see, e.g., Tsai: fig. 2B) a power tap. Tsai also shows (see, e.g., Tsai: fig. 2B) that the power tap cell delivers power from the back side to the front side (see, e.g., Tsai: par. [0037]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the power tap cell of Tsai in the device of Edathil in order delivers power from the back side to the front side.
Edathil in view of Tsai shows (see, e.g., Tsai: fig. 2B) a power tap cell comprising a global via structure electrically connecting the power line to a back-side pattern.
Regarding claim 15, Edathil in view of Tsai shows (see, e.g., Edathil: figs. 1, 3A, 4B, and 5C, and see, e.g., Tsai: fig. 2B) that:
The switch dummy cell is adjacent to a logic cell area
The power tap cell is adjacent to the switch dummy cell
The switch cell is adjacent to the power tap cell.
Regarding claim 18, Edathil in view of Tsai shows (see, e.g., Edathil: figs. 1, 3A, 4B, and 5C):
A global back-side pattern electrically connected to the power line SPWR and configured to provide the global power supply voltage (see MPEP 2112.01 and MPEP 2114.I/2114.II)
A first back-side pattern electrically connected to the plurality of first power rails GND and configured to provide the first power supply voltage (see MPEP 2112.01 and MPEP 2114.I/2114.II)
A second back-side pattern electrically connected to the plurality of second power rails PPWR and configured to provide the second power supply voltage (see MPEP 2112.01 and MPEP 2114.I/2114.II)
Regrading claim 19, Edathil in view of Tsai shows (see, e.g., Tsai: fig. 2B) the power tap cell comprises a plurality of first via structures electrically connecting the plurality of first power rails to the first back-side pattern (see, e.g., Tsai: par. [0046]).
Regrading claim 21, Edathil in view of Tsai shows (see, e.g., Tsai: fig. 2B) that a plurality of first via structures electrically connecting the plurality of first power rails with the first back-side pattern, wherein the power tap cell is apart from the plurality of first via structures (see, e.g., Tsai: par. [0046]).
Regarding claim 24, Edathil in view of Tsai shows (see, e.g., Edathil: figs. 1, 3A, 4B, and 5C) the global back-side pattern (see, e.g., Edathil: par. [0019] - [0023]), the first back-side pattern, and the second back-side pattern extend in the first horizontal direction.
Allowable Subject Matter
Claims 11, 17, and 25 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for objecting to claim 11: The prior art of record neither anticipates nor renders obvious that the global via structure and the first via structure are misaligned in the second horizontal direction.
The following is an examiner’s statement of reasons for objecting to claim 17: The prior art of record neither anticipates nor renders obvious a plurality of dummy gate lines extending in a second horizontal direction perpendicular to the first horizontal direction, and N-type well region comprising a jog pattern.
The following is an examiner’s statement of reasons for objecting to claim 25: The prior art of record neither anticipates nor renders obvious that the global back-side pattern, the first back-side pattern, and the second back-side pattern extend in a second horizontal direction perpendicular to the first horizontal direction.
Claims 26-28 are allowed.
The following is an examiner’s statement of reasons for allowance of claim 26: The prior art of record neither anticipates nor renders obvious that an N-type well region comprising a jog pattern is provided in the switch dummy cell.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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