DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 12-20) in the reply filed on 4/2/ 26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12 – 14 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee (2021/0304802) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
With respect to Claim 12, Lee discloses an electronic device (Figure 1) comprising: a package substrate (Figure 1, 130) including one or more connectors (vertical wires on top of 130), a package (Figure 1, 110) including a plurality of electrodes (TSV) , wherein the plurality of electrodes are exposed on a top surface of the package and electrically coupled to the one or more connectors (vertical wires on top of 130) ; and an interface circuit (Figure 1, 1142 and paragraph 44) coupled to the one or more connectors of the package substrate, wherein the interface circuit is configured to measure one or more electrical signals via one or more connectors of the package substrate and determine one or more interface parameters of the top surface of the package based on the one or more electrical signals. (paragraphs 52-56). See Figure 1-3 and corresponding text, especially paragraphs 44-62.
With respect to Claim 13, Lee discloses wherein the package (Figure 1, 110) is physically coupled to the package substrate (Figure 1, 130) and configured to enclose and protect an integrated circuit (Figure 1, 114).
With respect to Claim 14, the electronic device further includes the integrated circuit (Figure 1, 114, base die), and the integrated circuit further includes an interface circuit (PHY, 1142 and paragraph 44) ; and the interface circuit is electrically coupled to the one or more connectors of the package substrate via one or more conductor traces of the package substrate (vertical wires on top of 130 in Figure 1) , and configured to measure the one or more electrical signals and determine the one or more interface parameters (paragraphs 52-56).
With respect to Claim 20, wherein each of a subset of electrodes (Figure 1, TSV) is coupled to an electrical path that runs through the package (Figure 1, 110) and is coupled to an electrode located on a bottom surface of the package, and the electrode located on the bottom surface of the package (bottom TSV) is electrically coupled to a respective one of the one or more connectors. See Figure 1 and corresponding text.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (2021/0304802).
Lee is relied upon as discussed above.
However, Lee does not disclose the use of conductive traces in circuit boards (Claim 15) and the use of a solid state drive ( SSD ) (Claim 19).
With respect to Claim 15, Lee discloses wherein the package substrate includes a main printed circuit board (paragraphs 123-124) ; an interface circuit (Figure 1, 1142 and paragraph 44) is configured to measure the one or more electrical signals and determine the one or more interface parameters (paragraphs 44 and 52-56); and the interface circuit (Figure 1, 1142 and paragraph 44) is mounted on the main printed circuit board. Moreover Lee discloses the printed board is electrically connected. See Figure 1 of Lee.
With respect to the limitation “ and electrically coupled to the one or more connectors of the package of the package substrate via one or more conductive traces of the main printed circuit board”, the Examiner takes Official Notice that the use of conductive traces are well known in printed circuit boards.
It would have been obvious for one of ordinary skill in the art, before the effective date of the invention, to use conductive traces in the printed circuit board of Lee, as the use of a known component for its known benefit would have been prima facie obvious to one of ordinary skill in the art.
With respect to Claim 19, and the limitation wherein the electrostatic device further includes a solid state drive (SSD) that is enclosed in the package, which is mounted on the package substrate, and the electronic device is applied in a data center computer system, Lee discloses a processor with an interface circuit. See Figure 1, 120. The Examiner takes Official Notice that solid state drives and connections to a data center computer system are well known in the art for processors with interface circuits.
It would have been obvious for one of ordinary skill in the art, before the effective date of the invention, to use a solid state drive and connection with a computer data center device of Lee, as the use of a known component for its known benefit would have been prima facie obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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AGG
May 28, 2026
/ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812
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