Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election without traverse of in the reply filed on 17 April 2026 is acknowledged.
Claims 3 and 10 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 17 April 2026.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application KR 1020230125362 filed on 9/20/2023. The foreign application is not in English. The certified copy of the foreign priority application has been received. Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application KR 1020230125362 that is not in English, an English translation of the non-English language foreign application and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Objections
Claims 1, 14 and 16 objected to because of the following informalities:
Claim 1 recites the limitation “the support structure including a first inclined surface extending in a second direction crossing the first direction;” where there is no prior mention of a first direction.
Examiner’s Interpretation: For purposes of examination the first part of claim one is interpreted to read “A semiconductor device comprising: a source structure; a support structure disposed over the source structure in a first direction, the support structure including a first inclined surface extending in a second direction crossing the first direction; “
Claim 14 recites the following limitation “and wherein each of the conductive layers includes a wave-like profile extending in the second direction.” There is no antecedent basis for the second direction.
Examiner’s Interpretation: For purposes of examination, claim one is interpreted to read “A semiconductor device comprising: a source structure; a support structure disposed over the source structure, the support structure including a plurality of supports arranged along a first direction; a gate structure disposed over the support structure in a second direction, perpendicular to the first direction, the gate structure including conductive layers and insulating layers alternately stacked; and channel structures passing through the gate structure to connect to the source structure, wherein the support structure has an overall wave-like profile with a plurality of alternating convex protrusions and concave valleys; and wherein each of the conductive layers includes a wave-like profile extending in the second direction
Claim 16 reads “The semiconductor device of claim 14, at least one of the channel structures extends through the wave-like profile of the conductive layers.” This does not contain a linking word or phrase (e.g. wherein). For purposes of examination it is being interpreted as “The semiconductor device of claim 14, wherein at least one of the channel structures extends through the wave-like profile of the conductive layers.”
Appropriate correction is required.
Claim Rejections 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14 and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yune et al. (KR 101900892), hereinafter referred to as Yune.
Regarding claim 14, Yune teaches a semiconductor device comprising: a source structure (Yune, 303, Fig. 5, page 16, para. 1); a support structure disposed over the source structure (Yune, 311a, Fig. 5, page 15, para. 7), the support structure including a plurality of supports arranged along a first direction (Yune, 311a, Fig. 5); a gate structure disposed over the support structure in a second direction, perpendicular to the first direction, the gate structure including conductive layers and insulating layers alternately stacked (Yune, LSL, WL, USL, ILD1-6, page15 para. 7-page 16 para. 1) ; and channel structures passing through the gate structure to connect to the source structure (Yune, 321, 323, 325, Fig. 5, page 16, para. 1), wherein the support structure has an overall wave-like profile with a plurality of alternating convex protrusions and concave valleys (Yune, Fig. 5); and wherein each of the conductive layers includes a wave-like profile extending in the second direction (Yune, Fig. 5).
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Regarding claim 16, Yune teaches the semiconductor device of claim 14, wherein at least one of the channel structures extends through the wave-like profile of the conductive layers (Yune, Fig. 5, shows channel structures (321, 323, 325) extending through the troughs of the waves).
Regarding claim 17, Yune teaches the semiconductor device of claim 14, wherein the support structure (Yune, 311a, Fig. 5, page. 15, para.7 and page 11, para. 1, NOTE: page 15, para. 7 says it is an oxide, page 11, para. 1 says oxide film is an insulator) includes an insulating material having an etch selectivity with respect to nitride.
Regarding claim 18, Yune teaches wherein a shape of the wave-like profile of the conductive layers is different for each level of the conductive layers, such that the conductive layers relatively adjacent to the support structure have a shape transferred from the overall wave-like profile of the support structure (Yune, Fig. 5, the shape of the stack structure is directly related to the shape of the support structure beneath them).
Claim Rejections 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-9, 11-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yune in view of Sugawara et al. (US Pub 20190139974) hereinafter referred to as Sugawara.
Examiner’s Note: All page numbers and paragraph numbers are from the copy provided by the applicant.
Regarding claim 1, Yune teaches a semiconductor device comprising: a source structure (Yune, 303, Fig. 5, page 16, para. 1); a support structure (Yune, 311a, Fig. 5, page 15, para. 7) disposed over the source structure in a first direction, the support structure including a first inclined surface extending in a second direction crossing the first direction; a gate structure disposed over the source structure and the support structure, the gate structure including conductive layers (Yune, LSL, WL, USL, Fig. 5, page 16, para. 1) and insulating (Yune, ILD1-ILD6, Fig. 5, page 15, para. 7) layers alternately stacked; channel structures passing through the gate structure to connect to the source structure (Yune, 321, 323,m 325, Fig. 5, page 16, paras. 1, 5); and a slit structure (Yune, 335, Fig. 5, page 15, para 7); wherein each of the conductive layers includes a second inclined surface extending in the second direction.
Yune does not teach wherein the slit structure extends in the first direction through the gate structure.
However, Sugawara teaches a semiconductor device wherein a backside contact via structure (Sugawara, 76, Fig 21B, para 140) and an insulating spacer (Sugawara, 74, Fig. 21B, para 137) extends in the same first direction as the plurality of channel structures (Sugawara, 20, Fig. 21B).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the device of Yune with the backside structures of Sugawara in order to reduce or prevent electrical shorts between vertically neighboring pairs of electrically conductive layers (Sugawara para. 164).
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Regarding claim 2, modified Yune teaches the semiconductor device of claim 1, wherein at least one of the channel structures extends through the second inclined surface (Sugawara, 20, Fig. 21A, para. 120).
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Regarding claim 4, modified Yune teaches the semiconductor device of claim 1, wherein the support structure includes supports spaced apart in the first direction, and wherein each support has a trapezoidal shape (Yune, 311a, Fig. 5).
Regarding claim 5, modified Yune teaches the semiconductor device of claim 4, wherein the supports are adjacent in the second direction (Yune, 311a, Fig. 5, supports are adjacent to one another), and the slit structure is positioned between the supports adjacent in the second direction (Sugawara, 74, 76, Fig, 21B, the slit structures are located between the rows of channel structures, as seen in Fig. 1A of the application).
Regarding claim 6, modified Yune teaches the semiconductor device of claim 1, wherein the first inclined surface includes an angled surface (Yune, see Fig. 5).
Regarding claim 7, modified Yune teaches the semiconductor device of claim 1, wherein the support structure (Yune, 311a, Fig. 5, page 15, para. 7, 311a is an oxide) includes a material having an etch selectivity with respect to nitride.
Regarding claim 8, modified Yune teaches the semiconductor device of claim 1, wherein the support structure (Yune, 311a, Fig. 5, page. 15, para.7 and page 11, para. 1, NOTE: page 15, para. 7 says it is an oxide, page 11, para. 1 says oxide film is an insulator) includes an insulating material.
Regarding claim 9, Yune teaches a semiconductor device comprising: a support structure including a first inclined surface (Yune, 311a, Fig. 5, page 15, para. 7);
a gate structure including insulating layers (Yune, ILD 1-6, Fig. 5, page 15, para. 7) and conductive layers (Yune, LSL, WL, USL, Fig. 5, page 16, para. 1) alternately stacked on the support structure, each of the conductive layers including a second inclined surface;
a channel structure extending through the surface of the gate structure (Yune, 321, 323, 325, Fig. 5, page 16, pars. 1, 5). ;
and a slit structure (Yune, 335, Fig. 5, page 15, para. 7).
Yune does not teach wherein the channel structure extends through the second inclined surface of the gate structure; or where the slit structure extends through the second inclined surface of the gate structure.
However, Sugawara teaches a semiconductor device where the channel structures (Sugawara, 20, Fig. 21A, para. 120) extend through the second inclined surface of the gate structure. Additionally Sugawara teaches a a backside contact via structure (Sugawara, 76, Fig 21B, para 140) and an insulating spacer (Sugawara, 74, Fig. 21B, para 137) extends in the same first direction as the plurality of channel structures (Sugawara, 20, Fig. 21B). This would cause the slit structure to extend through the inclined portions (not shown in the figures)).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the device of Yune with the channel structures and backside structures of Sugawara in order to reduce or prevent electrical shorts between vertically neighboring pairs of electrically conductive layers (Sugawara para. 164)
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Regarding claim 11, modified Yune teaches the semiconductor device of claim 9, wherein the first inclined surface includes an angled surface (Yune, Fig. 5).
Regarding claim 12, modified Yune teaches the semiconductor device of claim 9, wherein the support structure (Yune, 311a, Fig. 5, page 15, para. 7, 311a is an oxide) includes a material having an etch selectivity with respect to nitride.
Regarding claim 13, modified Yune teaches the semiconductor device of claim 9, wherein the support structure (Yune, 311a, Fig. 5, page. 15, para.7 and page 11, para. 1, NOTE: page 15, para. 7 says it is an oxide, page 11, para. 1 says oxide film is an insulator) includes an insulating material.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yune as applied to claim 14 above, and further in view of Sugawara.
Regarding claim 15, Yune teaches the semiconductor device of claim 14, further comprising: a slit structure (Yune, 335, Fig. 5, page 15, para 7), but does not teach the slit structure extending in the first direction through the gate structure.
However, Sugawara teaches a semiconductor device wherein a backside contact via structure (Sugawara, 76, Fig 21B, para 140) and an insulating spacer (Sugawara, 74, Fig. 21B, para 137) extends in the same first direction as the plurality of channel structures (Sugawara, 20, Fig. 21B).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the device of Yune with the backside structures of Sugawara in order to reduce or prevent electrical shorts between vertically neighboring pairs of electrically conductive layers (Sugawara para. 164).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jung et al. (US Pub. 20240315034) teaches a semiconductor device with slit structures extending parallel to the lines of channel structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:00-4:3.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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