DETAILED ACTION
1. This Office action is in response to the amendment filed on 02/24/2026
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
4. Claim 14 is objected to because of the following informalities:
Claim 14 recites “A method comprising: estimating electrical current at intermediate nodes of a power converter based on voltage measured at an input to the power converter,… ”. However, it appears that it should recite “A method comprising: estimating an electrical current at intermediate nodes of a power converter based on a voltage measured at an input to the power converter,… ”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 1 - 3 and 7 - 8 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US Pub. No. 2015/0092460 A1; (hereinafter Tallam et al).
Regarding claim 1, Tallam et al [e.g., Figs. 2 and 5] discloses a power converter comprising: a filter system comprising a plurality of input nodes and a plurality of output nodes [e.g., LC filter 20], each input node configured to electrically connect to one phase of a multi-phase AC electrical power distribution network [e.g., each node connected to AC source 2]; an electrical network comprising a plurality of intermediate nodes [e.g., nodes between LC Filter 20 and Active rectifier 30], each intermediate node electrically connected to one output node of the filter system [e.g., each node connected to output of LC filter 20], the electrical network configured to convert alternating current (AC) to direct current (DC) [e.g., converts AC from AC source 2 to DC via DC link 40], the electrical network comprising a plurality of electronic switches [e.g., active rectifier 30]; a DC link electrically connected to the electrical network and configured to receive DC current from the electrical network [e.g., DC link 40]; and a control system [e.g., controller 60 and Degradation detection circuit 70] configured to: access a measured indication of voltage of the multi-phase AC electrical power distribution network [e.g., -- refer to Fig. 5 for degradation codetection circuit 70 --, access measured voltages VRS and VST]; estimate electrical current at the intermediate nodes based on the measured indication of voltage of the multi-phase AC electrical power distribution network [e.g., Phasor computation component 71 calculates current phasor based on received line voltages (VRS and VST), p. 0021 recites “the phasor computation component 71 receives measured filter branch currents iR, iS and iT as well as line-line voltages vRS and vST…. Based on these, the phasor computation component 71 computes fundamental frequency current and voltage phasors R, S, T,..”]; estimate an unbalance metric at the intermediate nodes based on the estimate of electrical current at the intermediate nodes [e.g., calculates unbalanced admittance matrix when capacitor bank of the filter 20 becomes unbalanced p. 0024 recites “p. 0024 recites “Accordingly, the diagonal admittance matrix terms Ypp and Ynn (representing the effect of positive sequence voltage on positive sequence current, and the effect of negative sequence voltage on negative sequence current, respectively) are generally equal for an ideal balanced capacitor bank, while the off-diagonal terms Ypn and Ynp are zero. When the capacitor bank of the filter 20 becomes unbalanced (e.g., due to degradation of one or more of the filter capacitors), the off-diagonal terms Ynp and Ypn become non-zero, and may be used to measure the degree of degradation.”]; and control the electronic switches to compensate for the estimated unbalance metric to thereby reduce an amplitude of a ripple current in the DC current [e.g., control AFE rectifier 30 to attenuate second harmonic ripple on the DC bus p. 0045 recites “Moreover, the inventors have appreciated that the response of an active rectifier 30 to voltage unbalance is also a function of control loop bandwidths during operation of the power converter 10, in particular the current regulator, and thus the magnitude of negative-sequence current through the capacitors of the filter circuit 20 may be affected by the control loops of the AFE rectifier 30. In this regard, the AFE rectifier 30 could either regulate the line currents to be of positive sequence only (resulting in high second harmonic ripple on DC bus 40) or regulate the DC bus 40 to attenuate second harmonic ripple on the DC bus (resulting in unbalanced line currents)”].
Regarding claim 2, Tallam et al [e.g., Fig. 2] discloses wherein the unbalance metric is an estimate of an amount of voltage unbalance [e.g., admittance matrix elements calculated with estimated phasor voltages VRS and VST, p. 0021 recites “…the phasor computation component 71 receives measured filter branch currents iR, iS and iT as well as line-line voltages vRS and vST…. Based on these, the phasor computation component 71 computes fundamental frequency current and voltage phasors R, S, T, {tilde over (V)}RS and {tilde over (V)}ST….. Beginning with the measured current and voltage values (e.g., iR, iS, iT, vRS and vST), the fundamental frequency phasor computation component 71 in FIG. 5 constructs the fundamental frequency phasors R, S, T, {tilde over (V)}RS and {tilde over (V)}ST in one embodiment according to the following equations (1):…”].
Regarding claim 3, Tallam et al [e.g., Fig. 2] discloses wherein the unbalance metric comprises an estimate of a negative sequence voltage at the intermediate nodes [e.g., voltage Vn generated by Sequence Component Computation72, p. 0024 recites “Accordingly, the diagonal admittance matrix terms Ypp and Ynn (representing the effect of positive sequence voltage on positive sequence current, and the effect of negative sequence voltage on negative sequence current, respectively) are generally equal for an ideal balanced capacitor bank, while the off-diagonal terms Ypn and Ynp are zero. When the capacitor bank of the filter 20 becomes unbalanced (e.g., due to degradation of one or more of the filter capacitors), the off-diagonal terms Ynp and Ypn become non-zero, and may be used to measure the degree of degradation.”].
Regarding claim 7, Tallam et al [e.g., Fig. 2] discloses wherein the electrical network comprises a rectifier [e.g., active rectifier 30], and each of the plurality of electronic switches is a transistor [e.g., S1 - S6, p. 0017 recites “The switching rectifier 30 and the inverter 50 may employ any suitable form of switching devices S1-S12 including without limitation insulated gate bipolar transistors (IGBTs), silicon controlled rectifiers (SCRs), gate turn-off thyristors (GTOs), integrated gate commutated thyristors (IGCTs), etc.”].
Regarding claim 8, Tallam et al [e.g., Fig. 2] discloses wherein the electrical network is configured to convert DC power to AC power such that the power converter is a bi-directional power converter [e.g., converts DC from DC link 40 to AC via inverter 50].
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claim(s) 4 - 6 are rejected under 35 U.S.C. 103 as being unpatentable over Tallam et al in view of US Pub. No. 2009/0244937 A1; (hereinafter Tallam et al and Liu).
Regarding claim 4, Tallam et al discloses the claimed invention except for the wherein the unbalance metric comprises an estimate of a d-axis component of the negative sequence voltage and a q-axis component of the negative sequence voltage.
Liu [e.g., Fig. 2] teaches wherein the unbalance metric [e.g., measure unbalance three phase voltage] comprises an estimate of a d-axis component of the negative sequence voltage and a q-axis component of the negative sequence voltage [e.g., p. 0035 recites “The control system 280 includes a voltage sample and hold circuit 202, which samples AC line input voltage and provides digitized three-phase voltage signals ea, eb, and ec to a three phase to two phase transformer 204. The transformer 204 transforms three phase signals into two phase quantities in a stationary .alpha.-, .beta.-coordinate system. The output of the transformer 204 (i.e., e.alpha. and e.beta.) is converted by a stationary to rotating reference frame converter 206 to d- and q-axis components (i.e., ed and eq) in a rotating reference frame defined by a phase angle .theta.. In this rotating reference frame, positive and negative sequence components edp, edn, eqp, eqn of the voltage signals ed and eq are also obtained, whereas non-zero values of negative sequence components edn and eqn indicate the presence of unbalanced voltage conditions..”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Tallam et al with wherein the unbalance metric comprises an estimate of a d-axis component of the negative sequence voltage and a q-axis component of the negative sequence voltage as suggested by Liu for reducing DC bus voltage harmonics caused by unbalanced input voltages.
Regarding claim 5, Tallam et al discloses the claimed invention except for the determine a d-axis component of an AC current that flows in the intermediate nodes of the power converter; and determine a q-axis component of an AC current that flows in the intermediate nodes of the power converter, and, wherein the control system estimates the unbalance metric based on the d-axis component of the AC current that flows in the intermediate nodes and the q- axis component of the AC current that flows in the intermediate nodes.
Liul [e.g., Fig. 2] discloses determine a d-axis component of an AC current that flows in the intermediate nodes of the power converter [e.g., currents Id and Iq generated by Stationary to Rotating reference frame converter 216]; and determine a q-axis component of an AC current that flows in the intermediate nodes of the power converter [e.g., determines Iq current by Stationary to Rotating reference frame converter 216], and, wherein the control system estimates the unbalance metric based on the d-axis component of the AC current that flows in the intermediate nodes and the q-axis component of the AC current that flows in the intermediate nodes [e.g., d-axis components and q-axis components used to detect unbalance conditions of the circuit, p. 0045 recites “Upon collecting the reference current signals id* and iq*, in step 340, the current regulator compares id* and iq* with sampled AC line current components id and iq for generating d- and q-axis correction voltages ede and eqe, respectively. The conversion of id and iq from three phase signals ia, ib, and ic follows a similar set of Clark Transformation 324 and Park Transformation 326 to those described for voltage conversion. Note in this step, both positive current sequences idp, iqp and negative current sequences idn, iqn are regulated together to the reference levels id* and iq* in the same positive synchronous reference frame. Examples of the current regulator will be described in greater details later.” It continues on p. 0035 recites “The control system 280 includes a voltage sample and hold circuit 202, which samples AC line input voltage and provides digitized three-phase voltage signals ea, eb, and ec to a three phase to two phase transformer 204. The transformer 204 transforms three phase signals into two phase quantities in a stationary .alpha.-, .beta.-coordinate system. The output of the transformer 204 (i.e., e.alpha. and e.beta.) is converted by a stationary to rotating reference frame converter 206 to d- and q-axis components (i.e., ed and eq) in a rotating reference frame defined by a phase angle .theta.. In this rotating reference frame, positive and negative sequence components edp, edn, eqp, eqn of the voltage signals ed and eq are also obtained, whereas non-zero values of negative sequence components edn and eqn indicate the presence of unbalanced voltage conditions”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Tallam et al with determine a d-axis component of an AC current that flows in the intermediate nodes of the power converter; and determine a q-axis component of an AC current that flows in the intermediate nodes of the power converter, and, wherein the control system estimates the unbalance unbalanced metric based on the d-axis component of the AC current that flows in the intermediate nodes and the q- axis component of the AC current that flows in the intermediate nodes as suggested by Liu as suggested by Liu for reducing DC bus voltage harmonics caused by unbalanced input voltages.
Regarding claim 6, Tallam et al discloses the claimed invention except to estimate a d-axis positive sequence voltage component, a q-axis positive sequence voltage component, a d-axis negative sequence voltage component, and a q-axis negative sequence voltage component based on the d-axis component of the AC current that flows in the intermediate nodes and the q-axis component of the AC current that flows in the intermediate nodes; and the control system estimates the unbalance unbalanced metric based on the d-axis positive sequence voltage component, the q-axis positive sequence voltage component, the d- axis negative sequence voltage component, and the q-axis negative sequence voltage component.
Liu [e.g., Fig. 6] teaches to estimate a d-axis positive sequence voltage component [e.g., d -axis positive sequence component (edp) generated by Stationary to rotating reference frame converter 206], a q-axis positive sequence voltage component [e.g., q-axis positive sequence component (eqp) generated by Stationary to rotating reference frame converter 206], a d-axis negative sequence voltage component [e.g., d-axis negative sequence component (edn) generated by Stationary to rotating reference frame converter 206], and a q-axis negative sequence voltage component based on the d-axis component of the AC current that flows in the intermediate nodes and the q-axis component of the AC current that flows in the intermediate nodes [e.g., q-axis negative sequence component (eqn) generated by Stationary to rotating reference frame converter 206]; and the control system estimates the unbalance unbalanced metric based on the d-axis positive sequence voltage component, the q-axis positive sequence voltage component, the d- axis negative sequence voltage component, and the q-axis negative sequence voltage component [p. 0035 recites “The control system 280 includes a voltage sample and hold circuit 202, which samples AC line input voltage and provides digitized three-phase voltage signals ea, eb, and ec to a three phase to two phase transformer 204. The transformer 204 transforms three phase signals into two phase quantities in a stationary .alpha.-, .beta.-coordinate system. The output of the transformer 204 (i.e., e.alpha. and e.beta.) is converted by a stationary to rotating reference frame converter 206 to d- and q-axis components (i.e., ed and eq) in a rotating reference frame defined by a phase angle .theta.. In this rotating reference frame, positive and negative sequence components edp, edn, eqp, eqn of the voltage signals ed and eq are also obtained, whereas non-zero values of negative sequence components edn and eqn indicate the presence of unbalanced voltage conditions”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify to estimate a d-axis positive sequence voltage component, a q-axis positive sequence voltage component, a d-axis negative sequence voltage component, and a q-axis negative sequence voltage component based on the d-axis component of the AC current that flows in the intermediate nodes and the q-axis component of the AC current that flows in the intermediate nodes; and the control system estimates the unbalance unbalanced metric based on the d-axis positive sequence voltage component, the q-axis positive sequence voltage component, the d- axis negative sequence voltage component, and the q-axis negative sequence voltage component as suggested by Liu reducing DC bus voltage harmonics caused by unbalanced input voltages.
Regarding claim 18, Tallam et al [e.g., Fig. 2] discloses a power converter comprising: a filter system comprising a plurality of input nodes [e.g., LC filter 20], each input node configured to electrically connect to one phase of a multi-phase AC electrical power distribution network [e.g., each node connected to AC source 2; an electrical network comprising a plurality of intermediate nodes[e.g., nodes between LC Filter 20 and Active rectifier 30], each intermediate node electrically connected to one phase of the filter system [e.g., each node connected to output of LC filter 20], the electrical network configured to convert alternating current (AC) to direct current (DC) [e.g., converts AC from AC source 2 to DC via DC link 40], the electrical network comprising a plurality of electronic switches [e.g., active rectifier 30]; a DC link electrically connected to the electrical network and configured to receive DC current from the electrical network [e.g., DC link 40]; and a control system configured to: estimate an unbalance metric at the intermediate nodes [e.g., calculates unbalanced admittance matrix when capacitor bank of the filter 20 becomes unbalanced p. 0024 recites “Accordingly, the diagonal admittance matrix terms Ypp and Ynn (representing the effect of positive sequence voltage on positive sequence current, and the effect of negative sequence voltage on negative sequence current, respectively) are generally equal for an ideal balanced capacitor bank, while the off-diagonal terms Ypn and Ynp are zero. When the capacitor bank of the filter 20 becomes unbalanced (e.g., due to degradation of one or more of the filter capacitors), the off-diagonal terms Ynp and Ypn become non-zero, and may be used to measure the degree of degradation.”]; and control the electronic switches to compensate for the estimated unbalance metric to thereby reduce an amplitude of a ripple current in the DC current [e.g., control AFE rectifier 30 to attenuate second harmonic ripple on the DC bus p. 0045 recites “Moreover, the inventors have appreciated that the response of an active rectifier 30 to voltage unbalance is also a function of control loop bandwidths during operation of the power converter 10, in particular the current regulator, and thus the magnitude of negative-sequence current through the capacitors of the filter circuit 20 may be affected by the control loops of the AFE rectifier 30. In this regard, the AFE rectifier 30 could either regulate the line currents to be of positive sequence only (resulting in high second harmonic ripple on DC bus 40) or regulate the DC bus 40 to attenuate second harmonic ripple on the DC bus (resulting in unbalanced line currents)”].
Tallam et al does not disclose wherein the unbalance metric comprises an estimate of a negative sequence voltage at the intermediate nodes, and the estimate of a negative sequence voltage at the intermediate nodes comprises an estimate of a d-axis component of the negative sequence voltage and a q-axis component of the negative sequence voltage.
Liu [e.g., Fig. 2] teaches wherein the unbalance metric [e.g., measure unbalance three phase voltage] comprises an estimate of a negative sequence voltage at the intermediate nodes, and the estimate of a negative sequence voltage at the intermediate nodes comprises an estimate of a d-axis component of the negative sequence voltage and a q-axis component of the negative sequence voltage [e.g., negative sequence components eqn and edn p. 0035 recites “The control system 280 includes a voltage sample and hold circuit 202, which samples AC line input voltage and provides digitized three-phase voltage signals ea, eb, and ec to a three phase to two phase transformer 204. The transformer 204 transforms three phase signals into two phase quantities in a stationary .alpha.-, .beta.-coordinate system. The output of the transformer 204 (i.e., e.alpha. and e.beta.) is converted by a stationary to rotating reference frame converter 206 to d- and q-axis components (i.e., ed and eq) in a rotating reference frame defined by a phase angle .theta.. In this rotating reference frame, positive and negative sequence components edp, edn, eqp, eqn of the voltage signals ed and eq are also obtained, whereas non-zero values of negative sequence components edn and eqn indicate the presence of unbalanced voltage conditions.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Tallam et al with wherein the unbalance metric comprises an estimate of a negative sequence voltage at the intermediate nodes, and the estimate of a negative sequence voltage at the intermediate nodes comprises an estimate of a d-axis component of the negative sequence voltage and a q-axis component of the negative sequence voltage as suggested by Liu for reducing DC bus voltage harmonics caused by unbalanced input voltages.
Response to Arguments
10. Applicant’s arguments with respect to claim(s) 1, 2, 5, 7 - 9, 14 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
11. Claims 9, 11 - 17 and 19 - 21 are allowed.
12. The following is a statement of reasons for the indication of allowable subject matter:
13. The primary reason for the indication of the allowability of claim 9 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “an observer block configured to estimate a voltage disturbance in an active front end based on d-axis and q-axis components of an AC current input to the active front end; a first control block configured to determine a DC reference current based on a reference voltage for an energy storage apparatus and a measured voltage across the energy storage apparatus; a second control block configured to determine a voltage reference based on the determined DC reference current; a junction configured to subtract the estimated voltage disturbance from the determined voltage reference to determine a voltage control signal; and a third control block configured to generate a switch control signal based on the voltage control signal and to provide the switch control signal to the active front end to reduce a ripple current in a rectified current produced by the active front end.”
The primary reason for the indication of the allowability of claim 14 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… determining a voltage control signal based on the estimated positive and negative sequence components of the voltage disturbance and a reference voltage for the energy storage apparatus; determining a switch control signal based on the voltage control signal; and applying the switch control signal to switch electronic switches in the power converter in accordance with the switch control signal to thereby reduce a ripple current in the rectified current provided to the energy storage apparatus.”.
The primary reason for the indication of the allowability of claim 19 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…, wherein the first control block is configured to determine the DC reference current based on the reference voltage for the energy storage apparatus, the measured voltage across the energy storage apparatus, and a feedforward term.”
14. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
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