DETAILED ACTION Priority Claim Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. IDS All references provided in the IDS have been considered . Election/Restrictions Applicant’s election without traverse of Group I (Claims 1-7) in the reply filed on 02/26/2026 is acknowledged. Specification Applicant is reminded of the proper content of an abstract of the disclosure. A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art. If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives. Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps. Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length. See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts. Claim Objections Claim 3 is objected to because of the following informalities: Claim 3, line 6 recites “the dielectric or ferroelectric memory layer (112)” . Previous recitation of this layer in claim 1, line 7 reads “a gate dielectric layer (112) or a ferroelectric memory layer (112)”. The word “gate” appears to be missing in the claim 3 recitation. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim s 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. D ependent claim 3 , recite(s) the limitation " a bottom " in line 6 . It is unclear what surface “a bottom” is referring to. It has been interpreted to mean any surface. Appropriate correction is required. D ependent claim 3 , recite(s) the limitation " the cavities " in line 7 . Claim 3, line 2 introduces “a cavity” (singular form). There is insufficient antecedent basis for this limitation (plurality of cavities) in the claim. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-2, 4-7 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Frougier ( US 10388732 B1 ). Re: Independent Claim 1, Frougier discloses: A microelectronic device ( Frougier , field-effect transistor: Fig. 11, not numbered) comprising: a substrate ( Frougier , substrate; Fig. 11, element 14) a semiconductor layer ( Frougier , channel layer and continuous layer; Fig. 11, elements 44 and 46, respectively make up the semiconductor layer) comprising several first areas superposed on top of one another ( Frougier , channel layers; Fig. 11, element 44, Col. 6, lines 1-2, can be considered first areas, Fig. 11 shows multiple stacks of layer 44 on top of one another) and forming an electrical conduction channel of the microelectronic device ( Frougier , Fig. 11); an electrostatic control gate ( Frougier , gate structures; Fig. 11, element 36 and 38); a gate dielectric layer or a ferroelectric memory layer ( Frougier , gate dielectric layer ; Fig. 9C , element 3 7 , Col. 4 -5 , lines 65 - 18 ), such that parts of the gate dielectric layer or of the ferroelectric memory layer are each arranged between a part of the electrostatic control gate and one amongst the first areas of the semiconductor layer ; dielectric spacers ( Frougier , sidewall spacers; Fig. 11, element 24) arranged against sidewalls of the electrostatic control gate; source/drain regions ( Frougier , source/drain contacts; Fig. 11, element 52) electrically coupled to the first areas of the semiconductor layer by second areas ( Frougier , continuous layer; Fig. 11, element 46, Col. 6, lines 32- 42) of the semiconductor layer, the second areas of the semiconductor layer extending between the source/drain regions and the dielectric spacers ( Frougier , Fig. 11 shows element 46 between element 52 and element 24); and wherein the second areas of the semiconductor layer are arranged directly against and in contact with the dielectric or ferroelectric memory layer and form a continuous layer with the first areas Re: Dependent Claim 2 , Frougier disclose(s) all the limitations of claim 1 on which this claim depends. Frougier further discloses: wherein the semiconductor layer ( Frougier , channel layer and continuous layer; Fig. 11, elements 44 and 46, respectively make up the semiconductor layer) includes a two-dimensional material ( Frougier , Col. 5, lines 61-64). Re: Dependent Claim 4 , Frougier disclose(s) all the limitations of claim 1 on which this claim depends. Frougier further discloses: wherein each of the first areas ( Frougier , channel layers; Fig. 11, element 44, Col. 6, lines 1-2, can be considered first areas) of the semiconductor layer ( Frougier , channel layer and continuous layer; Fig. 11, elements 44 and 46, respectively make up the semiconductor layer) is surrounded by the same electrostatic control gate ( Frougier , gate structures; Fig. 11, element 36 and 38) or by an electrostatic control gate different from that surrounding the other first areas of the semiconductor layer ( Frougier , Fig. 9A, shows element 44 is surrounded by the same gate structure) . Re: Dependent Claim 5 , Frougier disclose(s) all the limitations of claim 1 on which this claim depends. Frougier further discloses: further including one or more dielectric portion(s) ( Frougier , dielectric layer; Fig. 9C, element 50) each arranged between two first areas ( Frougier , channel layer; Fig. 9C, elements 44a and 44b make up layer 44, which is a first area, and layer 50 is shown between two regions of these first areas) of the semiconductor layer ( Frougier , channel layer and continuous layer; Fig. 11, elements 44 and 46, respectively make up the semiconductor layer) and such that each of the dielectric portions is surrounded by one amongst the first areas of the semiconductor layer ( Frougier , Fig. 9C, shows element 50 surrounded by the first areas) . Re: Dependent Claim 6 , Frougier disclose(s) all the limitations of claim 1 on which this claim depends. Frougier further discloses: further including inner dielectric spacers ( Frougier , inner spacers; Fig. 11, element 30) arranged against sidewalls of one or more part(s) of the electrostatic control gate ( Frougier , gate structures; Fig. 11, elements 36 and 38). Re: Dependent Claim 7 , Frougier disclose(s) all the limitations of claim 1 on which this claim depends. Frougier further discloses: A microelectronic component ( Frougier , not labeled, Fig. 11 discloses the microelectronic component) including several microelectronic devices ( Frougier , field-effect transistor: Fig. 11, not numbered, but two stacks are shown) according to claim 1, and wherein: the electrostatic control gates ( Frougier , gate structures; Fig. 11, elements 36 and 38) of several ones among the microelectronic devices are common and formed by the same material portions ( Frougier , Col. 6, lines 47-56), and/or one amongst the source/drain regions ( Frougier , source/drain contacts; Fig. 11, element 52) is common to two neighboring ones among the microelectronic devices. Claim Rejections - 35 USC § 103 The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 3 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Frougier (US 10388732 B1) in view of Yeh (US 10957761 B2). R e: Dependent Claim 3 , Frougier disclose(s) all the limitations of claim 1 on which this claim depends. Frougier further discloses: wherein: each of the source/drain regions ( Frougier , source/drain contacts; Fig. 11, element 52) is arranged in a cavity comprising lateral walls formed at least by the dielectric spacers ( Frougier , sidewall spacers; Fig. 11, element 24) Frougier is silent regarding: each of the source/drain regions is arranged in a cavity comprising lateral walls formed at least by the dielectric spacers and at least by an insulating dielectric material or by the dielectric spacers and by spacers of a neighboring microelectronic device; Yeh discloses: wherein: each of the source/drain regions (Yeh, source/drain regions; Fig. 11, element 56) is arranged in a cavity (Yeh, trench, Fig. 11, element 36) comprising lateral walls formed at least by the dielectric spacers and at least by an insulating dielectric material or by the dielectric spacers (Yeh, top spacer; Fig. 11, element 42) and by spacers of a neighboring microelectronic device (Yeh, Fig. 11 shows the source/drain between the spacers of the neighboring device stack) (Because 'the dielectric spacers and at least by an insulating dielectric material‘ is part of an alternative 'or' limitation, this is not required by the prior art to read on the claim as presented); Frougier discloses a source drain region located in a cavity comprising lateral walls formed by at least the dielectric spacers, but Frougier does not disclose that each of the source/drains regions is in a cavity formed by the dielectric spacers and at least by an insulating material or by the dielectric spacers and by spacers of a neighboring dielectric material. Yeh discloses each of the source drain regions is arranged in a cavity comprising lateral walls formed by the dielectric spacers and by spacers of a neighboring microelectr on ic device for use in a transistor device for structural isolation . Both Frougier and Yeh disclose field-effect transistor devices with 2D semiconducting material and their components and are therefore analogous art. It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to replace the source/drain region structure of Frougier with that of Yeh for the purpose of electrically isolating the gates from the source/drain regions of nanosheet transistors (Yeh, Col. 1, lines 30-34) . Frougier , as modified by Yeh, further discloses: the dielectric or ferroelectric memory layer ( Frougier , gate dielectric layer ; Fig. 9C , element 3 7 , Col. 4 -5 , lines 65 - 18 ), being in contact with a bottom ( Frougier , bottom of gate structures; Fig. 11, elements 36 and 38, can be considered a bottom) and said lateral walls of the cavities (150) in which the source/ drain regions are arranged the second areas ( Frougier , continuous layer; Fig. 11, element 46, Col. 6, lines 32- 42) of the semiconductor layer ( Frougier , channel layer and continuous layer; Fig. 11, elements 44 and 46, respectively make up the semiconductor layer) cover the walls of the cavities, the dielectric or ferroelectric memory layer at the bottom and said lateral walls of the cavities in which the source/drain regions are arranged. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT NIMARTA KAUR CHOWDHARY whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-7679 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT usually Monday - Thursday, 7:00 AM - 5:00 pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Leonard Chang can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 270-3691 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NIMARTA KAUR CHOWDHARY/ Examiner, Art Unit 2898 /Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898