DETAILED ACTION
Response to Amendments
The Amendment filed 06/04/2026 has been entered. Claims 1-15 are amended. Claims 1-15 are pending in the application. Claims 8-15 are withdrawn from consideration as been drawn to non-elected claims. Examiner notes the amendment to the abstract overcomes the previous objection. Examiner notes the amendment to claim 3 overcomes the previous objections and 112b rejections.
Response to Arguments
Applicant's arguments filed 06/04/2026 have been fully considered but they are not persuasive.
Regarding the argument on pages 11-12, where applicant argues that now amended independent claim 1, which recites a “semiconductor layer comprising several first areas superposed on top of one another and forming an electrical conduction channel, and source and drain regions electrically coupled to the first areas of the semiconductor layer by second areas of the semiconductor layer, the second areas of the semiconductor layer extending between the source and drain regions and the dielectric spacers, wherein the second areas of the semiconductor layer are arranged directly against and in contact with the gate dielectric layer or the ferroelectric memory layer and form a continuous layer with the first areas”, is not taught by the prior art made of record (Frougier, ‘732 patent) is not persuasive.
Examiner kindly reminds applicant that the claims are analyzed using the broadest reasonable interpretation (BRI). The claims, as written, do not require specific limitations on the gate dielectric layer. As such, a person of ordinary skill in the art (POSITA) before the effective filing date would recognize two separate dielectric layers disclosed in the ‘732 patent (layers 35 and 37) as being equivalent to the claimed gate dielectric layer. The newly defined gate dielectric layer and its configuration as being direct against in contact with the second areas reads on the claims as amended, and therefore the argument is not considered persuasive. The claims, while amended, can be rejected using the same prior art in the same manner, which can be used to disclose the amended limitations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-7 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Frougier (US 10388732 B1).
Re: Independent Claim 1, Frougier discloses:
A microelectronic device (Frougier, field-effect transistor: Fig. 11, not numbered) comprising:
a substrate (Frougier, substrate; Fig. 11, element 14)
a semiconductor layer (Frougier, channel layer and continuous layer; Fig. 11, elements 44 and 46, respectively make up the semiconductor layer) comprising several first areas superposed on top of one another (Frougier, sections/channel layers; Figs. 9 and Fig. 11, elements 44a, 44b, 44, Col. 6, lines 1-2, can be considered first areas, Fig. 11 shows multiple stacks of layer 44 on top of one another) and forming an electrical conduction channel of the microelectronic device (Frougier, Fig. 11);
an electrostatic control gate (Frougier, gate structures; Fig. 11, element 36 and 38);
a gate dielectric layer or a ferroelectric memory layer (Frougier, interface layer, gate dielectric layer; Fig. 9C, elements 35 and 37, respectively, can make up a gate dielectric layer, Col. 4-5, lines 65-18), wherein parts of the gate dielectric layer or the ferroelectric memory layer are each arranged between a part of the electrostatic control gate and one of the first areas of the semiconductor layer (Frougier, Fig. 9C, shows part of elements 35 and 37 are arranged between a part of element 36 and between 44a and 44b, which is one of the first areas);
dielectric spacers (Frougier, sidewall spacers; Fig. 11, element 24) arranged against sidewalls of the electrostatic control gate;
source and drain regions (Frougier, source/drain contacts; Fig. 11, element 52, the middle to left portion can be considered source regions, the middle to right portion can be considered drain regions) electrically coupled to the first areas of the semiconductor layer by second areas (Frougier, continuous layer; Fig. 11, element 46, Col. 6, lines 32- 42) of the semiconductor layer, the second areas of the semiconductor layer extending between the source and drain regions and the dielectric spacers (Frougier, Fig. 11 shows element 46 between element 52 and element 24)
wherein the second areas of the semiconductor layer are arranged directly against and in contact with the gate dielectric layer or the ferroelectric memory layer and form a continuous layer with the first areas (Frougier, Fig. 9C, shows element 46 directly against and in contact with the gate dielectric layer (elements 35 and 37, collectively) and it forms a continuous layer with element 44a, 44b).
Re: Dependent Claim 2, Frougier disclose(s) all the limitations of claim 1 on which this claim depends. Frougier further discloses:
wherein the semiconductor layer (Frougier, channel layer and continuous layer; Fig. 11, elements 44 and 46, respectively make up the semiconductor layer) includes a two-dimensional material (Frougier, Col. 5, lines 61-64).
Re: Dependent Claim 4, Frougier disclose(s) all the limitations of claim 1 on which this claim depends. Frougier further discloses:
wherein each of the first areas (Frougier, sections/channel layers; Figs. 9 and Fig. 11, elements 44a, 44b, 44, Col. 6, lines 1-2, can be considered first areas, Fig. 11 shows multiple stacks of layer 44 on top of one another) of the semiconductor layer (Frougier, channel layer and continuous layer; Fig. 11, elements 44 and 46, respectively make up the semiconductor layer) is surrounded by the electrostatic control gate (Frougier, gate structures; Fig. 11, element 36 and 38) or by an electrostatic control gate different from that surrounding another of the first areas of the semiconductor layer (Frougier, Fig. 9A, shows element 44 is surrounded by the electrostatic control gate).
Re: Dependent Claim 5, Frougier disclose(s) all the limitations of claim 1 on which this claim depends. Frougier further discloses:
further comprising one or more dielectric portions (Frougier, dielectric layer; Fig. 9C, element 50) each arranged between two of the first areas (Frougier, channel layer; Fig. 9C, elements 44a and 44b make up layer 44, which is a first area, and layer 50 is shown between two regions of these first areas) of the semiconductor layer (Frougier, channel layer and continuous layer; Fig. 11, elements 44 and 46, respectively make up the semiconductor layer) such that each of the one or more dielectric portions is surrounded by one of the first areas of the semiconductor layer (Frougier, Fig. 9C, shows element 50 surrounded by the first areas, element 44).
Re: Dependent Claim 6, Frougier disclose(s) all the limitations of claim 1 on which this claim depends. Frougier further discloses:
further comprising inner dielectric spacers (Frougier, inner spacers; Fig. 11, element 30) arranged against sidewalls of one or more parts of the electrostatic control gate (Frougier, gate structures; Fig. 11, elements 36 and 38).
Re: Dependent Claim 7, Frougier disclose(s) all the limitations of claim 1 on which this claim depends. Frougier further discloses:
A microelectronic component (Frougier, not labeled, Fig. 11 discloses the microelectronic component) comprising a plurality of the microelectronic devices (Frougier, field-effect transistor: Fig. 11, not numbered, but two stacks are shown) according to claim 1, wherein:
the electrostatic control gates (Frougier, gate structures; Fig. 11, elements 36 and 38) of several ones among the microelectronic devices are common and formed by same material portions (Frougier, Col. 6, lines 47-56), and/or
one of the source and drain regions (Frougier, source/drain contacts; Fig. 11, element 52, the middle to left portion can be considered source regions, the middle to right portion can be considered drain regions) is common to two neighboring ones among the microelectronic devices.
Claim 3 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Frougier (US 10388732 B1) in view of Yeh (US 10957761 B2).
Re: Dependent Claim 3, Frougier disclose(s) all the limitations of claim 1 on which this claim depends. Frougier further discloses:
wherein: each of the source and drain regions (Frougier, source/drain contacts; Fig. 11, element 52, the middle to left portion can be considered source regions, the middle to right portion can be considered drain regions) is arranged in a cavity comprising lateral walls formed at least by the dielectric spacers (Frougier, sidewall spacers; Fig. 11, element 24)
Frougier is silent regarding:
each of the source and drain regions is arranged in a cavity comprising lateral walls formed at least by the dielectric spacers and at least by an insulating dielectric material or by the dielectric spacers and by spacers of a neighboring microelectronic device;
Yeh discloses:
wherein: each of the source and drain regions (Yeh, source/drain regions; Fig. 11, element 56) is arranged in a cavity (Yeh, trench, Fig. 11, element 36) comprising lateral walls formed at least by the dielectric spacers and at least by an insulating dielectric material or by the dielectric spacers (Yeh, top spacer; Fig. 11, element 42) and by spacers of a neighboring microelectronic device (Yeh, Fig. 11 shows the source and drain regions between the spacers of the neighboring device stack, the corresponding elements make up the lateral walls) (Because 'the dielectric spacers and at least by an insulating dielectric material‘ is part of an alternative 'or' limitation, this is not required by the prior art to read on the claim as presented);
Frougier discloses a source drain region located in a cavity comprising lateral walls formed by at least the dielectric spacers, but Frougier does not disclose that each of the source and drains regions is in a cavity formed by the dielectric spacers and at least by an insulating material or by the dielectric spacers and by spacers of a neighboring dielectric material. Yeh discloses each of the source and drain regions is arranged in a cavity comprising lateral walls formed by the dielectric spacers and by spacers of a neighboring microelectronic device for use in a transistor device for structural isolation. Both Frougier and Yeh disclose field-effect transistor devices with 2D semiconducting material and their components and are therefore analogous art. It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to replace the source/drain region structure of Frougier with that of Yeh for the purpose of electrically isolating the gates from the source/drain regions of nanosheet transistors (Yeh, Col. 1, lines 30-34).
Frougier, as modified by Yeh, further discloses:
the gate dielectric layer or the ferroelectric memory layer (Frougier, interface layer, gate dielectric layer; Fig. 9C, elements 35 and 37, respectively, can make up a gate dielectric layer, Col. 4-5, lines 65-18), is in contact with a bottom wall (Frougier, bottom of gate structures; Fig. 11, elements 36 and 38, can be considered a bottom wall) and said lateral walls of the cavity (150) in which the source/ drain regions are arranged
the second areas (Frougier, continuous layer; Fig. 11, element 46, Col. 6, lines 32- 42) of the semiconductor layer (Frougier, channel layer and continuous layer; Fig. 11, elements 44 and 46, respectively make up the semiconductor layer) cover the lateral walls of the cavity, and the gate dielectric layer or the ferroelectric memory layer at the bottom and said lateral walls of the cavity in which the source and drain regions are arranged (Frougier, as modified by Yeh, Fig. 9 and 11, the second areas cover the lateral walls of the cavity and contact/cover the bottom wall of the cavity).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 6:45 AM - 4:45 PM (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIMARTA KAUR CHOWDHARY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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