CTNF 18/393,186 CTNF 101464 DETAILED ACTION IDS All references provided in the IDS have been considered. Election/Restrictions Applicant’s election without traverse of Group I (Claims 1-15) in the reply filed on 04/14/2026 is acknowledged. Examiner notes the withdrawal of claims 16-20. Specification 07-29 AIA The disclosure is objected to because of the following informalities: missing/incorrect/inconsistent reference numerals for claimed elements. In the specification, for example ¶ [0012] “one of more first conductor-less regions “ is provided with the reference numeral ‘150’ and is then later (for example, specification, ¶ [0013]) “conductor-less regions” is also provided the reference numeral ‘150’ In the specification, “second conductor-less region” is not clearly defined, nor provided with a reference character. In the specification, “second conductor-less region” is not clearly defined, nor provided with a reference character. In the specification, “first cavity” does not have a reference numeral and “second cavity” is not clearly defined, nor provided with a reference character. “Each cavity” is disclosed and it is unclear which cavity is “the first cavity” and “the second cavity”, distinction in accordance with the disclosure is needed. Similar issues to the ones presented above may exist in the disclosure, the specification and drawings should be reviewed/corrected to ensure that all claimed elements are clearly and consistently supported with the drawings, disclosed elements, and reference numerals . Appropriate correction is required. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a first region of silicon”, “a second region of silicon” , “second conductor-less region”, “first cavity”, “second cavity”, “second conductive region” must be shown, in accordance with the disclosure, or the feature(s) canceled from the claim(s). No new matter should be entered. 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claims 9, 10, and 15 are objected to because of the following informalities: Regarding claim 9, Claim 9, lines 1-2 recites: “using a xenon fluorine (XeF2)...” in accordance with the disclosure, examiner believes this should be “xenon fluoride” (ending in ‘ide’ not ‘ine’). Regarding claim 10, Claim 10, line 8 recites: “wherein the first cavity includes first upper cavity surface…” examiner believes this should read ‘wherein the first cavity includes a first upper cavity surface” (including an ‘a’ between includes and first). Regarding claim 15, Claim 15, lines 1-2 recites: “using a xenon fluorine (XeF2)...” in accordance with the disclosure, examiner believes this should be “xenon fluoride” (ending in ‘ide’ not ‘ine’). Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 07-34-01 AIA Claim s 1, 5, 7, 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Re: Independent Claim 1, Claim 1, lines 3 and 4 recite(s) the limitation “the substrate”. There is insufficient antecedent basis for this limitation in the claim as no “a substrate” is claimed. Both instances of “the substrate” have been interpreted to mean “the semiconductor substrate”. Claims 2-9 are rejected by virtue of their dependency on Claim 1. Re: Independent Claim 1, Claim 1, line 9 recites the limitation: “and electrically coupling the first conductive feature to one of the control electrode, the first current-conducting electrode, or the second current-conducting electrode”. It is unclear what ‘one of’ encompasses because, as written, as it implies there may be a plurality of control electrodes. It has been interpreted to mean: “one of the following: the control electrode, the first current-conducting electrode, or the second current-conducting electrode”. Claims 2-9 are rejected by virtue of their dependency on Claim 1. Re: Independent Claim 1, Claim 1, lines 11-12 recite(s) the limitation “the second conductive region”. There is insufficient antecedent basis for this limitation in the claim as no “a second conductive region” is claimed. “The second conductive region” have been interpreted to mean “the second conductive feature”. Claims 2-9 are rejected by virtue of their dependency on Claim 1. Re: Dependent Claim 5, Claim 5, line 2 recites “a dielectric medium selected from..”. It is unclear if this dielectric medium is the same “the dielectric medium” from Claim 5 (line 1) or if it a different instance of a dielectric medium. It has been interpreted to mean “the dielectric medium”. Re: Dependent Claim 7, Claim 7, line 1 recites “where the second conductive region”. There is insufficient antecedent basis for this claim as no “a second conductive region” has been claimed. It has been interpreted to mean “the second conductive feature”. Re: Independent Claim 10, Claim 10, lines 4 and 5 recite(s) the limitation “the substrate”. There is insufficient antecedent basis for this limitation in the claim as no “a substrate” is claimed. Both instances of “the substrate” have been interpreted to mean “the SOI substrate”. Claims 11-15 are rejected by virtue of their dependency on Claim 1. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1-8 are rejected under 35 U.S.C. 102( a)(1) and 35 U.S.C. 102(a)(2 ) as being anticipated by Green (US 9871107 B2) . Re: Independent Claim 1, Green discloses: A method, comprising: providing a semiconductor substrate (Green, semiconductor substrate; Fig. 2, element 110) including a first region of silicon (Green, left portion including semiconductor substrate 110 can be a first region of silicon, Col.2, lines 63-67, see attached annotated figure), a second region of silicon (Green, right portion including semiconductor substrate 110 can be considered a second region, Col.2, lines 63-67, see attached annotated figure), a layer of silicon dioxide (Green, first dielectric layer; Fig. 2, element 220, Col. 8 , lines 1-4) disposed between the first region and the second region of the substrate, and a layer of gallium nitride (Green, buffer layer; Fig. 2, element 214, Col. 5, lines 24-29, Col. 15, lines 26-28) on a first surface of the substrate (Green, upper surface; Fig. 2, element 213 can be considered a first surface of the substrate); PNG media_image1.png 411 584 media_image1.png Greyscale forming a transistor (Green, transistor; Fig. 2, element 120) over the first surface of the substrate, wherein forming the transistor comprises forming a control electrode (Green, gate electrode; Fig. 2, element 126), a first current-conducting electrode (Green, drain electrode; Fig. 2, element 122), and a second current- conducting electrode (Green, source electrode; Fig. 2, element 124) over the first substrate surface; forming a first conductive feature (Green, first conductive feature; Fig. 2, e.g. elements 130, and/or 132, and/or 134 can be considered a first conductive feature, Col. 2, lines 26-31 and Col. 3, lines 44-48) over the first surface of the substrate and electrically coupling the first conductive feature to one of the control electrode, the first current-conducting electrode, or the second current-conducting electrode (Green, Col. 3, lines 44 - 48); forming a second conductive feature (Green, second conductive features; Fig. 2, elements 140 and/or 142, Col. 2, lines 31-32) over a second surface of the substrate (Green, bottom substrate surface; Fig. 2, element 210), wherein the second conductive region covers only a portion of the second substrate surface to define a first conductor-less region (Green, conductor-less region; Fig. 2, element 150, Col. 9, lines 61-64, both portions of '150' can be considered the first conductor-less region); and forming a first cavity (Green, cavity; Fig. 2, element 160) within the first conductor-less region that includes a first upper cavity surface (Green, inner cavity surface; Fig. 2, element 262) defined by a surface of the layer of silicon dioxide (Green, Fig. 2, the region including dielectric layer 220 and a portion of semiconductor region 222 above 262 can be considered a surface of the layer of silicon dioxide), wherein the first upper cavity surface is directly below the first conductive feature (Green, Fig. 2, shows 262 below element 130). Re: Dependent Claim 2, Green disclose(s) all the limitations of claim 1 on which this claim depends. Green further discloses: wherein forming the first conductive feature (Green, first conductive feature; Fig. 2, e.g. elements 130, and/or 132, and/or 134 can be considered a first conductive feature, Col. 2, lines 26-31 and Col. 3, lines 44-48) includes forming at least a portion of at least one of an inductor (Green, inductor; Fig. 2, element 130) and a capacitor (Green, not illustrated; Col. 21, lines 54 - 58) over the first surface of the substrate (Green, upper surface; Fig. 2, element 213 can be considered a first surface of the substrate). Re: Dependent Claim 3, Green disclose(s) all the limitations of claim 1 on which this claim depends. Green further discloses: wherein the first conductive feature (Green, first conductive feature; Fig. 2, e.g. elements 130, and/or 132, and/or 134 can be considered a first conductive feature, Col. 2, lines 26-31 and Col. 3, lines 44-48) is a component of a bulk acoustic wave (BAW) filter (Green, discloses element 130 is an inductor which is a component of a BAW filter). Re: Dependent Claim 4, Green disclose(s) all the limitations of claim 1 on which this claim depends. Green further discloses: further comprising forming a dielectric medium (Green, dielectric medium; Fig. 2, element 166) within the first cavity (Green, cavity; Fig. 2, element 160), wherein the dielectric medium has a dielectric constant less than a dielectric constant of the semiconductor substrate (Green, Col. 25, lines 5-8). Re: Dependent Claim 5, Green disclose(s) all the limitations of claim 4 on which this claim depends. Green further discloses: wherein forming the dielectric medium (Green, dielectric medium; Fig. 2, element 166) within the first cavity (Green, cavity; Fig. 2, element 160) includes disposing a dielectric medium selected from benzocyclobutene (BCB), polymide, epoxy, and spin-on glass into the first cavity (Green, Col. 10, lines 62-68). Re: Dependent Claim 6, Green disclose(s) all the limitations of claim 4 on which this claim depends. Green further discloses: further comprising: forming an active region (Green, active area; Fig. 2, element 114) that includes the control electrode (Green, gate electrode; Fig. 2, element 126), the first current-conducting electrode (Green, drain electrode; Fig. 2, element 122), and the second current- conducting electrode (Green, source electrode; Fig. 2, element 124); and forming an isolation region (Green, isolation region; Fig. 1, element 112) that includes the first conductive feature (Green, first conductive feature; Fig. 2, e.g. elements 130, and/or 132, and/or 134 can be considered a first conductive feature, Col. 2, lines 26-31 and Col. 3, lines 44-48) (Green, Fig. 1 shows a portion of element 134 contained within 112). Re: Dependent Claim 7, Green disclose(s) all the limitations of claim 6 on which this claim depends. Green further discloses: wherein the second conductive region (Green, second conductive features; Fig. 2, elements 140 and/or 142, Col. 2, lines 31-32) covers only the portion of the second substrate surface (Green, bottom substrate surface; Fig. 2, element 210) to define a second conductor-less region (Green, conductor-less region; Fig. 2, element 150, Col. 9, lines 61-64, the leftmost instance of 150 can be considered a second conductor-less region) and further comprising: PNG media_image2.png 430 600 media_image2.png Greyscale forming a second cavity (Green, not illustrated, see attached figure) within the first conductor-less region (Green, conductor-less region; Fig. 2, element 150, Col. 9, lines 61-64, both portions of '150' can be considered the first conductor-less region) that includes a second upper cavity surface (Green, not illustrated, see attached figure, the top most surface of the second cavity can be considered a second upper cavity surface) defined by a surface of the active region (Green, active area; Fig. 2, element 114, the bottom portion of 114 can be considered a surface), wherein the second upper cavity surface is directly below the transistor (Green, transistor; Fig. 2, element 120); and forming a conductive material (Green, back metal; Fig. 2, element 140, Col. 4, lines 27-30) within the second cavity. Re: Dependent Claim 8, Green disclose(s) all the limitations of claim 6 on which this claim depends. Green further discloses: further comprising forming the first cavity (Green, cavity; Fig. 2, element 160) by etching the semiconductor substrate Green, semiconductor substrate; Fig. 2, element 110, Cols. 9 and 10, lines 67-19) using a dry etch technique (Green, Col. 23, lines 54-60). Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 9 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Green (US 9871107 B2) in view of Akiyama (US 20200101492 A1). Re: Dependent Claim 9, Green discloses all the limitations of claim 1 on which this claim depends. Green further discloses: further comprising forming the first cavity (Green, cavity; Fig. 2, element 160), etching process (Green, Cols. 9 and 10, lines 67-19). Green does not explicitly disclose: forming the first cavity using a xenon difluorine (XeF2) etching process. Akiyama discloses: forming the first cavity (Akiyama, cavity; Fig. 8G, element 114) using a xenon difluorine (XeF2) etching process (Akiyama, dry etching with xenon difluoride, ¶ [0067]). Green discloses forming the cavity uses an etching process, and further discloses that any suitable number of etching processes can be used, but does not explicitly disclose the use of a xenon difluorine (XeF2) etching process. Akiyama discloses forming a cavity using Xenon difluoride within a layer of material for use within a device. Both Akiyama and Green disclose methods of forming a cavity within semiconductor devices and are therefore analogous art. It would be obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to use an XeF2 etching process as it is a high selectivity process allowing for more control over what is removed (Akiyama, ¶ [0040]). Claims 10-14 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Green (US 9871107 B2) in view of Kamgaing (US 20200219861 A1). Re: Independent Claim 10, Green discloses: providing a substrate (Green, semiconductor substrate, first dielectric layer; Fig. 2, elements 110 and 220, collectively make up the substrate), Green does not explicitly disclose: providing a silicon-on-insulator (SOI) substrate Kamgaing discloses: providing a silicon-on-insulator (SOI) substrate (Kamgaing, substrate; Fig. 1, element 110, ¶ [0015] "substrate may be a semiconductor substrate, such as but not limited to a silicon substrate, a silicon on insulator substrate") Green broadly discloses a semiconductor substrate but does not explicitly disclose the semiconductor substrate to be an silicon-on-insulator (SOI) substrate. Kamgaing discloses that semiconductor substrate may include various substrate structures, including silicon-on-insulator (SOI) substrates, further indicating that SOI substrates are known structures used within semiconductor devices Green and Kamgaing disclose components used within semiconductor devices and are therefore analogous art. It would be obvious to a POSITA before the effective filing date to modify and replace the semiconductor substrate of Green to comprise a SOI substrate, as demonstrate by Kamgaing, as SOI substrates are known structures included within the broader category of semiconductor substrates. Selecting an SOI substrate from a finite number of alternatives for a semiconductor substrate is a known and predictable substitution, yielding predictable results of enhanced electrical isolation or reducing parasitic effects. Green, as modified by Kamgaing, further discloses: a layer of gallium nitride (Green, buffer layer; Fig. 2, element 214, Col. 5, lines 24-29, Col. 15, lines 26-28) on a first surface of the substrate (Green, upper surface; Fig. 2, element 213 can be considered a first surface of the substrate); forming a device (Green, transistor; Fig. 2, element 120) over the first surface of the substrate, forming a first conductive feature (Green, first conductive feature; Fig. 2, e.g. elements 130, and/or 132, and/or 134 can be considered a first conductive feature, Col. 2, lines 26-31 and Col. 3, lines 44-48) over the first surface of the substrate and electrically coupling the first conductive feature to the device (Green, Col. 3, lines 44 - 48); and forming a first cavity (Green, cavity; Fig. 2, element 160) in a second surface of the SOI substrate (Green, bottom substrate surface; Fig. 2, element 210) directly below the first conductive feature, wherein the first cavity includes first upper cavity surface (Green, inner cavity surface; Fig. 2, element 262) defined by a surface of a layer of silicon dioxide (Green, Fig. 2, the region including dielectric layer 220 and a portion of semiconductor region 222 above 262 can be considered a surface of the layer of silicon dioxide) in the SOI substrate. Re: Dependent Claim 11, Green, as modified by Kamgaing, discloses all the limitations of claim 10 on which this claim depends. Green, as modified by Kamgaing, further discloses: wherein forming the first conductive feature (Green, first conductive feature; Fig. 2, e.g. elements 130, and/or 132, and/or 134 can be considered a first conductive feature, Col. 2, lines 26-31 and Col. 3, lines 44-48) includes forming at least a portion of at least one of an inductor (Green, inductor; Fig. 2, element 130) and a capacitor (Green, not illustrated; Col. 21, lines 54 - 58) over the first surface (Green, upper surface; Fig. 2, element 213 can be considered a first surface of the SOI substrate) of the SOI substrate (Green, semiconductor substrate, Fig. 2, elements 110). Re: Dependent Claim 12, Green, as modified by Kamgaing, discloses all the limitations of claim 10 on which this claim depends. Green, as modified by Kamgaing, further discloses: further comprising forming a dielectric medium (Green, dielectric medium; Fig. 2, element 166) within the first cavity (Green, cavity; Fig. 2, element 160), wherein the dielectric medium has a dielectric constant less than a dielectric constant of the SOI substrate (Green, semiconductor substrate, Fig. 2, elements 110, Col. 25, lines 5-8). Re: Dependent Claim 13, Green, as modified by Kamgaing, discloses all the limitations of claim 10 on which this claim depends. Green, as modified by Kamgaing, further discloses: further comprising the steps of: forming an active region (Green, active area; Fig. 2, element 114) that includes the device (Green, transistor; Fig. 2, element 120); and forming an isolation region (Green, isolation region; Fig. 1, element 112) that includes the first conductive feature (Green, first conductive feature; Fig. 2, e.g. elements 130, and/or 132, and/or 134 can be considered a first conductive feature, Col. 2, lines 26-31 and Col. 3, lines 44-48) (Green, Fig. 1 shows a portion of element 134 contained within 112). Re: Dependent Claim 14, Green, as modified by Kamgaing, discloses all the limitations of claim 13 on which this claim depends. Green, as modified by Kamgaing, further discloses: further comprising forming a second cavity (Green, not illustrated, see attached figure) in the second surface of the SOI substrate (Green, bottom substrate surface; Fig. 2, element 210), wherein the second cavity includes a second upper cavity surface (Green, not illustrated, see attached figure of Claim 7, the top most surface of the second cavity can be considered a second upper cavity surface) defined by a surface of the active region (Green, active area; Fig. 2, element 114, the bottom portion of 114 can be considered a surface), wherein the second upper cavity surface is directly below the device (Green, transistor; Fig. 2, element 120). Claim 15 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Green (US 9871107 B2) in view of Kamgaing (US 20200219861 A1) and in further view of Akiyama (US 20200101492 A1). Re: Dependent Claim 15, Green, as modified by Kamgaing, discloses all the limitations of claim 10 on which this claim depends. Green, as modified by Kamgaing, further discloses: further comprising forming the first cavity (Green, cavity; Fig. 2, element 160), etching process (Green, Cols. 9 and 10, lines 67-19) Green, as modified by Kamgaing, does not explicitly disclose: forming the first cavity using a xenon difluorine (XeF2) etching process. Akiyama discloses: forming the first cavity (Akiyama, cavity; Fig. 8G, element 114) using a xenon difluorine (XeF2) etching process (Akiyama, dry etching with xenon difluoride, ¶ [0067]). Green, as modified by Kamgaing, discloses forming the cavity uses an etching process, and further discloses that any suitable number of etching processes can be used, but does not explicitly disclose the use of a xenon difluorine (XeF2) etching process. Akiyama discloses forming a cavity using Xenon difluoride within a layer of material for use within a device. Both Akiyama and Green, as modified by Kamgaing, disclose methods of forming a cavity within semiconductor devices and are therefore analogous art. It would be obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to use an XeF2 etching process as it is a high selectivity process allowing for more control over what is removed (Akiyama, ¶ [0040]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 6:45 AM - 4:45 PM (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NIMARTA KAUR CHOWDHARY/Examiner, Art Unit 2898 /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 18/393,186 Page 2 Art Unit: 2898 Application/Control Number: 18/393,186 Page 3 Art Unit: 2898 Application/Control Number: 18/393,186 Page 4 Art Unit: 2898 Application/Control Number: 18/393,186 Page 5 Art Unit: 2898 Application/Control Number: 18/393,186 Page 6 Art Unit: 2898 Application/Control Number: 18/393,186 Page 7 Art Unit: 2898 Application/Control Number: 18/393,186 Page 8 Art Unit: 2898 Application/Control Number: 18/393,186 Page 9 Art Unit: 2898 Application/Control Number: 18/393,186 Page 10 Art Unit: 2898 Application/Control Number: 18/393,186 Page 11 Art Unit: 2898 Application/Control Number: 18/393,186 Page 12 Art Unit: 2898 Application/Control Number: 18/393,186 Page 13 Art Unit: 2898 Application/Control Number: 18/393,186 Page 14 Art Unit: 2898 Application/Control Number: 18/393,186 Page 15 Art Unit: 2898 Application/Control Number: 18/393,186 Page 16 Art Unit: 2898
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