DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 & 11-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chainer (US 20170186728 ).
Regarding claim 1, Chainer discloses that a micro-electronic component having a front side and a back side, the component comprising:
at the front side of the component 1206-1, a front end of line (FEOL) portion comprising a plurality of semiconductor devices 110 & 108, and, on the FEOL portion, a back end of line (BEOL) portion comprising multiple interconnect levels 118 (Fig. 11 & 12);
at the back side of the component, a power delivery network (PDN) comprising multiple interconnect levels 118 (a top and bottom surfaces), and power supply terminals electrically connected to the upper interconnect level (Fig. 11 & 12); and
a plurality of via connections 1216 (through-silicon vias as TSVs) for electrically connecting the semiconductor devices 110 & 108 to the power delivery network, wherein the first and a number of subsequent levels of the PDN 108 (para. 0041-0042, note: TSV would require an insulating structure around each TSV) are formed of electrical conductors embedded in a dielectric material, and at least the two upper levels of the PDN 108 & 1216 include electrical conductors which are part of a manifold structure 1226 configured to receive therein a flow of cooling fluid flowing into and out of the manifold structure, in order to remove heat generated by the plurality of semiconductor devices in the FEOL portion (Fig. 11 & 12).
Reclaim 2, Chainer discloses that the manifold structure comprises an input port and an output port 1226 configured to direct respective input and output flows in a direction that is oriented essentially perpendicularly to the back to front direction of the component (Fig. 11 & 12, note: from an end to an another end).
Reclaim 3, Chainer discloses that the at least two upper levels of the PDN 1216 each comprise an array of parallel line-shaped conductors interconnected by via connections, so that the spacing between each pair of parallel conductors forms a fluid channel 1206-1, the conductors of each pair of adjacent levels are arranged in crosswise fashion, so that a cooling fluid is able to flow from one level to an adjacent level and back, and the manifold structure further comprises guiding elements configured to guide a cooling fluid towards and away from the at least two upper levels of conductors (Fig. 11 & 12, note: at least 3 upper levels of the PDN).
Reclaim 4, Chainer discloses that the guiding elements include a floor portion at the same level as at least the lowest level of parallel conductors, a wall portion on the floor portion comprising wall elements which define a flow path for cooling fluid towards and from the conductors of one or more upper levels, and a cover on the wall portion (Fig. 11 & 12)
Reclaim 5, Chainer discloses that the input and output ports are at the same level as the upper level of conductors of the manifold structure, and wherein the guiding elements are configured so that a cooling fluid flowing from the inlet port to the outlet port is forced to flow between first selected pairs of upper-level conductors, thereafter downwards between conductors of one or more lower levels and again upwards so as to flow towards the outlet port between second selected pairs of upper-level conductors (Fig. 11 & 12).
Reclaim 6, Chainer discloses that the guiding elements are formed of a non-electrically conductive material (dielectric fluid, R1234Zw or R245a refrigerants).
Reclaim 7, Chainer discloses that the guiding elements are formed of an electrically conductive material, and wherein an electrically non-conductive material separates the parallel conductors from the guiding elements (para. 0042, conductive fluid such as water).
Reclaim 8, Chainer discloses that the contact terminals comprise contact pads on the upper surface of the conductors of the upper level of the manifold structure (Fig. 11 & 12, solder ball requires contact pads).
Reclaim 9, Chainer discloses that the guiding elements include a cover, and wherein the cover is provided with openings configured to allow the passage of the contact pads (Fig. 11 & 12)
Regarding claim 11, Chainer discloses that a method of producing a component according to claim 1, comprising:
producing the front end of line (FEOL) portion on the front side of a semiconductor substrate 1206-1 (Fig. 11 & 12);
producing the back end of line (BEOL) portion on the front end of line portion; thereafter, attaching the front side of the substrate to a carrier 1202 (Fig. 11 & 12);
thereafter, thinning or removing the substrate from the back side (para. 0073, note chip carrier may include);
thereafter, producing a plurality of levels of the back side PDN, the plurality of levels being embedded in a dielectric material (para. 0042), then producing a planar hybrid surface formed of the dielectric material with patches of a conductive material coplanar 108 with the dielectric material (Fig. 11 & 12); and
producing the manifold structure 1226 on the planar hybrid surface, wherein the levels of the PDN included in the manifold structure are contacting the patches of conductive material on the hybrid surface (Fig. 11 & 12).
Reclaim 12 , Chainer discloses that density of the via connections the manifold structure is produced by one or more 3D printing steps (para. 0073).
Reclaim 13, Chainer discloses that the at least two upper levels of the PDN 1206-2 1206-3 each comprise an array of parallel line-shaped conductors, so that the spacing between each pair of parallel conductors forms a fluid channel, wherein the conductors of each pair of adjacent levels are arranged in crosswise fashion, so that a cooling fluid is able to flow from one level to an adjacent level and back, the manifold structure further comprising guiding elements for guiding a cooling fluid towards and away from the at least two upper levels of conductors, and wherein the conductors of the at least two upper levels are produced on the hybrid surface by a first 3D printing step, and at least some of the guiding elements are produced on the hybrid surface by a second 3D printing step (Fig. 11 & 12).
Reclaim 14, Chainer discloses that depositing a non-electrically conductive layer 1206 (dielectric fluid is passing through TSVs) on all exposed surfaces of electrical conductors of the PDN which are part of the manifold structure (Fig. 11 & 12).
Regarding claim 15, Chainer discloses that stack of interconnected semiconductor chips, wherein the upper chip is a component in accordance with claim 1, and wherein the manifold structure and the power supply terminals are oriented upwards so as to allow the supply of power to the stack via the power supply terminals (Fig. 11 & 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chainer (US 20170186728 ).
Reclaim 10, Chainer discloses that the electrical conductors of the PDN embedded in a dielectric material include crosswise arranged levels of line-shaped electrical conductors interconnected by via connections wherein the density of the via connections (Fig. 11-12).
Chainer fails to specify that the density of the via connections is between 10% and 50%.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain density of the via connections, because it would have been to obtain a certain density of the via connections to achieve better functionality by controlling electro-magnetic with controlling a density of vias.
Response to Arguments
Applicant's arguments filed on 5/21/2026 have been fully considered but they are not persuasive.
With respect to rejected claims under 35 U.S.C. 102(a)(1), applicant argues that “the multiple interconnect levels of the BEOL portion that is on the FEOL portion at the front side of the claimed micro-electronic component are not the same as the multiple interconnect levels of the PDN at the back side of the claimed micro-electronic component. Thus, feature 118 of Chainer cannot be equivalent to both the multiple interconnect levels of the BEOL portion at the front side of the component and the multiple interconnect levels of the PDN at the back side of the component.”
In response to applicant’s argument, the multiple interconnect levels of the BEOL can be considered as Chainer’s Fig. 12 since claim clearly does not limit the locational relationship with a FEOL, BEOL, PDN, and each other (i.e. , the BEOL is opposites side from FEOL in the same chip or die).
The features 118 and 1216 also, can be considered as the multiple interconnect levels of the PDS since features 118 (solders) and 1216 (TSVs) are extended and interconnected to feature 104 in features of 1206-1, 108, & 112 in different height because the plurality of features 118 and 1216 are constructed in multilevel different chips or die.
As shown below modified Fig. 12, the PDN has multilayer of interconnections to the front end of line (FEOL) and anything below the FEOL can be considered as PDN with multilayer of interconnection with feature of 118 & 1216 in different chips or die 1206-1, 108, & 112.
Claim 1 includes at the front side of the component 1206-1, a front end of line (FEOL, can be a top side of feature 1206-1) , a back end of line (BEOL, a bottom side of feature 1206-1) with multiple interconnect levels 118 (solders at the top of feature 1206-1)-1216 (interconnection TSV)-118 (other solders at the bottom of feature 1206-1).
The multiple interconnect levels (TSV with solders in 1206-1, 104, & 12) can be considered any interconnection in different heights as shown with solders 118 at the top of feature, TSVs 1216, and other solders at the bottom of feature 1206-1.
Even if Chainer has different features from claim 1, at least claim 1 limitation does not overcome the prior part (Chainer) since claim 1 is not sufficient enough to distinguish difference(s) from Chainer.
Applicant further argues that “the first and a number of subsequent levels of the PDN are formed electrical conductors embedded in a dielectric material”.
According to Chainer’s paragraph 0042 includes “TSVs would require an insulating structure around each TSV” and there are at least two levels of the PDN are electrical conductor (TSVs) embedded on at least two separated features 1206-1, 104, & 112.
Since Chainer’s Fig 12, include multilevel and plurality of TSVs with an insulating structure around each TSV, Chainer discloses at least TSVs are formed electrical conductors embedded in a dielectric material.
Furthermore, claim 1 includes that “at the back side of the component, a power delivery network comprising multiple interconnect levels, and power supply terminals - -“.
At the front side of the component and at the back side of the component can be shown in modified Fig. 12 below.
Anything above font end of line can be considered as the front side of the component and anything below the front side of the component can be the back side of the component.
Furthermore, a power delivery network (PDN) can be considered plurality of solder and TSVs to show multilevel interconnections and plurality of connections are on right and left of the chips or dies 104 & 1206-1 since claim does not clearly define the how a power delivery network relates with the front side, back side, how vias are connected in PDN in a meaning of multilevel interconnections and only defines “a plurality of via connection for electrically connecting the semiconductor device to PDN” at the back side of the component.
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Applicant argument are not persuasive since at least claim 1 does not overcome Chainer’s Fig. 12.
Therefore, the rejection of claims 1-9 & 11-15 under 35 U.S.C. 102(a)(1) is deemed proper.
In addition, for the rejection of claim 10, the prima facie case of obviousness has been met and the rejection under 35 U.S.C. § 103 is deemed proper.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
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/SU C KIM/Primary Examiner, Art Unit 2899
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