DETAILED ACTION
This action is responsive to the following communication: the response filed 10/15/2025. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-7 and 9-21 pending.
Claim Objections
The claim(s) is/are objected to because of the following informalities:
Claim 1: it appears that “the first pair of bit lines” in line(s) 4 was meant to be -- a first pair of bit lines --.
Claim 2: it appears that “the first two respective binary signals” in line(s) 6 was meant to be -- a first two respective binary signals --.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2017/0047113 ‒hereinafter Kim).
The disclosure of fig(s). 11 and 16-17 of Kim is incorporated into an embodiment as considered below, since elements are analogous and similarly referenced (para 0191, 0197-0198). Therefore, before the effective filing date of the invention, it would have been obvious to one with ordinary skill in the art to modify the figure(s) with the embodiment as taught for the purpose of improving the overall performance by increasing storage capacity without comprising the overall geometry of the device (para 0194).
Regarding claim 1, Kim discloses a memory device comprising:
a first tri-state cell (a first unit cell UCELL may have one of at least three states; fig. 12, further “the three states of cell data CD are indicated as ‘1’, ‘0’, and ‘X’” para 0200) to store a first voltage level that is one of three voltage levels (“cell data has one [any first voltage level] of at least three voltages” and “one of at least three voltages respectively corresponding to one of the at least three states of the cell data” para 0022, 0173);
wherein a first bit line (BL1; fig. 12) of the first pair of bit lines (BL1 and BL2 are considered a pair of bit lines connected to a unit cell UCELL; fig. 12) is coupled between the first tri-state cell (UCELL) and a first sense amplifier (120_1; fig. 12) and a second bit line (BL2; fig. 12) of the first pair of bit lines (BL1 and BL2) is coupled between the first tri-state cell (UCELL) and a second, different sense amplifier (120_2; fig. 12);
a second tri-state cell (array 110c may include a plurality of unit cells array 110c, i.e. a second unit cell UCELL having one of at least three states; fig. 12, further “the three states of cell data CD are indicated as ‘1’, ‘0’, and ‘X’” para 0200) to store a second voltage level that is one of the three voltage levels (“cell data has one [another second voltage level] of at least three voltages” and “one of at least three voltages respectively corresponding to one of the at least three states of the cell data” para 0022, 0173); and
three input/output lines (any three of input/output lines BIT1-BITn to input/output sense amplifier 180d; fig. 16 para 0216) to access (i.e. for read/write) the memory device (100c, i.e. 100d; fig. 12, 16), the three input/output lines (BIT1-BITn) to carry three respective binary signals (first through third bit data BIT1, BIT2, and BIT3, each bit data having binary signal of BIT 0/1; fig. 11, 12 para 0200) based on the first voltage level and the second voltage level (i.e. based on the first and second voltage levels of the unit cells).
Regarding claim 2, Kim discloses the memory device, further comprising:
a second pair of bit lines (an array comprises BL1-BLm bit lines; fig. 11, i.e. array 100c essentially comprises another pair of bit lines BL3 and BL4 connected to the second unit cell; fig. 12) to access (i.e. for read/write) the second tri-state cell and to carry a second two respective binary signals (BIT 0/1 corresponding to the second unit cell; fig. 11, 12) based on the second voltage level (i.e. based on the second voltage level of the second unit cell); and
logic (160; fig. 11, 12) to translate the first two respective binary signals (BIT 0/1 corresponding to the first unit cell; fig. 11, 12) and the second two respective binary signals (BIT 0/1 corresponding to the second unit cell) into the three respective binary signals (i.e. to BIT1, BIT2, and BIT3; fig. 11, 12) and to translate the three respective binary signals (i.e. from BIT1, BIT2, and BIT3 of the array; fig. 11, 12) into the first two respective binary signals and the second two respective binary signals (BIT 0/1 corresponding to the first and second unit cells).
Regarding claim 3, Kim discloses the memory device, wherein each bit line of the second pair of bit lines is coupled to a respective sense amplifier (a respective sense amplifier of a plurality of sense amplifiers of read circuit 151; fig. 12).
Claim(s) 7, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2017/0047113 ‒hereinafter Kim) in view of Ho (US 2005/0174841).
The disclosure of fig(s). 11 and 16-17 of Kim is incorporated into an embodiment as considered below, since elements are analogous and similarly referenced (para 0191, 0197-0198). Therefore, before the effective filing date of the invention, it would have been obvious to one with ordinary skill in the art to modify the figure(s) with the embodiment as taught for the purpose of improving the overall performance by increasing storage capacity without comprising the overall geometry of the device (para 0194).
Regarding claim 7, Kim discloses a memory device comprising:
tri-state memory cells (a plurality of unit cells UCELL may have one of at least three states; fig. 12, further “the three states of cell data CD are indicated as ‘1’, ‘0’, and ‘X’” para 0200), each of the tri-state memory cells (UCELL) accessible by a respective bit line (any of BL1-BLm; fig. 11, 12), groups of the bit lines (groups of bit line of each UCELL; fig. 12);
wherein each of the respective bit lines (BL1-BLm) is comprised of a pair of bit lines (BL1 and BL2 are considered a pair of bit lines connected to a unit cell UCELL, another BL3 and BL4 are considered another pair of bit lines connected to another unit cell UCELL of an array; fig. 12), wherein one bit line (BL1) of the pair of bit lines (BL1 and BL2) is coupled to a first sense amplifier (120_1; fig. 12) and another bit line (BL2) of the pair of bit lines (BL1 and BL2) coupled to a second, different sense amplifier (120_2; fig. 12).
Kim does not expressly disclose a bank comprising: a number of continuous arrays of tri-state memory cells; and a number of sub-word-line drivers interspersed between the number of continuous arrays.
Ho discloses a bank (100; fig. 1) comprising: a number of continuous arrays (each memory bank array 100 comprising continuous arrays of row 150, i.e. comprising additional rows and columns of cells; fig. 1, para 0034) of tri-state memory cells (101; fig. 1, detailed as 250; fig. 2 para 00033); and a number of sub-word-line drivers (i.e. of word line drive 241, for respectively driving word line signals sub-word-line 1-2 and sub-word-line 104; fig. 1, 2) interspersed between the number of continuous arrays (i.e. in between continuous arrays of row 150 as coupled to the tri-state cells).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kim is modifiable as taught by Ho for the purpose of improving the overall geometry of the device by scaling down to small areas and low power consumption without compromising storage capacities (para 0008 of Ho).
Regarding claim 17, Kim discloses a memory device comprising:
array (fig. 11, 12) comprising respective numbers of pairs of tri-state memory cells (a plurality of unit cells UCELL may have one of at least three states; fig. 12, further “the three states of cell data CD are indicated as ‘1’, ‘0’, and ‘X’” para 0200); each of the pairs of tri-state memory cells comprising:
a first tri-state cell (a first unit cell UCELL may have one of at least three states; fig. 12, further “the three states of cell data CD are indicated as ‘1’, ‘0’, and ‘X’” para 0200) to store a first voltage level that is one of three voltage levels (“cell data has one [any first voltage level] of at least three voltages” and “one of at least three voltages respectively corresponding to one of the at least three states of the cell data” para 0022, 0173);
the first tri-state cell accessible by a first pair of bit lines (BL1 and BL2 are considered a pair of bit lines connected to a unit cell UCELL; fig. 12), the first pair of bit lines to carry a first two binary signals (BIT 0/1 corresponding to BL1 and BL2; fig. 11, 12) based on the first voltage level (i.e. based on the first voltage level of the first unit cell), each bit line of each first pair of bit lines (BL1 and BL2) coupled to different sense amplifiers (120_1 and 120_2, respectively; fig. 12); and
a second tri-state cell (array 110c may include a plurality of unit cells array 110c, i.e. a second unit cell UCELL having one of at least three states; fig. 12, further “the three states of cell data CD are indicated as ‘1’, ‘0’, and ‘X’” para 0200) to store a second voltage level that is one of the three voltage levels (“cell data has one [another second voltage level] of at least three voltages” and “one of at least three voltages respectively corresponding to one of the at least three states of the cell data” para 0022, 0173), the second tri-state cell accessible by a second pair of bit lines (the array comprises BL1-BLm bit lines; fig. 11, i.e. array 100c essentially comprises another pair of bit lines BL3 and BL4 connected to the second unit cell; fig. 12), the second pair of bit lines to carry a second two binary signals (BIT 0/1 corresponding to BL3 and BL4; fig. 11, 12) based on the second voltage level (i.e. based on the second voltage level of the second unit cell), each bit line of each second pair of bit lines (BL3 and BL4) coupled to different sense amplifiers (plurality of sense amplifiers 120 essentially comprises another different sense amplifiers, i.e. 120_3 and 120_4, coupled to BL3 and BL4, respectively; fig. 12);
three input/output lines (any three of input/output lines BIT1-BITn to input/output sense amplifier 180d; fig. 16 para 0216) for each pair of tri-state memory cells (UCELL), the three input/output lines (BIT1-BITn) to carry three respective binary signals (first through third bit data BIT1, BIT2, and BIT3, each bit data having binary signal of BIT 0/1; fig. 11, 12 para 0200) based on the first voltage level and the second voltage level (i.e. based on the first and second voltage levels of the unit cells) of the pair of tri-state memory cells (UCELL);
logic (160; fig. 11, 12) to translate respective first two binary signals (BIT 0/1 corresponding to the first unit cell; fig. 11, 12) and second two binary signals (BIT 0/1 corresponding to the second unit cell; fig. 11, 12) of a pair of tri-state memory cells into respective three binary signals (i.e. to BIT1, BIT2, and BIT3; fig. 11, 12) and to translate the respective three binary signals (i.e. from BIT1, BIT2, and BIT3 of the array; fig. 11, 12) into the respective first two binary signals and second two binary signals (BIT 0/1 corresponding to the first and second unit cells).
Kim does not expressly disclose a number of continuous arrays; column-select lines associated with groups of pairs of bit lines; and a number of sub-word-line drivers interspersed between the number of continuous arrays.
Ho discloses a number of continuous arrays (each memory array 100 comprising continuous arrays of row 150, i.e. comprising additional rows and columns of cells; fig. 1, para 0034); column-select lines (247; fig. 2) associated with groups of pairs of bit lines (252/254); and a number of sub-word-line drivers (i.e. of word line drive 241, for respectively driving word line signals sub-word-line 102 and sub-word-line 104; fig. 1, 2) interspersed between the number of continuous arrays (i.e. in between continuous arrays of row 150 as coupled to the tri-state cells).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kim is modifiable as taught by Ho for the purpose of improving the overall geometry of the device by scaling down to small areas and low power consumption without compromising storage capacities (para 0008 of Ho).
Allowable Subject Matter
Claim(s) 4-6, 9-16, 18-21 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 4 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely when the first voltage level is a first one of the three voltage levels, the first pair of bit lines are both low; when the first voltage level is a second one of the three voltage levels, one of the first pair of bit lines is low and the other of the first pair of bit lines is high; when the first voltage level is a third one of the three voltage levels, the first pair of bit lines are both high; when the second voltage level is the first one of the three voltage levels, the second pair of bit lines are both low; when the second voltage level is the second one of the three voltage levels, one of the second pair of bit lines is low and the other of the second pair of bit lines is high; and when the second voltage level is the third one of the three voltage levels, the first pair of bit lines are both high.
With respect to dependent claim 9, 11, 13, 15 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely wherein the number of continuous arrays comprises ten/nine/eight continuous arrays; wherein each of the number of continuous arrays comprises three/two column planes; wherein each of the column planes is associated with sixty-four respective column-select lines; and wherein each of the column-select lines is associated with a respective group of six/nine/ten/twelve bit lines.
With respect to dependent claim 18, 19, 20, 21 the prior art fails to teach or suggest the claimed limitations, namely wherein the number of continuous arrays comprises ten/nine/eight continuous arrays; wherein each of the number of continuous arrays comprises three/two column planes; wherein each of the column planes is associated with sixty-four respective column-select lines; wherein each column plane is associated with three hundred eighty-four/ five hundred seventy six/six hundred forty/seven hundred sixty eight pairs of bit lines; and wherein each of the column-select lines is associated with a respective group of six/nine/ten/twelve pairs of bit lines.
The allowable claims are supported in at least para 0050-0079 of the instant application.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN SMET whose telephone number is (571) 272-2267. The examiner can normally be reached M-F, 9 AM-5 PM.
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/UYEN SMET/
Primary Examiner, Art Unit 2824______