Prosecution Insights
Last updated: July 17, 2026
Application No. 18/393,354

MANAGING TRAP-UP IN A MEMORY SYSTEM

Non-Final OA §112
Filed
Dec 21, 2023
Priority
Jan 06, 2023 — provisional 63/437,535
Examiner
LUONG, DUY HAN
Art Unit
2825
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
3 (Non-Final)
94%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
34 granted / 36 resolved
+26.4% vs TC avg
Moderate +9% lift
Without
With
+9.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
19 currently pending
Career history
63
Total Applications
across all art units

Statute-Specific Performance

§103
86.1%
+46.1% vs TC avg
§102
9.0%
-31.0% vs TC avg
§112
3.3%
-36.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 36 resolved cases

Office Action

§112
DETAILED ACTION This action is responsive to the following communications: the Amendment filed on May 12, 2026. Claims 1-9 and 12-22 are pending. Claims 10-11 are canceled. Claims 21-22 are newly added. Claims 1, 12-13, 18 and 20 are amended. Claims 1, 18 and 20 are independent. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 12, 2026 has been entered by way of the RCE filed 5/28/26. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-9 and 12-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. With respect to independent claims 1, 18 and 20, each claim recites “wherein the P/E cycle lowers a voltage threshold distribution of a select line connected to the dummy word line based at least in part on disrupting a positive feedback loop, associated with increased voltage thresholds, between the dummy word line and the select line”. The specification as originally filed does not reasonable convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of a method in which the recited P/E cycle lowers a voltage threshold distribution of a select line. The specification discloses that increased trap-up in an oxide layer associated with a dummy word line may cause increased trap-up in an oxide layer associated with an adjacent select line, and vice versa, thereby forming a positive feedback loop [para. 71-72]. The specification further discloses that adjusting a de-bias voltage applied to the dummy word line may release charge from the oxide layer of the dummy word line and may improve the trap-up condition of the dummy word line and, by proxy the trap-up condition for an adjacent select line by inhibiting the positive feedback loop [para. 73]. Paragraphs 78 and 91 similarly disclose that restoring a high threshold voltage dummy word line may disrupt a positive feedback loop and reduce the occurrence of high threshold voltage select lines. However, these disclosures do not describe that performing the claimed P/E cycle causes a threshold voltage distribution of the select line to shift downward. Disrupting the positive feedback loop may prevent, reduce or slow additional trap-up in the select line without necessarily lowering the select line’s threshold voltage distribution. In contrast, where the specification expressly describes a downward shift of a threshold voltage distribution following one or more program and erase operations using the lowered de-bias voltage, that disclosure concerns the threshold voltage distribution of the dummy word line [para. 104]. The specification does not similarly disclose measuring a select line’s threshold voltage distribution before and after the P/E cycle or determining that select line’s distribution shifted downward as a result of the P/E cycle. Accordingly, although the specification may suggest that recovery of the dummy word line can improve the operating condition of an adjacent select line or reduce select line’s trap-up, the specification does not reasonably convey possession of the claimed result that the P/E cycle lowers a voltage threshold distribution of a select line. Claims 2-9, 12-17, 19 and 21-22 are rejected for inheriting this issue from claims 1, 18 and 20. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY H LUONG/Examiner, Art Unit 2825 /ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
Read full office action

Prosecution Timeline

Dec 21, 2023
Application Filed
Aug 27, 2025
Non-Final Rejection mailed — §112
Nov 26, 2025
Response Filed
Mar 12, 2026
Final Rejection mailed — §112
May 12, 2026
Response after Non-Final Action
May 28, 2026
Request for Continued Examination
Jun 02, 2026
Response after Non-Final Action
Jul 02, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12676194
INTERFACES BETWEEN HIGHER VOLTAGE AND LOWER VOLTAGE WAFERS AND RELATED APPARATUSES AND METHODS
3y 1m to grant Granted Jul 07, 2026
Patent 12665037
MEMORY DEVICE INCLUDING CHARGE PUMP FOR GENERATING VOLTAGE AND OPERATING METHOD THEREOF
2y 4m to grant Granted Jun 23, 2026
Patent 12658264
MEMORY DEVICE PERFORMING ERASE OPERATION AND METHOD OF OPERATING THE SAME
3y 0m to grant Granted Jun 16, 2026
Patent 12658259
ADDRESS COUNTER USING ASYNCHRONOUS INPUT AND OPERATING METHOD THEREOF
2y 6m to grant Granted Jun 16, 2026
Patent 12645589
HALF LATCH LEVEL SHIFTING CIRCUIT FOR NON-VOLATILE MEMORY ARCHITECTURES
4y 0m to grant Granted Jun 02, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
94%
Grant Probability
99%
With Interview (+9.1%)
2y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 36 resolved cases by this examiner. Grant probability derived from career allowance rate.

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