DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on November 26, 2025.
Claims 1-20 are pending. Claims 1-2, 4-5, 7-9, 11-12, 14 and 17-20 are amended. Claims 1, 18 and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on November 26, 2025. These drawings are acceptable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, 11, 13 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 20210225452), in view of Hemink et al. (US 20080019164) as supported by Liikanen et al. (US 10446241).
Regarding independent claim 1, Yoon et al. disclose a method, comprising:
receiving a request to erase a block of a memory device [Fig. 13: S100];
performing, at a first time and based on the request, a scan operation for determining whether a threshold voltage distribution for a dummy word line associated with the block satisfies one or more criteria [see Fig. 14, which is an expansion of Figure 13’s step S200 as indicated in para. 97; Note Fig. 14: S510, the read operation may be performed on the dummy cells to detect the threshold voltage distribution of the dummy cells using a reference threshold voltage Vs. As a result of reading the dummy cells, it may be determined whether the number of dummy cells whose threshold voltages are equal to or higher than the reference threshold voltage Vs is greater than a first predetermined number N, para. 99-100];
determining, based on the scan operation, whether to perform erase on the block using a first voltage level for a de-biasing operation of the P/E cycle [Fig. 13, S200-S400, if the dummy cells have deteriorated (S200), the device changes an unused line erase condition (S300) and performs an erase operation (operation S400); if the dummy cells have not deteriorated (S200), the erase verify operation is not performed on the dummy cells because the erase operation itself is not performed on the dummy cells, and an erase operation may be performed on a memory block (operation S402) and then completed, para. 97-98], and
performing an operation to manage the block of the memory device based on whether the P/E cycle is performed [Fig. 14: S530, if the dummy cell distribution remains bad, the controller designated the block as a bad block; otherwise, it keeps the block in normal use, para. 100-103].
However, Yoon et al. is silent with respect to perform a program and erase (P/E) cycle on the block after the scan using a first voltage level for a de-biasing operation of the P/E cycle and the first voltage level being lower than a second voltage level for a prior de-biasing operation of a prior P/E cycle performed on the block.
Hemink et al. teach perform a program and erase (P/E) cycle on the block using a first voltage level for a de-biasing operation of the P/E cycle [Hemink et al. disclose a soft-programming after erase to narrow the distribution of erased threshold voltages for the erased memory cells, see Fig. 7: step 340-342, para. 67] and the first voltage level being lower than a second voltage level for a prior de-biasing operation of a prior P/E cycle performed on the block [para. 22].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yoon et al. to the teaching of Hemink et al. such that when Yoon et al.’s dummy cell scan indicates another program and erase cycle is required, the controller performs a program and erase (P/E) cycle on the block and issues the next erase pulse at a voltage level that is lower than the erase pulse used in the prior cycle as taught by Hemink et al. to avoid over-erasing the memory cells and more accurately position an erased threshold voltage distribution [see Hemink et al.’s para. 22].
Yoon et al. in combination with Hemink et al. are silent to the term trap-up detection and that trap-up indicates charge in an oxide layer. However, Yoon et al. in combination with Hemink et al. perform the same process on the dummy word line to determine the same effect (i.e., whether the dummy cells’ threshold voltage has drifted out of range). This would indicate the term trap-up is just a different word used by applicant, and although a reference must teach the limitations of the claim, identity of terminology is not required (see MPEP 2131).
Supporting this position, Liikanen et al. explain in columns 7-8 (col. 7, ln. 65-col. 8, ln. 12), as a memory cell is repeatedly programmed and erased, its threshold voltage drifts higher due to, for example, the trapping of electrons in the tunnel oxide. In this regard, Liikanen et al. support the position that Yoon et al. and Hemink et al., as combined, detection of threshold voltage of cells along the dummy word line would yield the same identification of trap-up criteria indicating charge in an oxide layer, as claimed.
Regarding claim 2, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 1.
Furthermore, Yoon et al. disclose further comprising:
determining, based on the trap-up detection scan operation, that the threshold voltage distribution for the dummy word line satisfies the one or more trap-up criteria, wherein determining whether to perform the P/E cycle comprises determining to perform the P/E cycle based on the threshold voltage distribution for the dummy word line satisfying the one or more trap-up criteria [Fig. 6: S210, the read operation may be performed on the dummy cells to detect the threshold voltage distribution of the dummy cells using a reference threshold voltage Vs. As a result of reading the dummy cells, it may be determined whether the number of dummy cells whose threshold voltages are equal to or higher than the reference threshold voltage Vs is greater than a first predetermined number N, para. 69-70];
However, Yoon et al. is silent with respect to perform the P/E cycle based on determining to perform the P/E cycle. Yoon et al. perform erase only after the scan [Fig. 13, S200-S500, if the dummy cells have deteriorated (S200), the device changes an unused line erase condition (S300) and performs an erase operation (operation S400); if the dummy cells have not deteriorated (S200), the erase verify operation is not performed on the dummy cells because the erase operation itself is not performed on the dummy cells, and an erase operation may be performed on a memory block (operation S402) and then completed, para. 97-98].
Hemink et al. teach perform a program and erase (P/E) cycle on the block based on determining to perform the P/E cycle [Hemink et al. disclose a soft-programming after erase, see Fig. 7: step 340-342, para. 67].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yoon et al. to the teaching of Hemink et al. such that when Yoon et al.’s dummy cell scan indicates another program and erase cycle is required, the controller performs a program and erase (P/E) cycle on the block as taught by Hemink et al. to avoid over-erasing the memory cells and more accurately position an erased threshold voltage distribution [see Hemink et al.’s para. 22].
Regarding claim 3, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 2.
Furthermore, Yoon et al. disclose wherein performing the P/E cycle comprises:
applying a de-bias voltage having the first voltage level to the dummy word line [para. 93].
Regarding claim 4, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 1.
Furthermore, Yoon et al. disclose further comprising:
performing, at a second time that occurs after the P/E cycle is performed, the trap-up detection scan operation for the dummy word line [Fig. 14: S510 with respect to Fig. 13: S500, para. 99]; and
storing, in the memory device, a second threshold voltage distribution for the dummy word line based on performing the trap-up detection scan operation at the second time [the read operation may be performed on the dummy cells to detect the threshold voltage distribution of the dummy cells using a reference threshold voltage Vs, para. 99].
Regarding claim 5, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 1.
Furthermore, Yoon et al. disclose further comprising:
comparing, based on the P/E cycle being performed, a first threshold voltage distribution with a second threshold voltage distribution [para. 102-103], wherein:
the first threshold voltage distribution is measured for the dummy word line after the trap-up detection scan operation is performed at the first time [Fig. 6: S210, para. 69] and the second threshold voltage distribution is measured for the dummy word line after the P/E cycle is performed and the trap-up detection scan operation is performed at a second time [Fig. 14: S510 with respect to Fig. 13: S500, para. 99]; and
determining whether the second threshold voltage distribution has changed relative to the first threshold voltage distribution [Fig. 14: S520, para. 106-107], wherein performing the operation to manage the block of the memory device is based on determining whether the second threshold voltage distribution is changed [Fig. 14: S530, para. 102-103].
Regarding claim 7, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 1.
Furthermore, Yoon et al. disclose wherein performing the operation to manage the block of the memory device comprises:
marking the block as susceptible to trap-up based on a second threshold voltage distribution being unchanged relative to a first threshold voltage distribution [Fig. 14: S530, para. 102-103], wherein the first threshold voltage distribution is measured for the dummy word line after the trap-up detection scan operation is performed at the first time [Fig. 6: S210, para. 69] and the second threshold voltage distribution is measured for the dummy word line after the P/E cycle is performed and the trap-up detection scan operation is performed at a second time [Fig. 14: S510 with respect to Fig. 13: S500, para. 99].
Regarding claim 8, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 1.
Furthermore, Yoon et al. disclose further comprising:
determining whether a second threshold voltage distribution for the dummy word line satisfies the one or more trap-up criteria based on the second threshold voltage distribution being changed relative to a first threshold voltage distribution [Fig. 14: S520, the controller compares the new read result with the second predetermined number N, para. 102-103], wherein:
the first threshold voltage distribution is measured for the dummy word line after the trap-up detection scan operation is performed at the first time [Fig. 6: S210, para. 69] and the second threshold voltage distribution is measured for the dummy word line after the P/E cycle is performed and the trap-up detection scan operation is performed at a second time [Fig. 14: S510 with respect to Fig. 13: S500, para. 99]; and
performing the operation to manage the block of the memory device comprises marking, based on determining that the second threshold voltage distribution fails to satisfy the one or more trap-up criteria, the block as a usable block [when the count is not greater than N, the erase verification operation may be completed and the block is not designated as a bad block, so it remains available for normal program/erase operations, para. 103].
Regarding claim 11, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 1.
Furthermore, Yoon et al. disclose further comprising:
performing, based on the request, a second trap-up detection scan operation for determining whether a threshold voltage distribution for a select line associated with the block satisfies the one or more trap-up criteria, wherein the trap-up detection scan operation is performed as part of the second scan operation [para. 10], and wherein the select line and the dummy word line are electrically coupled with one another [see Fig. 2, para. 54-55 and 57-58].
Regarding claim 13, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 11.
Furthermore, Yoon et al. disclose wherein: the dummy word line is connected to a plurality of memory cells in the memory device that are prevented from storing data in the memory device [para. 53].
Regarding independent claim 18, Yoon et al. disclose an apparatus, comprising:
a memory device [Fig. 1, para. 38]; and
a controller [Fig. 1: 150] coupled with the memory device [para. 44-47] and configured to cause the apparatus to:
receive a request to erase a block of a memory device [Fig. 5: S100, para. 67];
perform, at a first time and based on the request, a scan operation for determining whether a threshold voltage distribution for a dummy word line associated with the block satisfies one or more criteria [see Fig. 14, which is an expansion of Figure 13’s step S200 as indicated in para. 97; Note Fig. 14: S510, the read operation may be performed on the dummy cells to detect the threshold voltage distribution of the dummy cells using a reference threshold voltage Vs. As a result of reading the dummy cells, it may be determined whether the number of dummy cells whose threshold voltages are equal to or higher than the reference threshold voltage Vs is greater than a first predetermined number N, para. 99-100];
determining, based on the scan operation, whether to perform erase on the block using a first voltage level for a de-biasing operation of the P/E cycle [Fig. 13, S200-S400, if the dummy cells have deteriorated (S200), the device changes an unused line erase condition (S300) and performs an erase operation (operation S400); if the dummy cells have not deteriorated (S200), the erase verify operation is not performed on the dummy cells because the erase operation itself is not performed on the dummy cells, and an erase operation may be performed on a memory block (operation S402) and then completed, para. 97-98], and
performing an operation to manage the block of the memory device based on whether the P/E cycle is performed [Fig. 14: S530, if the dummy cell distribution remains bad, the controller designated the block as a bad block; otherwise, it keeps the block in normal use, para. 100-103].
However, Yoon et al. is silent with respect to perform a program and erase (P/E) cycle on the block after the scan using a first voltage level for a de-biasing operation of the P/E cycle and the first voltage level being lower than a second voltage level for a prior de-biasing operation of a prior P/E cycle performed on the block.
Hemink et al. teach perform a program and erase (P/E) cycle on the block using a first voltage level for a de-biasing operation of the P/E cycle [Hemink et al. disclose a soft-programming after erase to narrow the distribution of erased threshold voltages for the erased memory cells, see Fig. 7: step 340-342, para. 67] and the first voltage level being lower than a second voltage level for a prior de-biasing operation of a prior P/E cycle performed on the block [para. 22].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yoon et al. to the teaching of Hemink et al. such that when Yoon et al.’s dummy cell scan indicates another program and erase cycle is required, the controller performs a program and erase (P/E) cycle on the block and issues the next erase pulse at a voltage level that is lower than the erase pulse used in the prior cycle as taught by Hemink et al. to avoid over-erasing the memory cells and more accurately position an erased threshold voltage distribution [see Hemink et al.’s para. 22].
Yoon et al. in combination with Hemink et al. are silent to the term trap-up detection and that trap-up indicates charge in an oxide layer. However, Yoon et al. in combination with Hemink et al. perform the same process on the dummy word line to determine the same effect (i.e., whether the dummy cells’ threshold voltage has drifted out of range). This would indicate the term trap-up is just a different word used by applicant, and although a reference must teach the limitations of the claim, identity of terminology is not required (see MPEP 2131).
Supporting this position, Liikanen et al. explain in columns 7-8 (col. 7, ln. 65-col. 8, ln. 12), as a memory cell is repeatedly programmed and erased, its threshold voltage drifts higher due to, for example, the trapping of electrons in the tunnel oxide. In this regard, Liikanen et al. support the position that Yoon et al. and Hemink et al., as combined, detection of threshold voltage of cells along the dummy word line would yield the same identification of trap-up criteria indicating charge in an oxide layer, as claimed.
Regarding claim 19, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 1.
Furthermore, Yoon et al. disclose wherein the controller is further configured to cause the apparatus to:
determine, based on the trap-up detection scan operation, that the threshold voltage distribution for the dummy word line satisfies the one or more trap-up criteria, wherein, to determine whether to perform the P/E cycle, the controller is further configured to cause the apparatus to determine to perform the P/E cycle based on the threshold voltage distribution for the dummy word line satisfying the one or more trap-up criteria [Fig. 6: S210, the read operation may be performed on the dummy cells to detect the threshold voltage distribution of the dummy cells using a reference threshold voltage Vs. As a result of reading the dummy cells, it may be determined whether the number of dummy cells whose threshold voltages are equal to or higher than the reference threshold voltage Vs is greater than a first predetermined number N, para. 69-70]; and
However, Yoon et al. is silent with respect to perform the P/E cycle based on determining to perform the P/E cycle. Yoon et al. perform erase only after the scan [Fig. 13, S200-S500, if the dummy cells have deteriorated (S200), the device changes an unused line erase condition (S300) and performs an erase operation (operation S400); if the dummy cells have not deteriorated (S200), the erase verify operation is not performed on the dummy cells because the erase operation itself is not performed on the dummy cells, and an erase operation may be performed on a memory block (operation S402) and then completed, para. 97-98].
Hemink et al. teach perform a program and erase (P/E) cycle on the block based on determining to perform the P/E cycle [Hemink et al. disclose a soft-programming after erase, see Fig. 7: step 340-342, para. 67].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yoon et al. to the teaching of Hemink et al. such that when Yoon et al.’s dummy cell scan indicates another program and erase cycle is required, the controller performs a program and erase (P/E) cycle on the block as taught by Hemink et al. to avoid over-erasing the memory cells and more accurately position an erased threshold voltage distribution [see Hemink et al.’s para. 22].
Regarding independent claim 20, Yoon et al. disclose a non-transitory, computer-readable medium that stores code comprising instructions that are executable by a processor of an electronic device to cause the electronic device [para. 44-47] to:
receive a request to erase a block of a memory device [Fig. 5: S100, para. 67];
perform, at a first time and based on the request, a scan operation for determining whether a threshold voltage distribution for a dummy word line associated with the block satisfies one or more criteria [see Fig. 14, which is an expansion of Figure 13’s step S200 as indicated in para. 97; Note Fig. 14: S510, the read operation may be performed on the dummy cells to detect the threshold voltage distribution of the dummy cells using a reference threshold voltage Vs. As a result of reading the dummy cells, it may be determined whether the number of dummy cells whose threshold voltages are equal to or higher than the reference threshold voltage Vs is greater than a first predetermined number N, para. 99-100];
determining, based on the scan operation, whether to perform erase on the block using a first voltage level for a de-biasing operation of the P/E cycle [Fig. 13, S200-S400, if the dummy cells have deteriorated (S200), the device changes an unused line erase condition (S300) and performs an erase operation (operation S400); if the dummy cells have not deteriorated (S200), the erase verify operation is not performed on the dummy cells because the erase operation itself is not performed on the dummy cells, and an erase operation may be performed on a memory block (operation S402) and then completed, para. 97-98], and
performing an operation to manage the block of the memory device based on whether the P/E cycle is performed [Fig. 14: S530, if the dummy cell distribution remains bad, the controller designated the block as a bad block; otherwise, it keeps the block in normal use, para. 100-103].
However, Yoon et al. is silent with respect to perform a program and erase (P/E) cycle on the block after the scan using a first voltage level for a de-biasing operation of the P/E cycle and the first voltage level being lower than a second voltage level for a prior de-biasing operation of a prior P/E cycle performed on the block.
Hemink et al. teach perform a program and erase (P/E) cycle on the block using a first voltage level for a de-biasing operation of the P/E cycle [Hemink et al. disclose a soft-programming after erase to narrow the distribution of erased threshold voltages for the erased memory cells, see Fig. 7: step 340-342, para. 67] and the first voltage level being lower than a second voltage level for a prior de-biasing operation of a prior P/E cycle performed on the block [para. 22].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yoon et al. to the teaching of Hemink et al. such that when Yoon et al.’s dummy cell scan indicates another program and erase cycle is required, the controller performs a program and erase (P/E) cycle on the block and issues the next erase pulse at a voltage level that is lower than the erase pulse used in the prior cycle as taught by Hemink et al. to avoid over-erasing the memory cells and more accurately position an erased threshold voltage distribution [see Hemink et al.’s para. 22].
Yoon et al. in combination with Hemink et al. are silent to the term trap-up detection and that trap-up indicates charge in an oxide layer. However, Yoon et al. in combination with Hemink et al. perform the same process on the dummy word line to determine the same effect (i.e., whether the dummy cells’ threshold voltage has drifted out of range). This would indicate the term trap-up is just a different word used by applicant, and although a reference must teach the limitations of the claim, identity of terminology is not required (see MPEP 2131).
Supporting this position, Liikanen et al. explain in columns 7-8 (col. 7, ln. 65-col. 8, ln. 12), as a memory cell is repeatedly programmed and erased, its threshold voltage drifts higher due to, for example, the trapping of electrons in the tunnel oxide. In this regard, Liikanen et al. support the position that Yoon et al. and Hemink et al., as combined, detection of threshold voltage of cells along the dummy word line would yield the same identification of trap-up criteria indicating charge in an oxide layer, as claimed.
Claims 6, 9-10, 12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 20210225452), in view of Hemink et al. (US 20080019164), as supported by Liikanen et al. (US 10446241), as applied to claim 1 above, and further in view of Zainuddin et al. (US 20230058038).
Regarding claim 6, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 5 above.
Furthermore, Yoon et al. disclose further comprising:
determining that P/E cycles associated with the dummy word line have been performed using the first voltage level for respective de-biasing operations [Fig. 13, S200-S400, if the dummy cells have deteriorated (S200), the device changes an unused line erase condition (S300) and performs an erase operation (operation S400); if the dummy cells have not deteriorated (S200), the erase verify operation is not performed on the dummy cells because the erase operation itself is not performed on the dummy cells, and an erase operation may be performed on a memory block (operation S402) and then completed, para. 97-98], wherein the first threshold voltage distribution is compared with the second threshold voltage distribution [para. 102-103].
However, Yoon et al. are silent with respect to determining that a threshold quantity of P/E cycles associated with the dummy word line have been performed using the first voltage level for respective de-biasing operation.
Zainuddin et al. teach determining that a threshold quantity of P/E cycles associated with the dummy word line have been performed using the first voltage level for respective de-biasing operation [see Fig. 11A: step 1102-1103, para. 171].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yoon et al. in combination with Hemink et al. to the teaching of Zainuddin et al. such that incorporating the P/E counter logic as taught by Zainuddin et al. into the dummy word line monitoring scheme as taught by Yoon et al. in combination with Hemink et al. to reduce damage to memory cells [see Zainuddin et al.’s para. 57].
Regarding claim 9, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 1 above.
Furthermore, Yoon et al. disclose further comprising:
determining whether a second threshold voltage distribution for the dummy word line satisfies the one or more trap-up criteria based on the second threshold voltage distribution being changed relative to a first threshold voltage distribution [Fig. 14: S520, the controller compares the new read result with the second predetermined number N, para. 102-103], wherein:
the first threshold voltage distribution is measured for the dummy word line after the trap-up detection scan operation is performed at the first time [Fig. 6: S210, para. 69] and the second threshold voltage distribution is measured for the dummy word line after the P/E cycle is performed and the trap-up detection scan operation is performed at a second time [Fig. 14: S510 with respect to Fig. 13: S500, para. 99]; and
However, Yoon et al. are silent with respect to performing a second P/E cycle associated with the dummy word line using a third voltage level for a second de-biasing operation.
Zainuddin et al. teach performing a second P/E cycle associated with the dummy word line using a third voltage level for a second de-biasing operation [Fig. 11D: step 1120-1121-1122, described an erase loop that a decision step 1122 determines whether a next erase loop is needed in the erase operation. When the decision step is true, e.g., when erasing is not yet completed for all or nearly all of the memory cells, step 1123 steps up the erase voltage and step 1121 follows for a further erase loop, para. 177-179].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yoon et al. in combination with Hemink et al. to the teaching of Zainuddin et al. such that applying the repeated erase sequence as taught by Zainuddin et al. to the dummy word line maintenance flow as taught by Yoon et al. in combination with Hemink et al. so that when the dummy word line verify fails, the controller simply performs another low voltage erase loop instead of discarding the block, thereby reducing threshold voltages margin loss and recovering blocks while keeping channel stress low [see Zainuddin et al.’s para. 167-170].
Regarding claim 10, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, and Zainuddin et al. teach the limitation with respect to claim 9.
Furthermore, Zainuddin et al. disclose wherein the third voltage level is equivalent to the first voltage level [see Fig. 16D, para. 213].
Regarding claim 12, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 11 above.
Furthermore, Yoon et al. disclose the block comprises the select line and the dummy word line [see Fig. 2, para 54].
However, Yoon et al. are silent with respect to the select line and the dummy word line are electrically coupled by the oxide layer that contacts the select line and the dummy word line.
Zainuddin et al. teach the select line and the dummy word line are electrically coupled by an oxide layer [Fig. 6: 663] that contacts the select line and the dummy word line [para. 136-137].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yoon et al. in combination with Hemink et al. to the teaching of Zainuddin et al. such that the select line and the dummy word line as taught by Yoon et al. in combination with Hemink et al. are electrically coupled by an oxide layer as taught by Zainuddin et al. that contacts the select line and the dummy word line to provide a gradual transition in the channel voltage gradient [see Zainuddin et al.’s para. 127] and reduce disturb susceptibility [see Zainuddin et al.’s para. 138].
Regarding claim 14, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 1 above.
However, Yoon et al. are silent with respect to further comprising:
identifying, based on the request, a quantity of P/E cycles performed for the block; and
determining, based on the quantity of P/E cycles performed for the block, to enter a diagnostic mode for analyzing threshold voltage parameters of the block, wherein the trap-up detection scan operation is performed based on the diagnostic mode being entered.
Zainuddin et al. teach further comprising:
identifying, based on the request, a quantity of P/E cycles performed for the block [see Fig. 11A: step 1102-1103, para. 171]; and
determining, based on the quantity of P/E cycles performed for the block, to enter a diagnostic mode for analyzing threshold voltage parameters of the block [see Fig. 11A, if the decision step 1103 determines whether the count is less than a threshold is true, step 1104 performs the operation with modified SLC parameters which reduce stress on the memory cells, para. 171], wherein the scan operation is performed based on the diagnostic mode being entered [Fig. 11A: step 1100, para. 171].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yoon et al. in combination with Hemink et al. to the teaching of Zainuddin et al. such that dummy word line as taught by Yoon et al. in combination with Hemink et al. is executed in the modified parameter/diagnostic mode as taught by Zainuddin et al to reduce the stress on a set of memory cells [see Zainuddin et al.’s para. 57-58].
Regarding claim 15, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 1 above.
However, Yoon et al. are silent with respect to further comprising:
identifying, based on a second request to erase the block, a quantity of P/E cycles performed for the block;
determining, based on the quantity of P/E cycles performed for the block, to remain in a nominal operating mode; and
erasing, based on remaining in the nominal operating mode, the block using the second voltage level.
Zainuddin et al. teach further comprising:
identifying, based on a second request to erase the block, a quantity of P/E cycles performed for the block [see Fig. 11A: step 1102-1103, para. 171];
determining, based on the quantity of P/E cycles performed for the block, to remain in a nominal operating mode [see Fig. 11A, if the decision step 1103 determines whether the count is less than a threshold is false, step 1105 performs the operation with default SLC parameters, para. 171]; and
erasing, based on remaining in the nominal operating mode, the block using the second voltage level [para. 152 as well as Fig. 11B1, para. 172].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yoon et al. in combination with Hemink et al. to the teaching of Zainuddin et al. such that dummy word line as taught by Yoon et al. in combination with Hemink et al. is executed in the default parameter/nominal operating mode as taught by Zainuddin et al to reduce the stress on a set of memory cells [see Zainuddin et al.’s para. 57-58].
Regarding claim 16, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 1 above.
However, Yoon et al. are silent with respect to wherein P/E cycles are configured to use the second voltage level based on the memory device operating in a nominal operating mode and to use the first voltage level based on the memory device operating in a diagnostic mode.
Zainuddin et al. teach wherein P/E cycles are configured to use the second voltage level based on the memory device operating in a nominal operating mode and to use the first voltage level based on the memory device operating in a diagnostic mode [see Fig. 11A, if the decision step 1103 determines whether the count is less than a threshold is true, step 1104 performs the operation with modified SLC parameters which reduce stress on the memory cells; if the decision step 1103 is false, step 1105 performs the operation with default SLC parameters, para. 171].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yoon et al. in combination with Hemink et al. to the teaching of Zainuddin et al. such that dummy word line as taught by Yoon et al. in combination with Hemink et al. is executed in the modified parameter/diagnostic mode or default parameter/nominal operating mode as taught by Zainuddin et al to reduce the stress on a set of memory cells [see Zainuddin et al.’s para. 57-58].
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 20210225452), in view of Hemink et al. (US 20080019164), as supported by Liikanen et al. (US 10446241), as applied to claim 1 above, and further in view of Rajwade et al. (US 20170186497).
Regarding claim 17, Yoon et al. in combination with Hemink et al., as supported by Liikanen et al. explanation of the “trap-up” that is excess charge in the tunnel oxide after repeated program and erase cycles causing threshold voltage to drift upwards, teach the limitation with respect to claim 1 above.
However, Yoon et al. are silent with respect to wherein the trap-up detection scan operation comprises a check fail byte (CFBYTE) modulation or a read level modulation.
Rajwade et al. teach wherein the scan operation comprises a check fail byte (CFBYTE) modulation or a read level modulation [see Fig. 3D, para. 38-40 as well as para. 15-16].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yoon et al. in combination with Hemink et al. to the teaching of Rajwade et al. such that applying Rajwade et al.’s predictive CFBYTE technique to the dummy word line scan method as taught by Yoon et al. in combination with Hemink et al. to save one verify pulse per level, which amounts to about five to ten percent improvement in program performance [see Rajwade et al.’s para. 28].
Response to Arguments
Applicant's arguments filed with respect to independent claims 1, 18 and 20 have been fully considered but they are not persuasive.
With respect to independent claims 1, 18 and 20, Applicant asserted that Yoon discloses determining a threshold voltage associated with the dummy lines, and referencing it against a predetermined number. Yoon does not disclose detecting a charge in an oxide layer, and in fact does not disclose performing any kind of detection scan associated with determining trap-up. Thus, Yoon does not teach or suggest performing "a trap-up detection scan operation for determining ...trap-up criteria indicating charge in an oxide layer," as recited in amended independent claim 1, see Applicant’s Remarks page 12. In short, the argument is that the references do not use the term “trap-up” or define trap-up as the presence of electrons in the oxide layer.
This particular remark is not considered persuasive. While Yoon et al. in combination with Hemink et al. are silent to the term trap-up detection and that trap-up indicates charge in an oxide layer, the threshold drift problem they address is caused by trap-up. Yoon et al. in combination with Hemink et al. perform the same process on the dummy word line to determine the same effect (i.e., whether the dummy cells’ threshold voltage has drifted out of range). In other words, the differences applicant asserts between the claimed invention and the prior art is only a difference in terminology. Although a reference must teach the limitations of the claim, identity of terminology is not required (see MPEP 2131).
Supporting this position, Liikanen et al. explain in columns 7-8 (col. 7, ln. 65-col. 8, ln. 12), as a memory cell is repeatedly programmed and erased, its threshold voltage drifts higher due to, for example, the trapping of electrons in the tunnel oxide. In this regard, Liikanen et al. support the position that Yoon et al. and Hemink et al., as combined, detection of threshold voltage of cells along the dummy word line would yield the same identification of trap-up criteria indicating charge in an oxide layer, as claimed.
For the above reasons, the previously applied rejection is considered proper and maintained, as supported by Liikanen et al. (US 10446241) that explains the recognized threshold voltage drift property caused by electrons being trapped in the tunnel oxide layer of a memory transistor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825