Attorney’s Docket Number: 088453.8592.US00
Filing Date: 12/21/2023
Claimed Foreign Priority Date: 06/29/2023 (KR10-2023-0084346)
Applicants: Yun et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 04/10/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group Invention I (directed to a semiconductor structure), in the reply filed on 04/10/2026, is acknowledged. Applicant indicated that claims 1-13 read on the elected Group Invention. The examiner agrees. Accordingly, pending in this application are claims 1-20, with claims 14-20 standing withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group Invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 6, and 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US2024/0324243).
Regarding Claim 1, Kim (see, e.g., Figs. 2-3) shows all aspects of the instant invention, including a semiconductor device comprising:
- a substrate (e.g., comprising substrate 100, wiring insulating layer 110, and wiring structures 102 and 104)
- a pattern (e.g., magnetic tunnel junction pattern MTJ) disposed over the substrate
- a hard mask pattern (e.g., upper electrode 200/TE) that is conductive and disposed over the pattern (see, e.g., Figs. 9-10 and Par. [0067]-[0068]: upper electrode 200/TE is used as a metal etch mask to pattern MTJL, thus is also understood as a hard mask), the hard mask pattern including a lower hard mask pattern (e.g., portion of TE below upper surface 160U) and an upper hard mask pattern over the lower hard mask pattern (e.g., portion of TE above upper surface 160U)
- a conductive pattern (e.g., upper conductive line 170 or 180) disposed over the hard mask pattern and electrically connected to the pattern through the hard mask pattern
- an insulating layer (e.g., comprising capping insulating layer 150 and upper insulating layer 160) covering a sidewall of the pattern and a sidewall of the lower hard mask pattern
- wherein the upper hard mask pattern is disposed to protrude from the insulating layer (see, e.g., Fig. 3)
Regarding Claim 3, Kim (see, e.g., Fig. 3) shows that the sidewall of the lower hard mask pattern (e.g., portion of TE below upper surface 160U) and the sidewall of the pattern (e.g., MTJ) are aligned with each other.
Regarding Claim 6, Kim (see, e.g., Fig. 3) shows that the insulating layer includes a protective pattern (e.g., capping insulating layer 150) formed along sidewalls of the pattern and the lower hard mask pattern, and an insulating pattern (e.g., upper insulating layer 160) filling a space defined by the protective pattern.
Regarding Claim 13, Kim (see, e.g., Fig. 3) shows that the pattern includes a magnetic tunnel junction structure (e.g., magnetic tunnel junction pattern MTJ).
Claims 1-3, 6-8, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Weng et al. (US2020/0083428).
Regarding Claim 1, Weng (see, e.g., Fig. 7) shows all aspects of the instant invention, including a semiconductor device comprising:
- a substrate (e.g., comprising substrate 12, dielectric layers 18 and 24, and metal interconnections 26)
- a pattern (e.g., magnetic tunnel junction MTJ) disposed over the substrate
- a hard mask pattern (e.g., top electrode 78) that is conductive and disposed over the pattern (see, e.g., Figs. 1-2 and Par. [0014]: second electrode layer 52 is used as a metal etch mask to pattern the lower layers of the MTJ, thus 78 is also understood as a hard mask), the hard mask pattern including a lower hard mask pattern (e.g., portion 52 of 78) and an upper hard mask pattern over the lower hard mask pattern (e.g., portion 84 of 78)
- a conductive pattern (e.g., metal interconnection 88) disposed over the hard mask pattern and electrically connected to the pattern through the hard mask pattern
- an insulating layer (e.g., comprising dielectric liner 68/spacer 70 and dielectric layer 72) covering a sidewall of the pattern and a sidewall of the lower hard mask pattern
- wherein the upper hard mask pattern is disposed to protrude from the insulating layer (see, e.g., Fig. 7)
Regarding Claim 2, Weng (see, e.g., Fig. 7) shows that a width of the upper hard mask pattern (e.g., 84) is greater than a width of the lower hard mask pattern (e.g., 52).
Regarding Claim 3, Weng (see, e.g., Fig. 7) shows that the sidewall of the lower hard mask pattern (e.g., 52) and the sidewall of the pattern (e.g., MTJ) are aligned with each other.
Regarding Claim 6, Weng (see, e.g., Fig. 7) shows that the insulating layer includes a protective pattern (e.g., 70) formed along sidewalls of the pattern and the lower hard mask pattern, and an insulating pattern (e.g., 72) filling a space defined by the protective pattern.
Regarding Claim 7, Weng (see, e.g., Fig. 7) shows that the upper hard mask pattern (e.g., 84) covers at least a portion of an upper surface of the protective pattern (e.g., 70).
Regarding Claim 8, Weng (see, e.g., Fig. 7) shows that the upper hard mask pattern (e.g., 84) covers a portion of an upper surface of the insulating layer (e.g., 70,72).
Regarding Claim 13, Weng (see, e.g., Fig. 7) shows that the pattern includes a magnetic tunnel junction structure (e.g., magnetic tunnel junction MTJ).
Claims 1, 6, and 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yang et al. (US2023/0263069).
Regarding Claim 1, Yang (see, e.g., Fig. 6B) shows all aspects of the instant invention, including a semiconductor device comprising:
- a substrate (e.g., comprising substrate 302, dielectric layers 304 and 402, and conductive feature 404/ metal lines L4)
- a pattern (e.g., MTJ structure 418′) disposed over the substrate
- a hard mask pattern (e.g., top electrode 426) that is conductive and disposed over the pattern (see, e.g., Fig. 4D and Par. [0039]: top electrode 426 is used as a metal etch mask to pattern 418′, thus 426 is also understood as a hard mask), the hard mask pattern including a lower hard mask pattern (e.g., portion of 426 below top surface of oxide layer 442) and an upper hard mask pattern over the lower hard mask pattern (e.g., portion of 426 above top surface of oxide layer 442)
- a conductive pattern (e.g., conductive feature 460L/metal line L6) disposed over the hard mask pattern and electrically connected to the pattern through the hard mask pattern
- an insulating layer (e.g., comprising spacers 444 and oxide layer 442) covering a sidewall of the pattern and a sidewall of the lower hard mask pattern
- wherein the upper hard mask pattern is disposed to protrude from the insulating layer (see, e.g., Fig. 6B)
Regarding Claim 6, Yang (see, e.g., Fig. 6B) shows that the insulating layer includes a protective pattern (e.g., 444) formed along sidewalls of the pattern and the lower hard mask pattern, and an insulating pattern (e.g., 442) filling a space defined by the protective pattern.
Regarding Claim 13, Yang (see, e.g., Fig. 6B) shows that the pattern includes a magnetic tunnel junction structure (e.g., MTJ structure 418′).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 9-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US2024/0324243) in view of Liao et al. (US2020/0098978).
Regarding Claim 9, Kim (see, e.g., Fig. 3) shows that:
- the pattern includes a memory pattern (e.g., magnetic tunnel junction pattern MTJ)
- the substrate includes a first conductive line (e.g., wiring line 102) electrically connected to the pattern
- the conductive pattern includes a second conductive line extending in a second direction (e.g., upper conductive line 170 or 180 extending in direction D1)
However, Kim does not explicitly show that the first conductive line extends in a first direction, such that the second direction intersects the first direction. Liao (see, e.g., Figs. 1C and 20A-B), on the other hand and in the same field of endeavor, teaches that MRAM cells typically comprise a magnetic tunneling junction (MTJ) stack 330 arranged between WordLine (WL) and BitLine (BL) metal lines, to implement a crosspoint addressable MTJ-based memory, wherein the WordLine and BitLine metal lines are orthogonal to each other.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the first conductive line extending in a first direction intersecting the second direction in the structure of Kim, because such arrangement of conductive lines is well-known in the MRAM memory art for implementing a crosspoint addressable MTJ-based memory cell, as suggested by Liao, and implementing a known arrangement of conductive lines for its conventional purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 10, Kim (see, e.g., Fig. 3) shows that the second conductive line (e.g., 170) is disposed along an upper surface of the insulating layer and a surface of the upper hard mask pattern.
Regarding Claim 12, Kim (see, e.g., Fig. 3) shows:
- an additional insulating layer (e.g., interlayer insulating layer 178) covering the insulating layer and the upper hard mask pattern
- a contact plug (e.g., via contact 190) penetrating the additional insulating layer and in contact with the upper hard mask pattern
- wherein the second conductive line (e.g., 180) is disposed over the additional insulating layer and the contact plug, and is connected to the upper hard mask pattern through the contact plug.
Claims 9 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US2023/0263069) in view of Liao et al. (US2020/0098978).
Regarding Claim 9, Yang (see, e.g., Fig. 6B) shows that:
- the pattern includes a memory pattern (e.g., MTJ structure 418′)
- the substrate includes a first conductive line (e.g., conductive feature 404/metal lines L4) electrically connected to the pattern
- the conductive pattern includes a second conductive line (e.g., conductive feature 460L/metal line L6)
However, Yang does not explicitly show that the first conductive line extends in a first direction, and the second conductive line extends in a second direction such that the second direction intersects the first direction. Liao (see, e.g., Figs. 1C and 20A-B), on the other hand and in the same field of endeavor, teaches that MRAM cells typically comprise a magnetic tunneling junction (MTJ) stack 330 arranged between WordLine (WL) and BitLine (BL) metal lines, to implement a crosspoint addressable MTJ-based memory, wherein the WordLine and BitLine metal lines are orthogonal to each other. Also, see comments stated above in Par. 27 with regards to Claim 9, which are considered repeated here, as applied to Yang.
Regarding Claim 11, Yang (see, e.g., Fig. 6B) shows:
- an additional insulating layer (e.g., IMD layer 446) disposed over the insulating layer and having an upper surface forming a flat surface with an upper surface of the upper hard mask pattern
- wherein the second conductive line is disposed over the flat surface.
Regarding Claim 12, Yang (see, e.g., Fig. 6B) shows:
- an additional insulating layer (e.g., IMD layer 450) covering the insulating layer and the upper hard mask pattern
- a contact plug (e.g., via 460V) penetrating the additional insulating layer and in contact with the upper hard mask pattern
- wherein the second conductive line (e.g., 460L/L6) is disposed over the additional insulating layer and the contact plug, and is connected to the upper hard mask pattern through the contact plug.
Allowable Subject Matter
Claims 4 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited discloses MRAM structures having conductive hard mask patterns, and having some aspects of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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