Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to claim of priority to Korean Patent Application No. 10-2023-0090664, filed on July 12, 2023
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 22, 2023 is being considered by the examiner.
Drawings
The drawings were received on June 12, 2024. These drawings are acceptable.
Response to Amendment
This Office Action is in response to Applicant’s Preliminary Amendment filed June 12, 2024. Claims 3, 11, 14, and 15 are amended. The Examiner notes that claims 1-19 are examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2019/0088739 A1).
With respect to claim 1, Lee teaches in Figs. 1 and 2A:
A semiconductor device, comprising:
a plurality of first contacts (first contact plugs 126) spaced apart from each other by a predetermined distance in a semiconductor substrate (substrate 100);
a plurality of conductive structures (bit line structures BL including first conductive pattern 122, second conductive pattern 131, and mask pattern 141) formed over the first contacts (126), extending in a first direction (D2, see Fig. 1) and spaced apart in a second direction (D1) perpendicular to the first direction,
each of which partially overlaps with each of the first contacts (see Fig. 2A),
and having a top surface of a portion that overlaps with each of the first contacts at a lower level (level of portion of 141 directly below separation insulation layer 185 in the portion that overlaps the contact) than a top surface of a portion that does not overlap with each of the first contacts (portion of top surface of 141 to the side of 185 in portions of conductive structures that do not overlap the contacts.);
a plurality of second contacts (second contact structure 161) disposed between neighboring conductive structures;
and a plurality of spacer structures (spacer structure SS and gap-fill insulating layer 118) disposed between the conductive structures (BL) and the second contacts (161).
With respect to claim 2, Lee further teaches:
wherein the spacer structures have different stacked structures on sidewalls of the conductive structures that overlap with the first contacts and sidewalls of the conductive structures that do not overlap with the first contacts (see Fig. 2a, gap-fill insulating layer 118 is included on sidewalls where conductive structures overlap with first contacts but not on sidewalls that do not overlap with first contacts).
With respect to claim 3, Lee further teaches:
wherein in the spacer structures, a thickness on sidewalls of the conductive structures that overlap with the first contacts (thickness of 118) is greater than a thickness on sidewalls of the conductive structures that do not overlap with the first contacts (thickness of SS).
With respect to claim 4, Lee further teaches:
wherein the spacer structures include a stacked structure of a gap-fill spacer (118), a first spacer (first spacer 112), an air gap spacer (void VS), and a second spacer (second spacer 41) on the sidewalls of the conductive structures that overlaps with the first contacts.
With respect to claim 5, Lee further teaches:
wherein the air gap spacer (VS) partially overlaps with the conductive structure (131) in a parallel direction to the substrate surface (see Fig. 2A).
With respect to claim 6, Lee further teaches:
wherein the spacer structures include a first spacer (12) on the sidewall of the conductive structure that do not overlap with the first contact.
With respect to claim 7, Lee further teaches:
wherein a bottom surface of the first contact (bottom surface of 126) is disposed at a lower level than a top surface of the substrate (top surface of second impurity region 112b).
With respect to claim 8, Lee further teaches:
wherein the second contacts (161) are spaced apart from each other in the first direction (D2, see Fig. 1),
and further includes: a plug isolation layer (lower portions LR of fence insulating patterns 153, see Fig. 2C) gap-filling a space between the second contacts (161) that are spaced apart from each other in the first direction (D2, see Fig. 1).
With respect to claim 9, Lee further teaches:
wherein the first contact is a bit line contact (BL), and the second contact is a storage node contact (para. 43, “data storage units DS may be electrically connected to each of the second impurity regions 112b via each of the connection pads 169 and each of the second contact plugs 161.”)
With respect to claim 10, Lee further teaches:
wherein the conductive structure includes a stacked structure of a bit line (bit line conductive patterns 131, 122) and a bit line hard mask (141).
With respect to claim 11, Lee teaches:
a plurality of first contacts (first contact plugs 126) spaced apart from each other by a predetermined distance in a semiconductor substrate (substrate 100);
a plurality of first conductive structures (second conductive pattern 131 and mask pattern 141, see annotated Fig. 2A) formed over the first contacts (126); a plurality of second conductive structures (122, 131, and 141 not over 126, see annotated Fig. 2A) arranged alternately with the first conductive structure and formed over a hard mask (lower insulating patterns 101);
a plurality of second contacts (second contact plugs 161) disposed between the first conductive structures and the second conductive structures;
a plurality of first spacer structures (spacer structures SS and gap filling insulating layer 118) disposed between the first conductive structures and the second contacts;
and a plurality of second spacer structures (SS) disposed between the second contacts and the second conductive structures,
wherein a top surface of the first conductive structures is at a lower level (level of top surface of 141 in first conductive structure that is directly below 185) than a top surface of the second conductive structures (level of top surface of 141 in second conductive structure that is to the side of 185).
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With respect to claim 12, Lee further teaches:
wherein the first conductive structures and the second conductive structures are a single continuous conductive line in a first direction (D2, Fig. 1).
With respect to claim 13, Lee further teaches:
wherein the first spacer structures and the second spacer structures have different stacked structures (first spacer structures include 118 and second spacer structures do not, see Fig. 2A).
With respect to claim 14, Lee further teaches:
wherein a thickness of the first spacer structures is greater than a thickness of the second spacer structures (thickness of 118 is thicker than SS of second spacer structure).
With respect to claim 15, Lee further teaches:
wherein the first spacer structures include a stacked structure of a gap-fill spacer (118), a first spacer (first spacer 12), an air gap spacer (void VS), and a second spacer (second spacer 41).
With respect to claim 16, Lee further teaches:
wherein the second spacer structures include a first spacer (12).
With respect to claim 17, Lee further teaches:
wherein a bottom surface of the first contact (126) is disposed at a lower level than a bottom surface of the hard mask (101) (See Fig. 2A).
With respect to claim 18, Lee further teaches:
wherein the first contact is a bit line contact, and the second contact is a storage node contact (para. 43, “data storage units DS may be electrically connected to each of the second impurity regions 112b via each of the connection pads 169 and each of the second contact plugs 161.”).
With respect to claim 19, Lee further teaches:
wherein the first and second conductive structures include a stacked structure of a bit line (131) and a bit line hard mask (141).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang (US 2021/0375878 A1) teaches a device in which the uppermost level of the conductive structure above the contacts is lower than the uppermost level of the conductive structures that do not overlap with a contact and may read on claims if amended to narrow limitations about the level of the conductive structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897