DETAILED ACTION
This Office Action is in response to the Applicant Election filed on 04/26/2026.
Currently, claims 1-20 are pending in the application. Currently, claims 5, 6, 8, and 17-20 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I (claims 1-16) and Species V (Figs. 5D, 6A & 6B) in the reply filed on 04/26/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 5, 6, 8, and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-selected invention, there being no allowable generic or linking claim. Claims 1-4, 7, and 9-16 are examined in this Office action.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/22/2023 and 10/30/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being obvious over KIM et al. (US Pub. No. 2025/0062210) in view of LEE (US Pub. No. 2024/0234358).
Regarding independent claim 1, Kim teaches a semiconductor package (Figs. 6H & 12), comprising:
a first device die (Fig. 12,CH2, ¶ [0094]) and a second device die (Fig. 12, CH3, ¶ [0094]) stacked over the first device die;
functional bumps (Fig. 6H, RST, ¶¶ [0044] & [0094]), disposed between the first device die and the second device die, and electrically connected to the first device die and the second device die (Fig. 12, ¶¶ [0041]-[0044] & [0094]); and
a first seal ring (Fig. 6H, DST, ¶ [0044], [0069] & [0094]), comprising at least one dummy bump (Fig. 6H, DST, ¶ [0044], [0069] & [0094]) arranged along edges of the first device die (Figs. 6H, 7B, and 12, dummy structures DST are arranged in DR1 which are along outer edges of Kim’s semiconductor die CH2) and disposed between the first and second device dies (Fig. 12).
However, Kim does not explicitly teach that a first seal ring laterally surrounding the functional bumps.
However, Lee is a pertinent art that teaches a first seal ring (Figs. 2 &3C, 320, ¶¶ [0060], [0067] & [0073]-[0075] teaches dummy solder bumps surrounding a periphery of solder bump array 310) laterally surrounding the functional bumps (Figs. 2C &3C, 310, ¶¶ [0060], [0067] & [0073]-[0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s dummy structures to surround a periphery of their connection structures according to the teaching of Lee (Fig. 3C) in order to realize a more uniform connection between devices (Lee ¶¶ [0010] & [0030])
Regarding claim 2, Kim modified by Lee teaches the semiconductor package according to claim 1, and Kim teaches that the at least one dummy bump (Fig. 6H, DST, ¶ [0044], [0069] & [0094]) is structurally identical (Fig. 6H, DST and RST appear to be structurally identical) with the functional bumps (Fig. 6H, RST, ¶¶ [0044] & [0094]).
Regarding claim 3, Kim modified by Lee teaches the semiconductor package according to claim 1, and Kim teaches that the at least one dummy bump (Fig. 6H, DST, ¶ [0044], [0069] & [0094]) comprises multiple dummy bumps (Fig. 6H, ¶ [0069] teaches that multiple dummy structures DST can be arranged in DR1) separately arranged along the edges of the first device die (Figs. 6H, 7B, and 12, dummy structures DST are arranged in DR1 which are along outer edges of Kim’s semiconductor die CH2).
Regarding claim 4, Kim modified by Lee teaches the semiconductor package according to claim 1, and Kim modified by Lee teaches that the at least one dummy bump comprises (Kim Fig. 6H, DST, ¶ [0044], [0069] & [0094]) first (Kim modified by Lee would have dummy structures arranged along edges of their device in a same manner as Lee Fig. 3C) and second (Kim modified by Lee would have dummy structures arranged at corners of their device in a same manner as Lee Fig. 3C) segmental dummy bumps separately arranged along the edges of the first device die (Lee Fig. 3C, ¶ [0073], teaches dummy solder bumps 320 at the edges and corners of the chip 300)), each of the first segmental dummy bumps extends along a single one of the edges of the first device die (Lee Fig. 3C, it would be obvious that Kim modified by Lee’s dummy structures arranged at an edge of Kim modified by Lee’s chip would at least partially extend along an edge), and each of the second segmental dummy bumps extends along intersected ones of the edges of the first device die (Lee Fig. 3C, it would be obvious that Kim modified by Lee’s dummy structures arranged at a corner of a device would at least partially extend along two edges).
Claim 7 is rejected under 35 U.S.C. 103 as being obvious over KIM et al. (US Pub. No. 2025/0062210) in view of LEE (US Pub. No. 2024/0234358) and further in view of YU et al. (US Pub. No. 2022/0352109).
Regarding claim 7, Kim modified by Lee teaches the semiconductor package according to claim 1, and Kim modified by Lee teaches that the at least one dummy bump (Kim Fig. 6H, DST, ¶ [0044], [0069] & [0094]) comprises outer dummy bumps and inner dummy bumps, the outer dummy bumps are separately arranged along an outer annulus path close to the edges of the first device die in-between and the inner dummy bumps are separately arranged along an inner annulus path laterally surrounded by the outer annulus path (Kim Fig. 6H, ¶ [0069] teaches that there are at least two dummy structures DST between an edge of Kim’s die and the signal structures RST. Kim Fig. 2, ¶ [0039] teaches that Kim’s dummy structures, corresponding to the locations of CP2(D), can be arranged in rows along edges of Kim’s die. Kim modified by Lee’s dummy structures would extend along the periphery of Kim’s die in a similar manner to Lee Fig. 3C. Therefore, it would be obvious that Kim modified by Lee would have two rows of dummy structures along a periphery of Kim’s device in a similar manner to prior art Yu (see Yu Fig. 9, 114, ¶ [0041])).
Claims 9-11 are rejected under 35 U.S.C. 103 as being obvious over KIM et al. (US Pub. No. 2025/0062210) in view of LEE (US Pub. No. 2024/0234358) and further in view of JEE et al. (US Patent No. 9,543,276).
Regarding claim 9, Kim modified by Lee teaches the semiconductor package according to claim 1.
However, Kim modified by Lee does not explicitly teach that the first seal ring further comprises dummy through substrate vias formed into the first device die and in contact with the at least one dummy bump.
However, Jee is a pertinent art that teaches that the first seal ring (Fig. 2, 190, Col. 10 lines 43-56 teaches dummy though silicon vias 190 connected to all of the dummy bump pads 172 in their dummy connection portion D. Therefore, Kim modified by Jee’s inner and outer dummy structures DST would be connected to dummy through silicon vias) further comprises dummy through substrate vias (Fig. 2, 190, Col. 10 lines 43-56) formed into the first device die (Fig. 2, 100, Col. 7 lines 13-19) and in contact with the at least one dummy bump (Fig. 2, 172, Col. 10 lines 43-56).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s dummy structures to be connected to dummy through silicon vias according to the teaching of Jee (Fig. 2) in order to mitigate chip warpage (Jee Col. 10 lines 43-56).
Regarding claim 10, Kim modified by Lee modified by Jee teaches the semiconductor package according to claim 9, and Kim modified by Lee modified by Jee teaches that the dummy through substrate vias (Jee Fig. 2, 190, Col. 10 lines 43-56) are laterally surrounded by a second seal ring (Jee Fig. 2, 190, Col. 10 lines 43-56 teaches dummy though silicon vias 190 connected to all of the dummy bump pads 172 in their dummy connection portion D. Therefore, Kim modified by Jee’s inner and outer dummy structures DST would be connected to dummy through silicon vias. It would be obvious that the dummy through silicon vias connected to modified Kim’s inner dummy structures would be surrounded by a second ring of dummy through silicon vias connected to modified Kim’s outer dummy structures) in the first device die (Kim Fig. 12,CH2, ¶ [0094]).
Regarding claim 11, Kim modified by Lee modified by Jee teaches the semiconductor package according to claim 9, and Kim modified by Lee modified by Jee teaches a first group of the dummy through substrate vias are inserted into a second seal ring (Jee Fig. 2, 190, Col. 10 lines 43-56 teaches dummy though silicon vias 190 connected to all of the dummy bump pads 172 in their dummy connection portion D. Therefore, Kim modified by Jee’s inner and outer dummy structures DST would be connected to dummy through silicon vias. Kim modified by Lee’s outer dummy structures would surround Kim modified by Lee’s inner dummy structures and can be considered to be a second seal ring. It would be obvious that the dummy through silicon vias connected to Kim modified by Lee’s outer dummy structures would be integrally connected and can be considered to be inserted into the second seal ring formed by Kim modified by Lee’s outer dummy structures) of the first device die, and a second group (Kim modified by Lee modified by Jee’s dummy through silicon vias connected to Kim’s inner dummy structures) of the dummy through substrate vias are laterally surrounded by the second seal ring.
Claims 12-16 are rejected under 35 U.S.C. 103 as being obvious over KIM et al. (US Pub. No. 2025/0062210) in view of LEE (US Pub. No. 2024/0234358) and further in view of JUN et al. (US Pub. No. 2021/0183816).
Regarding independent claim 12, Kim teaches a semiconductor package (Figs. 6H & 12), comprising:
a first device die (Fig. 12, CH3, ¶ [0094]) and a second device die (Fig. 12,CH2, ¶ [0094]) overlapping the first device die;
functional bumps (Fig. 6H, RST, ¶¶ [0044] & [0094]), disposed between the first device die and the second device die, and electrically connected to the first device die and the second device die (Fig. 12, ¶¶ [0041]-[0044] & [0094]);
a first seal ring (Fig. 6H, DST, ¶ [0044], [0069] & [0094]), comprising at least one dummy bump (Fig. 6H, DST, ¶ [0044], [0069] & [0094]) between the first and second device dies;
a first bonding layer (Fig. 12, UF, ¶ [0045]), disposed between the first device die and the second device die, and extending along a side of the first device die facing toward the second device die (Fig. 12); and
However, Kim does not explicitly teach a first seal ring, comprising at least one dummy bump laterally surrounding the functional bumps between the first and second device dies; and
a second bonding layer, disposed between the first bonding layer and the second device die and bonded to the first bonding layer, wherein the functional bumps and the at least one dummy bump extend through the first and second bonding layers.
However, Lee is a pertinent art that teaches a first seal ring (Figs. 2 & 3C, 320, ¶¶ [0060], [0067] & [0073]-[0075] teaches dummy solder bumps 320 surrounding a periphery of solder bump array 310), comprising at least one dummy bump (Fig. 3C, 320) laterally surrounding the functional bumps (Fig. 3C, 310) between the first and second device dies (Figs. 1 & 3C, 300, ¶ [0073] teaches that Lee’s bump connectors can be connected in-between Lee’s stacked chips 101, 102, 103, and 104, which would correspond to Kim’s stacked device dies in Kim Fig. 12).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s dummy structures to surround a periphery of their connection structures according to the teaching of Lee (Fig. 3C) in order to realize a more uniform connection between devices (Lee ¶¶ [0010] & [0030]).
However, Kim modified by Lee does not explicitly teach a second bonding layer, disposed between the first bonding layer and the second device die and bonded to the first bonding layer, wherein the functional bumps and the at least one dummy bump extend through the first and second bonding layers.
However, Jun is a pertinent art that teaches a second bonding layer (Fig. 13, ILa, ¶ [0087]), disposed between the first bonding layer (Fig. 13, ILb, ¶ [0087]) and the second device die (Fig. 13, 300, ¶ [0087]) and bonded to the first bonding layer (Fig. 13, ¶ [0087]), wherein the functional bumps and the at least one dummy bump extend through the first and second bonding layers (Fig. 13, ¶ [0087] teaches that upper/lower pads CPb, CPa, TPb, and TPa extend through ILb and Ila. Therefore, Kim modified by Jun’s dummy structures and functional structures that include upper/lower pads would extend through Kim modified by Jun’s bonding layers).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim modified by Lee’s underfill layer to instead be a multilayered insulating layer according to the teaching of Jun (Fig. 12) in order to provide increased insulation to Kim’s components during processing.
Regarding claim 13, Kim modified by Lee modified by Jun teaches the semiconductor package according to claim 12, and Jun teaches that sidewalls of the first bonding layer (Figs. 12 & 13, IL + ILb, ¶ [0087]) are substantially coplanar with sidewalls of the first device die (Figs. 12 & 13, 400, ¶ [0087]).
Regarding claim 14, Kim modified by Lee modified by Jun teaches the semiconductor package according to claim 12, and Kim modified by Lee modified by Jun teaches a redistribution structure (Kim Figs. 6H & 12, RPL(D) + RPL(S) + IL1 + IL2, ¶ [0054] teaches redistribution patterns connected to dummy structures DST and signal structures RST) lying in between the second bonding layer (Jun Fig. 13, ILa, ¶ [0087]) and the second device die (Kim Fig. 12,CH2, ¶ [0094]. Kim’s redistribution pattern is underneath underfill UF and above device die CH2. Jun’s second bonding layer would correspond to the bottom half of Kim’s underfill UF. Therefore, Kim modified by Jun would fulfill this limitation), wherein the second bonding layer lines along the redistribution structure (Kim’s redistribution pattern is underneath underfill UF and above device die CH2. Jun’s second bonding layer would correspond to the bottom half of Kim’s underfill UF. Therefore, Kim modified by Jun would fulfill this limitation), and has sidewalls substantially coplanar with sidewalls of the redistribution structure (In Jun Fig. 13, Jun’s second bonding layer has sidewalls substantially coplanar with chip 300. In Kim Fig. 12, Kim’s redistribution insulating layers IL1 and IL2 underneath dummy structures DST and structures RST have substantially coplanar sidewalls with Kim’s device die CH2. Therefore, Kim modified by Jun would fulfill this limitation).
Regarding claim 15, Kim modified by Lee modified by Jun teaches the semiconductor package according to claim 14, and Kim teaches that the first seal ring (Fig. 6H, DST, ¶ [0044], [0069] & [0094]) further comprises dummy conductive pads (Fig. 6H, RPL(D), ¶ [0054]) formed in the redistribution structure (Kim Figs. 6H & 12, RPL(D) + RPL(S) + IL1 + IL2, ¶ [0054] teaches redistribution patterns connected to dummy structures DST and signal structures RST) and in contact with the dummy bumps (Fig. 6H, DST, ¶ [0044], [0069] & [0094]).
Regarding claim 16, Kim modified by Lee modified b Jun teaches the semiconductor package according to claim 12, and Jun teaches that the second bonding layer (Fig. 13, ILa, ¶ [0087]) extends along a side of the second device die (Figs. 12 & 13, 300, ¶ [0087]) facing toward the first device die (Figs. 12 & 13, 400, ¶ [0087]), and has sidewalls substantially coplanar with sidewalls of the second device die (Fig. 13).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2022/0302087 by Choi et al discloses a semiconductor package.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2025/0079377 by Yun et al discloses a semiconductor package.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813
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