DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "a second electron transit layer" and "a second electron supply layer" in lines 3 and 5 respectively. There is insufficient antecedent basis for this limitation in the claim because prior to "a second electron transit layer" and "a second electron supply layer" there are no antecedent limitations of "a first electron transit layer" and "a first electron supply layer".
Claims 5-8 are also rejected under 112(b) because of their dependency to the rejected claim 4.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu (US 2022/0005939 A1).
With respect to claim 1, Chiu discloses, in Figs1-6H, a nitride semiconductor device, comprising: a depletion mode transistor (100, 300) including a first gate terminal (34), a first source terminal (30), and a first drain terminal (32); and an enhancement mode transistor (200) including a second gate terminal (34), a second source terminal (30), and a second drain terminal (32), wherein the second drain terminal (32) is connected/(at least electrically connected) to the first source terminal (30), the second source terminal (30) is connected/(at least electrically connected) to the first gate terminal (34) (see Par.[0051]-[0052] wherein FIG. 2 shows a HEMT 200. The HEMT 200 shown in FIG. 2 can be an enhanced mode (E-mode) HEMT; see Par.[0060]-[0061] wherein the HEMT 300 shown in FIG. 3 can be a depletion-mode (D-mode) HEMT; the HEMT 300 has a structure similar to that of the HEMT 100 shown in FIG. 1; see Par.[0027]-[0028] wherein the HEMT 100 further includes an electrode 34 in contact with the gate conductor 28; the electrodes 30 and 32 may form the source/drain electrodes of the HEMT 100; see Par.[0143] wherein it should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present), and the depletion mode transistor (100, 300) includes an electron transit layer (20a1) composed of a nitride semiconductor including aluminum in a crystal composition, and an electron supply layer (20a2) formed on the electron transit layer (20a1) and composed of a nitride semiconductor including aluminum having a larger composition than that of the electron transit layer (20a1) (see Par.[0036]-[0038] wherein the layer 20a1 may include, for example, but is not limited to, group III nitride; the layer 20a1 may include a compound Al.sub.yGa.sub.(1−y)N, in which 0≤y≤1; the layer 20a1 may include a compound Al.sub.yGa.sub.(1−y)N, in which 0.1≤y≤0.35; the layer 20a2 may include, for example, but is not limited to, group III nitride; the layer 20a2 may include a compound In.sub.xAl.sub.(1−x)N, in which 0≤x≤1; the layer 20a2 may include a compound In.sub.xAl.sub.(1−x)N, in which 0.1≤x≤0.3; the layer 20a2 may include a compound In.sub.xAl.sub.(1−x)N, in which 0.1≤x≤0.6; it is submitted that semiconductor (e.g.; II-V materials, AlGaN) are highly ordered crystalline composition).
With respect to claim 2, Chiu discloses, in Figs1-6H, the nitride semiconductor device, wherein the electron transit layer (20a1) is formed of AlxGa1-xN, and the electron supply layer (20a2) is formed of AlyGa1-yN, where 0.1 < x < 0.2, 0.25 < y <0.4, and x < y (see Par.[0036]-[0038] wherein the layer 20a1 may include, for example, but is not limited to, group III nitride; the layer 20a1 may include a compound Al.sub.yGa.sub.(1−y)N, in which 0≤y≤1; the layer 20a1 may include a compound Al.sub.yGa.sub.(1−y)N, in which 0.1≤y≤0.35; the layer 20a2 may include, for example, but is not limited to, group III nitride; the layer 20a2 may include a compound In.sub.xAl.sub.(1−x)N, in which 0≤x≤1; the layer 20a2 may include a compound In.sub.xAl.sub.(1−x)N, in which 0.1≤x≤0.3; the layer 20a2 may include a compound In.sub.xAl.sub.(1−x)N, in which 0.1≤x≤0.6).
Claims 1-3, 9-11, 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bisi et al. (US 2023/0299190 A1 hereinafter referred to as “Bisi”).
With respect to claim 1, Bisi discloses, in Figs.2-7, a nitride semiconductor device, comprising: a depletion mode transistor (200) including a first gate terminal (23), a first source terminal (21), and a first drain terminal (22) (see Par.[0031] wherein Referring to FIG. 2, an N-polar depletion-mode III-N device 200 is shown; see Par.[0038] wherein As shown in FIG. 2, the III-N depleting layer 16 can be over the channel layer in the gate region 81 and laterally extending into the drain-side access region 83 between a gate contact 23 and the drain contact 22); and an enhancement mode transistor (600) including a second gate terminal (623), a second source terminal (621), and a second drain terminal (622), wherein the second drain terminal (622) is connected/(at least electrically connected) to the first source terminal (621), the second source terminal is connected/(at least electrically connected) to the first gate terminal (623) (see Par.[0074] wherein FIG. 6 shows a cross-sectional view of an enhancement mode device 600 which is fabricated in an N-polar direction; see Par.[0075] wherein Device 600 includes a gate contact 623 formed in a gate region 681, a drain contact 622, and a source contact 621 all formed on the same side of the device, which is a side opposite the substrate 610), and the depletion mode transistor (200) includes an electron transit layer (15) composed of a nitride semiconductor including aluminum in a crystal composition, and an electron supply layer (16) formed on the electron transit layer (15) and composed of a nitride semiconductor including aluminum having a larger composition than that of the electron transit layer (15) (see Par.[0035]-[0036] wherein a 0.5-5 nm Al.sub.xGa.sub.1-xN interlayer (where x>50%, not shown) can be disposed between the barrier layer 14 and the channel layer 15; the III-N channel layer 15 can be formed of In.sub.yGa.sub.1-yN (0≤y≤1), where y increases (e.g., continuously increases) from the side adjacent the III-N back-barrier layer 14 to the side opposite the III-N back-barrier layer 14; see Par.[0043] wherein the depleting layer 16 can be formed with a thin GaN layer (0.5-5 nm) deposited on top of a thin Al.sub.xGa.sub.1-xN layer (0.5-5 nm, where x can be higher than 50%, x can be high enough such that the valence-band discontinuity between the thin GaN layer 16 and the thin Al.sub.xGa.sub.1-xN layer is larger than the ionization energy of the p-type acceptor); it is submitted that semiconductor (e.g.; II-V materials, AlGaN) are highly ordered crystalline composition).
With respect to claim 2, Bisi discloses, in Figs.2-7, the nitride semiconductor device, wherein the electron transit layer (15) is formed of AlxGa1-xN, and the electron supply layer (16) is formed of AlyGa1-yN, where 0.1 < x < 0.2, 0.25 < y <0.4, and x < y (see Par.[0035]-[0036] wherein a 0.5-5 nm Al.sub.xGa.sub.1-xN interlayer (where x>50%, not shown) can be disposed between the barrier layer 14 and the channel layer 15; the III-N channel layer 15 can be formed of In.sub.yGa.sub.1-yN (0≤y≤1), where y increases (e.g., continuously increases) from the side adjacent the III-N back-barrier layer 14 to the side opposite the III-N back-barrier layer 14; see Par.[0043] wherein the depleting layer 16 can be formed with a thin GaN layer (0.5-5 nm) deposited on top of a thin Al.sub.xGa.sub.1-xN layer (0.5-5 nm, where x can be higher than 50%, x can be high enough such that the valence-band discontinuity between the thin GaN layer 16 and the thin Al.sub.xGa.sub.1-xN layer is larger than the ionization energy of the p-type acceptor)).
With respect to claim 3, Bisi discloses, in Figs.2-7, the nitride semiconductor device, wherein the depletion mode transistor (200) further includes a nitride semiconductor layer (17) formed on the electron supply layer (16) and including a donor impurity (see Par.[0046] wherein III-N contact layer 17 can be used, for example a n-type GaN layer, which is at least formed over the III-N depleting layer 16 in the gate region 81 of device 200 between the gate 23 and the III-N depleting layer 16; The III-N contact layer 17 can be doped with donors, for example silicon).
With respect to claim 9, Bisi discloses, in Figs.2-7, the nitride semiconductor device, wherein the enhancement mode transistor is a silicon MOSFET (see Par.[0035] wherein depletion-mode device can be useful when used in cascode configuration with a low-voltage enhancement-mode FET, preventing the enhancement-mode FET from entering avalanche-mode during the off-state, or from being biased outside the Safe-Operating Area, therefore undergoing thermal runaway during short-circuit events. In addition, a 0.5-5 nm Al.sub.xGa.sub.1-xN interlayer (where x>50%, not shown) can be disposed between the barrier layer 14 and the channel layer 15).
With respect to claim 10, Bisi discloses, in Figs.2-7, the nitride semiconductor device, wherein each of the depletion mode transistor and the enhancement mode transistor further includes a Si substrate (see Par.[0031] wherein Referring to FIG. 2, an N-polar depletion-mode III-N device 200 is shown. The III-N device 200 includes a III-N buffer layer 11, for example GaN or AlGaN, grown on a suitable substrate 10, which can for example be silicon (Si), silicon carbide (SiC), sapphire, AlN, or GaN).
With respect to claim 11, Bisi discloses, in Figs.2-7, the nitride semiconductor device, wherein the depletion mode transistor further includes a semiconductor substrate including Al, and the enhancement mode transistor further includes a Si substrate (see Par.[0035] wherein depletion-mode device can be useful when used in cascode configuration with a low-voltage enhancement-mode FET, preventing the enhancement-mode FET from entering avalanche-mode during the off-state, or from being biased outside the Safe-Operating Area, therefore undergoing thermal runaway during short-circuit events. In addition, a 0.5-5 nm Al.sub.xGa.sub.1-xN interlayer (where x>50%, not shown) can be disposed between the barrier layer 14 and the channel layer 15; see Par.[0031] wherein Referring to FIG. 2, an N-polar depletion-mode III-N device 200 is shown. The III-N device 200 includes a III-N buffer layer 11, for example GaN or AlGaN, grown on a suitable substrate 10, which can for example be silicon (Si), silicon carbide (SiC), sapphire, AlN, or GaN).
With respect to claim 13, Bisi discloses, in Figs.2-7, The nitride semiconductor device according to claim 1, wherein a drain-source voltage of the enhancement mode transistor has a maximum rating that is greater than or equal to 30 V (see Par.[0041] wherein The depleting layer 16 can be designed so that it becomes substantially fully ionized (fully depleted) when the gate voltage relative to the source (V.sub.GS) is sufficiently negative below a minimum value (for example, −5V, −10V, or −20V) that can be smaller, similar, or greater than the threshold voltage of the device. Additionally, the depleting layer 16 can become partially or substantially fully ionized (depleted) in the drain-side access region 83 when the gate is biased ON (above the threshold voltage of the device, for example at 0V) and the drain voltage exceeds a second minimum voltage (such as 10V, 20V, 30V, 100V, etc.)), and a drain-source voltage of the depletion mode transistor has a maximum rating that is greater than or equal to 500 V (see Par.[0077] wherein he separation 628 can influence the maximum rated blocking voltage of the device. For example, for a device with a maximum blocking voltage of 650V, the separation 628 can be between 5 μm and 15 μm. For a device with a maximum blocking voltage of 1200 V).
Claims 1-2, 10-12, 14, 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2014/0015591 A1 hereinafter referred to as “Chen”).
With respect to claim 1, Chen discloses, in Figs.1-22, a nitride semiconductor device, comprising: a depletion mode transistor (300) including a first gate terminal (318), a first source terminal (316), and a first drain terminal (320) (see Par.[0054] wherein a depletion-mode high electron mobility transistor (D-HEMT) semiconductor device 300; see Par.[0057] wherein Drain electrode 316, gate electrode 318, and source electrode 320 are formed on the primary surface 324 of semiconductor barrier layer 312); and an enhancement mode transistor (400) including a second gate terminal (318’), a second source terminal (316’), and a second drain terminal (320’), wherein the second drain terminal is connected to the first source terminal, the second source terminal is connected to the first gate terminal (see Par.[0058] wherein an enhancement-mode high electron mobility transistor (E-HEMT) semiconductor device 400; see Par.[0063] wherein Drain Ohmic contacts 316 and 316', source Ohmic contacts 320 and 320', along with the gate electrodes 318 and 318', are formed on the primary surface 324 of semiconductor barrier layer 312), and the depletion mode transistor (300) includes an electron transit layer (314) composed of a nitride semiconductor including aluminum in a crystal composition, and an electron supply layer (312) formed on the electron transit layer and composed of a nitride semiconductor including aluminum having a larger composition than that of the electron transit layer (see Par.[0055] wherein A nitride semiconductor barrier layer 312, such as, for example, Al.sub.XGa.sub.1-XN (0<X≤1), is formed on the semiconductor layer 306; see Par.[0061] wherein A nitride semiconductor barrier layer 314, such as Al.sub.XGa.sub.1-XN (0<X≤1), is formed on the semiconductor layer 306; as such there is a possible of choices such that the electron transit layer is formed of AlxGa1-xN, and the electron supply layer is formed of AlyGa1-yN, where 0.1 < x < 0.2, 0.25 < y <0.4, and x < y).
With respect to claim 2, Chen discloses, in Figs.1-22, the nitride semiconductor device, wherein the electron transit layer is formed of AlxGa1-xN, and the electron supply layer is formed of AlyGa1-yN, where 0.1 < x < 0.2, 0.25 < y <0.4, and x < y (see Par.[0055] wherein A nitride semiconductor barrier layer 312, such as, for example, Al.sub.XGa.sub.1-XN (0<X≤1), is formed on the semiconductor layer 306; see Par.[0061] wherein A nitride semiconductor barrier layer 314, such as Al.sub.XGa.sub.1-XN (0<X≤1), is formed on the semiconductor layer 306; as such there is a possible of choices such that the electron transit layer is formed of AlxGa1-xN, and the electron supply layer is formed of AlyGa1-yN, where 0.1 < x < 0.2, 0.25 < y <0.4, and x < y).
With respect to claim 10, Chen discloses, in Figs.1-22, the nitride semiconductor device, wherein each of the depletion mode transistor and the enhancement mode transistor further includes a Si substrate (see Par.[0055] wherein The device 300 includes a nitride material buffer layer 304 that is formed on a substrate layer 302. The substrate layer 302 can be made, for example, of Si, SiC, Sapphire or GaN).
With respect to claim 11, Chen discloses, in Figs.1-22, the nitride semiconductor device, wherein the depletion mode transistor further includes a semiconductor substrate including Al, and the enhancement mode transistor further includes a Si substrate (see Par.[0055] wherein A nitride semiconductor barrier layer 312, such as, for example, Al.sub.XGa.sub.1-XN (0<X≤1), is formed on the semiconductor layer 306; see Par.[0061] wherein A nitride semiconductor barrier layer 314, such as Al.sub.XGa.sub.1-XN (0<X≤1), is formed on the semiconductor layer 306; as such there is a possible of choices such that the electron transit layer is formed of AlxGa1-xN, and the electron supply layer is formed of AlyGa1-yN, where 0.1 < x < 0.2, 0.25 < y <0.4, and x < y; see Par.[0055] wherein The device 300 includes a nitride material buffer layer 304 that is formed on a substrate layer 302. The substrate layer 302 can be made, for example, of Si, SiC, Sapphire or GaN).
With respect to claim 12, Chen discloses, in Figs.1-22, the nitride semiconductor device, wherein a drain-source voltage of the depletion mode transistor has a maximum rating that is greater than that of the enhancement mode transistor (see Par.[0106] wherein D-HEMT 2102 effectively absorbs the excess (i.e.; greater value) voltage of V.sub.In-S, and V.sub.GS is clipped to a safe maximum operating voltage at 2.45V at gate terminal 104g of the E-HEMT 400).
With respect to claim 14, Chen discloses, in Figs.1-22, the nitride semiconductor device, wherein the depletion mode transistor has an on-resistance that is greater than that of the enhancement mode transistor (see Par.[0098]-[0103] wherein both the gate-protected E-HEMT and the conventional unprotected E-HEMT show the same threshold voltage V.sub.TH as +0.7V. The conventional unprotected E-HEMT has a saturation drain current I.sub.D of typically around 310 mA/mm when V.sub.GS is 2.45V. With gate-protection, the integrated device exhibits an I.sub.D close to the conventional counterpart when input bias V.sub.In-S is below 1.5V. When V.sub.In-S is above 2.5V, I.sub.D starts to saturate and remains at 310 mA/mm when V.sub.In-S continues to increase. In the output characteristics, the gate-protected E-HEMT shows a specific on-resistance (R.sub.ON,SP) of 1.5 m.OMEGA.-cm.sup.2 (including the effective active region of the bootstrapped D-HEMT), which is close to the conventional unprotected E-HEMT (1.24 m.OMEGA.-cm.sup.2); gate-protected E-HEMT was also undergone an ON-state electrical stress test, as shown in FIG. 19. The input bias V.sub.In-S was driven by a 10V constant input and V.sub.DS was biased at 0.85V, such that the drain current I.sub.D was kept at an ON-state current of .about.110 mA/mm during the stress. The bootstrapped D-HEMT effectively absorbs the extra gate overdrive).
With respect to claim 16, Chen discloses, in Figs.1-22, the nitride semiconductor device, wherein a drain-source voltage of the enhancement mode transistor has a maximum rating that is less than or equal to 100 V (see Par.[0106] wherein D-HEMT 2102 effectively absorbs the excess (i.e.; greater value) voltage of V.sub.In-S, and V.sub.GS is clipped to a safe maximum operating voltage at 2.45V at gate terminal 104g of the E-HEMT 400).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen.
With respect to claim 15, Chen discloses, in Figs.1-22, the nitride semiconductor device, wherein the depletion mode transistor has an on-resistance that is more greater than that of the enhancement mode transistor (see Par.[0098]-[0103] wherein both the gate-protected E-HEMT and the conventional unprotected E-HEMT show the same threshold voltage V.sub.TH as +0.7V. The conventional unprotected E-HEMT has a saturation drain current I.sub.D of typically around 310 mA/mm when V.sub.GS is 2.45V. With gate-protection, the integrated device exhibits an I.sub.D close to the conventional counterpart when input bias V.sub.In-S is below 1.5V. When V.sub.In-S is above 2.5V, I.sub.D starts to saturate and remains at 310 mA/mm when V.sub.In-S continues to increase. In the output characteristics, the gate-protected E-HEMT shows a specific on-resistance (R.sub.ON,SP) of 1.5 m.OMEGA.-cm.sup.2 (including the effective active region of the bootstrapped D-HEMT), which is close to the conventional unprotected E-HEMT (1.24 m.OMEGA.-cm.sup.2); gate-protected E-HEMT was also undergone an ON-state electrical stress test, as shown in FIG. 19. The input bias V.sub.In-S was driven by a 10V constant input and V.sub.DS was biased at 0.85V, such that the drain current I.sub.D was kept at an ON-state current of .about.110 mA/mm during the stress. The bootstrapped D-HEMT effectively absorbs the extra gate overdrive).
Even though Chen does not disclose the depletion mode transistor has an on-resistance that is more than ten times greater than that of the enhancement mode transistor, the said range is predictable by simple engineering optimization motivated by a design choice, such as, optimizing d-mode e-mode transistor configuration for better stability, higher efficiency, and higher saturation current. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818