DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20200373301) in view of Lo et al. (US 20180175171).
Regarding claim 1, Kim discloses that semiconductor device, comprising:
a front-side wiring structure UV & UAC connected to a signal line POR1 (Fig. 3);
a back-side wiring structure below the front-side wiring structure UV & UAC, the back-side wiring structure LAC & LV being connected to a power line LML (Fig. 3); and
gate structures GST between the front-side wiring structure and the back-side wiring structure (Fig. 3).
Kim fails to teach that each of the gate structures including a gate electrode, a first capping film, a second capping film, and a gate spacer, the first capping film being on a bottom surface of the gate electrode, and the second capping film being on a top surface of the gate electrode, wherein the gate spacer directly contacts a sidewall of the gate electrode.
Lo suggests that each of the gate structures including a gate electrode 65, a first capping film 60, a second capping film 80, and a gate spacer 45, the first capping film 60 being on a bottom surface of the gate electrode 65, and the second capping film 80 being on a top surface of the gate electrode, wherein the gate spacer 45 directly contacts a sidewall of the gate electrode 65 (Fig. 14-18).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Kim with each of the gate structures including a gate electrode, a first capping film, a second capping film, and a gate spacer, the first capping film being on a bottom surface of the gate electrode, and the second capping film being on a top surface of the gate electrode, wherein the gate spacer directly contacts a sidewall of the gate electrode as taught by Lo in order to enhance variation of different shape of a gate electrodes and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 2, Kim & Lo disclose that the gate GST structures are spaced apart from each other in a first horizontal direction, a source/drain region SD1 being positioned between the gate structures (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Reclaim 3, Kim & Lo disclose that the source/drain region SD1 includes a top surface facing the front-side wiring structure and a bottom surface facing the back-side wiring structure, the top surface of the source/drain region has a round shape having a width decreasing toward the front-side wiring structure, and the bottom surface of the source/drain region is flat (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Reclaim 4, Kim & Lo disclose that a first insulating layer filling a space between the back-side wiring structure and each of the source/drain region and the gate structures; and a second insulating layer filling a space between the front-side wiring structure and each of the source/drain region and the gate structures (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Reclaim 5, Kim & Lo disclose that the back-side wiring structure includes a back-side contact connected to the source/drain region, and the front-side wiring structure includes a front-side contact and a front-side via connected to the source/drain region (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Reclaim 6, Kim & Lo disclose that each of the back-side contact and the front-side contact has a tapered shape having a width decreasing toward the source/drain region (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Reclaim 7, Kim & Lo disclose that each of the back-side contact and the front-side contact extends between the gate structures and is connected to the source/drain region (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Reclaim 8, Kim & Lo disclose that the first capping film of each of the gate structures covers the bottom surface of the gate electrode, [[and]] the second capping film of each of the gate structures covers the top and bottom surface[[s]] of the gate electrode, and the gate spacer of each of the gate structures covers a sidewall of the first capping film[[,]] and a sidewall of the second capping film, and a sidewall of the gate electrode (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Reclaim 9, Kim & Lo disclose that a thickness of the first capping film in a vertical direction is greater than or equal to a thickness of the second capping film in the vertical direction (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Reclaim , Kim & Lo disclose that one of the gate structures does not include the second capping film, and a top surface of the gate electrode of the one of the gate structures is in contact with a gate contact (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Regarding claim 11, Kim & Lo disclose that a semiconductor device, comprising:
a front-side wiring structure UV & UAC connected to a signal line POR1;
a back-side wiring structure LV & LAC below the front-side wiring structure, the back-side wiring structure LV & LAC being connected to a power line LNL; and
an electronic element GSY between the front-side wiring structure and the back-side wiring structure, the electronic element including gate structures separated from each other in a first horizontal direction and a source/drain region between the gate structures (Kim Fig. 2A), wherein each of the gate structures includes a gate electrode, a capping film, and a gate spacer, and wherein the capping film includes a first capping film and a second capping film, the first capping film being on a bottom surface of the gate electrode, and the second capping film being on a top surface of the gate electrode, wherein the gate spacer directly contacts a sidewall of the gate electrode (Lo, Fig 14-18).
Reclaim 12, Kim & Lo disclose that a first insulating layer filling 114 or 112 a space between the back-side wiring structure LV & LAC and the electronic element (Fig. 2A, Kim); and
a second insulating layer 120 or APa filling a space between the front-side wiring structure and the electronic element, the first insulating layer including a same material as a material of the second insulating layer (Fig. 2A, Kim).
Reclaim 13, Kim & Lo disclose that the source/drain region includes a top surface facing the front-side wiring structure and a bottom surface facing the back-side wiring structure, the top surface of the source/drain region is round toward the front-side wiring structure, the bottom surface of the source/drain region is flat, and a vertical level of the top surface of the source/drain region is lower than or equal to a vertical level of the top surface of the gate electrode (Lo Fig. 14-18).
Reclaim 14, Kim & Lo disclose that the back-side wiring structure includes a back-side contact connected to the electronic element, the front-side wiring structure includes a front-side contact and a front-side via, each connected to the electronic element, the back-side contact passes through a bottom surface of the source/drain region, and the front-side contact passes through a top surface of the source/drain region (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Reclaim 15, Kim & Lo disclose that the front-side contact is connected to the signal line of the front-side wiring structure through the front-side via, and the back-side wiring structure is connected to the signal line (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Reclaim 16, Kim & Lo disclose that the gate spacer is between the gate electrode and the source/drain region and conformally covers a sidewall of the capping film and a sidewall of the gate electrode (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Regarding claim 17, Kim & Lo disclose that a semiconductor device, comprising:
a front-side wiring structure UAC & UV connected to a signal line POR1 (Fig. 2A, Kim);
a back-side wiring structure LAC & LV below the front-side wiring structure UAC & UV, the back-side wiring structure LAC & LV being connected to a power line LML;
an electronic element GST between the front-side wiring structure and the back-side wiring structure, the electronic element including gate structures separated from each other in a first horizontal direction and a source/drain region between the gate structures;
a first insulating layer 116 or 114 filling a space between the back-side wiring structure and the electronic element GST; and
a second insulating layer AP1 or 120 filling a space between the front-side wiring structure UV or UAC and the electronic element, wherein: the source/drain region SD1 includes a top surface facing the front-side wiring structure and a bottom surface facing the back-side wiring structure, the top surface of the source/drain region is round toward the front-side wiring structure, the bottom surface of the source/drain region is flat (Fig. 2A, Kim), and each of the gate structures includes a gate electrode 65, a capping film 60 , and a gate spacer 95 , the capping film includes a first capping film 60 and a second capping film 80, the first capping film 60 being on a bottom surface of the gate electrode, and the second capping film 80 being on a top surface of the gate electrode, and the gate spacer 95 covers directly contacts a sidewall of each of the gate electrode 65, the first capping film 60, and the second capping film 65 (Lo Fig. 14-18).
Reclaim 18, Kim & Lo disclose that the back-side wiring structure includes a back-side contact connected to the electronic element, the front-side wiring structure includes a front-side contact and a front-side via each connected to the electronic element, a vertical level of the top surface of the source/drain region is lower than or equal to a vertical level of the top surface of the gate electrode, the back-side contact passes through the bottom surface of the source/drain region, and the front-side contact passes through the top surface of the source/drain region (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Reclaim 19, Kim & Lo disclose that each of the back-side contact and the front-side contact has a tapered shape having a width decreasing toward the electronic element and extends between the plurality of gate structures (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Reclaim 20, Kim & Lo disclose that the first capping film includes a same material as a material of the second capping film, and a thickness of the first capping film in a vertical direction is greater than or equal to a thickness of the second capping film in the vertical direction (Kim’s Fig. 2A in view of Lo’s Fig. 14-18).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SU C KIM/Primary Examiner, Art Unit 2899
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