DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 7-9, 11-12, & 14-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20200373301).
Regarding claim 1, Kim discloses that a semiconductor device, comprising:
a front-side wiring structure LV connected to a signal line LML (Fig. 3);
a back-side wiring structure UAC below the front-side wiring structure UAC, the back-side wiring structure UAC being connected to a power line PoR1; and
gate structures GST between the front-side wiring structure LV and the back-side wiring structure UAC, each of the gate structures including a gate electrode GE, a first capping film GI, a second capping film GP, and a gate spacer GS, the first capping film being GI on a bottom surface of the gate electrode Ge, and the second capping film Gp being on a top surface of the gate electrode GE (Fig. 3).
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Reclaim 2, Kim discloses that the gate structures are spaced apart from each other in a first horizontal direction, a source/drain region being positioned between the gate structures (Fig. 1 & 3).
Reclaim 4, Kim discloses that a first insulating layer filling 122 a space between the back-side wiring structure UAC and each of the source/drain region SD1 and the gate structures GST (Fig. 3); and a second insulating layer filling 112 a space between the front-side wiring structure LV and each of the source/drain region SD1 and the gate structures GST (Fig. 3).
Reclaim 5, Kim discloses that the back-side wiring structure includes a back-side contact UAC connected to the source/drain region SD1, and the front-side wiring structure LV includes a front-side contact LAC and a front-side via LV connected to the source/drain region SD1 (Fig. 3).
Reclaim 7, Kim discloses that each of the back-side contact UAC and the front-side contact LAC extends between the gate structures and is connected to the source/drain region (Fig. 3).
Reclaim 8 , Kim discloses that the first capping film GP and the second capping film GI of each of the gate structures covers the top and bottom surfaces of the gate electrode GE, and the gate spacer GS of each of the gate structures covers a sidewall of the first capping film GP & GI, a sidewall of the second capping film, and a sidewall of the gate electrode GE (Fig. 3).
Reclaim 9, Kim discloses that a thickness of the first capping film GP in a vertical direction is greater than or equal to a thickness of the second capping film GI in the vertical direction (Fig. 3).
Regarding claim 11, Kim discloses that a semiconductor device, comprising:
a front-side wiring structure LAC & LV connected to a signal line LML (Fig. 3);
a back-side wiring structure below the front-side wiring structure, the back-side wiring structure UAC & UA being connected to a power line POR1; and
an electronic element GE between the front-side wiring structure and the back-side wiring structure, the electronic element including gate structures separated from each other in a first horizontal direction and a source/drain region between the gate structures (Fig. 1), wherein each of the gate structures includes a gate electrode GE, a capping film GP & GI, and a gate spacer GS, and wherein the capping film includes a first capping film GI and a second capping film GP, the first capping film being GI on a bottom surface of the gate electrode GE, and the second capping film GP being on a top surface of the gate electrode GE (Fig. 3).
Reclaim 12, Kim discloses that a first insulating layer 122 or 120 filling a space between the back-side wiring structure UV and the electronic element GE; and a second insulating layer filling 112 or 114 a space between the front-side wiring structure LV and the electronic element Ge, the first insulating layer including a same material as a material of the second insulating layer (Fig. 3, para 0032 & para. 0027).
Reclaim 14, Kim discloses that the back-side wiring structure includes a back-side contact UAC & UV connected to the electronic element GE (electrically connected), the front-side wiring structure LAC & LV includes a front-side contact and a front-side via, each connected to the electronic element, the back-side contact passes through a bottom surface of the source/drain region SD1, and the front-side contact LAC passes through a top surface of the source/drain region (Fig. 3).
Reclaim 15, Kim discloses that the front-side contact is connected to the signal line of the front-side wiring structure through the front-side via LV, and the back-side wiring structure is connected to the signal line POR1 (Fig. 3).
Reclaim 16, Kim discloses that gate spacer GS is between the gate electrode GE and the source/drain region SD1 and conformally covers a sidewall of the capping film GP & GI and a sidewall of the gate electrode GE (Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 6, 13, & 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20200373301) in view of Huang et al. (US 20220352326).
Reclaims 3 & 13 , Kim discloses that the source/drain region SD1 includes a top surface facing the front-side wiring structure LV and a bottom surface facing the back-side wiring structure UAC.
Kim fails to specify that the top surface of the source/drain region has a round shape having a width decreasing toward the front-side wiring structure, and the bottom surface of the source/drain region is flat.
However, Huang suggests that the top surface of the source/drain 232D region has a round shape having a width decreasing toward the front-side wiring structure, and the bottom surface of the source/drain region is flat (Fig. 21).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Kim with the top surface of the source/drain region has a round shape having a width decreasing toward the front-side wiring structure, and the bottom surface of the source/drain region is flat as taught by Huang in order to enhance variation of source/drain shapes and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Regarding claim 17, Kim & Huang disclose that a semiconductor device, comprising:
a front-side wiring structure LAC & LV connected to a signal line LML;
a back-side wiring structure UAC & UA below the front-side wiring structure, the back-side wiring structure UAC & UA being connected to a power line POR1;
an electronic element GE between the front-side wiring structure and the back-side wiring structure, the electronic element including gate structures GE separated from each other in a first horizontal direction and a source/drain region between the gate structures (Fig. 1);
a first insulating layer filling 122 or 120 a space between the back-side wiring structure UAC & UV and the electronic element GE and a second insulating layer 112 or 114 filling a space between the front-side wiring structure LV LAC and the electronic element GE, wherein: the source/drain region SD1 includes a top surface facing the front-side wiring structure and a bottom surface facing the back-side wiring structure, the top surface of the source/drain region 232D is round toward the front-side wiring structure 228, the bottom surface of the source/drain region is flat (Huang Fig. 21), and each of the gate structures GST includes a gate electrode GE, a capping film GI & GP, and a gate spacer GS, the capping film includes a first capping film GI and a second capping film GP, the first capping film GI being on a bottom surface of the gate electrode GE, and the second capping film GP being on a top surface of the gate electrode GE, and the gate spacer GS covers a sidewall of each of the gate electrode, the first capping film GI, and the second capping film GP(Fig. 3, Kim).
Reclaim 18, Kim & Huang disclose that the back-side wiring structure includes a back-side contact UAC connected to the electronic element GE, the front-side wiring structure includes a front-side contact LAC and a front-side via LV each connected to the electronic element GE, a vertical level of the top surface of the source/drain region SD1 is lower than or equal to a vertical level of the top surface of the gate electrode GE, the back-side contact passes through the bottom surface of the source/drain region, and the front-side contact passes through the top surface of the source/drain region (Fig. 3, Kim).
Reclaim 19, Kim & Huang disclose that each of the back-side contact 248 and the front-side contact has a tapered shape having a width decreasing toward the electronic element and extends between the plurality of gate structures (Huang’s Fig. 21, can be a taped shape, MPEP 2144.04 shape).
Reclaim 20, Kim & Huang disclose that the first capping film Gi includes a same material as a material of the second capping film GP (para. 0026-0027), and a thickness of the first capping film in a vertical direction is greater than or equal to a thickness of the second capping film in the vertical direction (Fig. 3, Kim).
Reclaim 6, Kim & Huang disclose that each of the back-side contact 248 and the front-side contact 248 has a tapered shape having a width decreasing toward the source/drain region (Huang suggests that contact can be a taped shape and decrease a width toward a source/drain).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20200373301) in view of Goktepeli (US 9780210 ).
Reclaim 10 , Kim fails to teach that one of the gate structures does not include the second capping film, and a top surface of the gate electrode of the one of the gate structures is in contact with a gate contact.
However, Goktepeli suggests that a gate structures does not include the second capping film, and a top surface of the gate electrode of the one of the gate structures is in contact with a gate contact (Fig. 7A).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Kim with a gate structures does not include the second capping film, and a top surface of the gate electrode of the one of the gate structures is in contact with a gate contact as taught by Goktepeli in order to enhance complexity of semiconductor device and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
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/SU C KIM/Primary Examiner, Art Unit 2899