DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 is objected to because of the following informalities:
Claim 11, Line 3: “a integrated heat spreader” should be amended to recite “an integrated heat spreader”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 8 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the group consisting of" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claims 8 and 14 recite the limitation "the group consisting of" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-11, 13-17 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kang (US 20240321681 A1).
As to Claim 1, Kang discloses:
A system (semiconductor package 10; see Figs. 1-3) comprising:
a semiconductor die (semiconductor device 100);
a first micro vapor chamber (at least one first vapor channel 733) coupled with a first region of the semiconductor die 100 (see highlighted first vapor chamber in Fig. below, coupled with a region of 100); and
a second micro vapor chamber (at least another first vapor channel 733) coupled with a second region of the semiconductor die 100 (see Fig. below, second highlighted vapor chamber coupled with another region of 100).
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As to Claim 2, Kang discloses:
wherein the semiconductor die 100 comprises a silicon chip (Par. 0036 “The first semiconductor device 100 may be configured to include a single slice of semiconductor material, e.g., from a semiconductor wafer, and the single slice may include the first semiconductor substrate 101”; Par. 0037 “The first semiconductor substrate 101 may be formed of or may include, for example, a silicon (Si) wafer including crystalline Si, polycrystalline Si, or amorphous Si”).
As to Claim 3 (as best understood), Kang discloses:
wherein the semiconductor die comprises a processing element selected from a group consisting of a central processing unit (CPU), a graphics processing unit (GPU), a configurable processing unit, and an integrated circuit (Par. 0031 “the first semiconductor device 100 may be implemented as a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an application processor, a system-on-chip, etc.”).
As to Claim 5, Kang discloses:
wherein the first and second micro vapor chambers (highlighted in attached Fig. in rejection of claim 1 above) are disposed within an integrated heat spreader (heat dissipation structure 700) overlying the semiconductor die 100 (733 are disposed within heat dissipation structure 700, overlaying 100).
As to Claim 6, Kang discloses:
wherein the first and second micro vapor chambers (highlighted in attached Fig. in rejection of claim 1 above) each directly overlie a respective region of the semiconductor die 100 (each highlighted first and second 733 overlie a respective region of 100).
As to Claim 7, Kang discloses:
wherein the first and second micro vapor chambers (highlighted in attached Fig. in rejection of claim 1 above) are independently configured to remove heat from respective regions of the semiconductor die 100 (each chamber 733 independently removes/dissipated heat from 100; Par. 0069 “the heat dissipation structure 700 includes the plurality of first vapor channels 733 radially diffused around the heat source therein, the uniformity of vapor diffusion in the heat dissipation structure 700 may be improved”).
As to Claim 8 (as best understood), Kang discloses:
wherein the first and second micro vapor chambers each comprise a fluid independently selected from a group consisting of water and an alcohol (Par. 0054 “The working fluid may be or include, for example, water, ethylene glycol, silicone oil, mineral oil, liquid Teflon, or a mixture thereof”).
As to Claim 9, Kang discloses:
wherein the first and second micro vapor chambers (highlighted in attached Fig. in rejection of claim 1 above) each have a maximum lateral dimension of less than approximately 10 mm (Par. 0062 “for each first vapor channel 733, the minimum width may be between about 0.5 mm and 3.5 mm, and the maximum width may be greater than the minimum width and be between about 1.5 mm and 10 mm”).
As to Claim 10, Kang discloses:
further comprising a third micro vapor chamber (highlighted in Fig. below) coupled with a third region of the semiconductor die (highlighted third chamber coupled with a third region of 100).
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As to Claim 11, Kang discloses:
A system (semiconductor package 10; see Figs. 1-3) comprising:
a semiconductor die (semiconductor device 100); and
an integrated heat spreader 700 overlying the semiconductor die 100 (Par. 0053 “The heat dissipation structure 700 may be arranged over the first and second semiconductor devices 100 and 200, and may be thermally coupled to the first and second semiconductor devices 100 and 200”), wherein the integrated heat spreader 700 comprises:
a first micro vapor chamber (at least one first vapor channel 733) adapted to cool a first region of the semiconductor die 100 (see highlighted first vapor chamber in Fig. below, coupled with a region of 100); and
a second micro vapor chamber (at least another first vapor channel 733) adapted to cool a second region of the semiconductor die 100 (see Fig. below, second highlighted vapor chamber coupled with another region of 100).
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As to Claim 13, Kang discloses:
wherein the first and second micro vapor chambers (highlighted in attached Fig. in rejection of claim 11 above) each directly overlie a respective region of the semiconductor die 100 (each highlighted first and second 733 overlie a respective region of 100).
wherein the first and second micro vapor chambers (highlighted in attached Fig. in rejection of claim 1 above) each directly overlie a respective region of the semiconductor die 100 (each highlighted first and second 733 overlie a respective region of 100).
As to Claim 14 (as best understood), Kang discloses:
wherein the first and second micro vapor chambers each comprise a fluid independently selected from a group consisting of water and an alcohol (Par. 0054 “The working fluid may be or include, for example, water, ethylene glycol, silicone oil, mineral oil, liquid Teflon, or a mixture thereof”).
As to Claim 15, Kang discloses:
wherein the first and second micro vapor chambers (highlighted in attached Fig. in rejection of claim 11 above) each have a maximum lateral dimension of less than approximately 10 mm (Par. 0062 “for each first vapor channel 733, the minimum width may be between about 0.5 mm and 3.5 mm, and the maximum width may be greater than the minimum width and be between about 1.5 mm and 10 mm”).
As to Claim 16, Kang discloses:
A method comprising:
contacting a first micro vapor chamber (at least one first vapor channel 733) with a first region of a semiconductor die 100 (see highlighted first vapor chamber in Fig. below, coupled with a region of 100); and
contacting a second micro vapor chamber (at least another first vapor channel 733) with a second region of the semiconductor die 100 (see Fig. below, second highlighted vapor chamber coupled with another region of 100).
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As to Claim 17, Kang discloses:
comprising forming the first and second micro vapor chambers (highlighted in attached Fig. in rejection of claim 16 above) within an integrated heat spreader (heat dissipation structure 700; 733 are disposed within heat dissipation structure 700).
As to Claim 19, Kang discloses:
wherein the first and second micro vapor chambers (highlighted in attached Fig. in rejection of claim 16 above) are independently configured to remove heat from respective regions of the semiconductor die 100 (each chamber 733 independently removes/dissipated heat from 100; Par. 0069 “the heat dissipation structure 700 includes the plurality of first vapor channels 733 radially diffused around the heat source therein, the uniformity of vapor diffusion in the heat dissipation structure 700 may be improved”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 20240321681 A1) as applied to claims 1 and 11 above, and further in view of Nishii (US 20160034368 A1).
As to Claims 4 and 12, Kang does not disclose:
wherein the first region of the semiconductor die comprises a first central processing unit (CPU) core and the second region of the semiconductor die comprises a second central processing unit (CPU) core.
However, Nishii discloses:
wherein the first region of the semiconductor die comprises a first central processing unit (CPU) core (first CPU core 11) and the second region of the semiconductor die comprises a second central processing unit (CPU) core (second CPU core 12; Abs. “The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core 11 and the second CPU core 12 respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result”);
in order to diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result (Abstract).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Kang as further suggested by Nishii e.g., providing:
wherein the first region of the semiconductor die comprises a first central processing unit (CPU) core and the second region of the semiconductor die comprises a second central processing unit (CPU) core;
in order to diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 20240321681 A1) as applied to claim 16 above, and further in view of Huang (US 20120168770 A1).
As to Claim 18, Kang does not disclose:
wherein a power density within at least one of the first and second regions of the semiconductor die ranges from approximately 10 W/cm2 to approximately 500 W/cm2.
However, Huang discloses:
wherein a power density within at least one of the first and second regions of the semiconductor die ranges from approximately 10 W/cm2 to approximately 500 W/cm2 (Par. 0002 “power density of a chip is around 100 W/cm.sup.2, and it is likely to increase even further according to International Technology Roadmap for semiconductor guidelines”);
in order to provide chips capable of large power consumption (Par. 0002).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Kang as further suggested by Huang e.g., providing:
wherein a power density within at least one of the first and second regions of the semiconductor die ranges from approximately 10 W/cm2 to approximately 500 W/cm2;
in order to provide chips capable of large power consumption.
Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
It has also been held that discovering an optimum value of a result-effective variable (e.g., the power density of the die regions for effecting the desired results of operating capabilities) involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 20240321681 A1) as applied to claim 16 above, and further in view of Zuo (US 20020100968 A1).
As to Claim 20, Kang does not disclose:
wherein a heat dissipation rate from the first region of the semiconductor die is less than a heat dissipation rate from the second region of the semiconductor die.
However, Zuo discloses:
wherein a heat dissipation rate from the first region of the semiconductor die (hot-spot region of 9 below recess 48) is less than a heat dissipation rate from the second region of the semiconductor die (lower temperature region of 9; Par. 0032 “the main evaporator region of cover/lid 20 (i.e., recess 48 and thinned wall 55) is advantageously located adjacent to the hot-spots on semiconductor device 9, whereas the condenser region of cover/lid 20 (i.e., the remainder of inner wicking surface 46 or channel 53) is located adjacent relatively lower temperature regions of semiconductor 9”);
in order to effectively spread thermal energy across the entire package so it may be drawn off and dissipated (Par. 0032).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Kang as further suggested by Zuo e.g., providing:
wherein a heat dissipation rate from the first region of the semiconductor die is less than a heat dissipation rate from the second region of the semiconductor die;
in order to effectively spread thermal energy across the entire package so it may be drawn off and dissipated.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin (US 20230386960 A1) discloses multiple heat pipes for cooling semiconductors.
Mikjaniec (US 10591964 B1) discloses multiple vapor chambers for cooling of components.
Chang (US 20200350229 A1) discloses a divided vapor chamber for cooling multiple dies.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW S MUIR whose telephone number is (571)270-1329. The examiner can normally be reached Monday - Friday 8 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jayprakash Gandhi can be reached at 571-272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW SINCLAIR MUIR/ Examiner, Art Unit 2841
/Jayprakash N Gandhi/ Supervisory Patent Examiner, Art Unit 2841
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