DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specification
Amendments to Para [0042 and 0043] of the Specification made in Applicant’s Arguments of 06/23/2026 are acknowledged and accepted by Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Kubis (US 2021/0057606 A1, hereinafter Kubis ‘606) in view of Park et al. (KR 20240109851 A, hereinafter Park ‘851), in view of the following arguments.
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With respect to Claim 1 Kubis discloses a display element (Fig 3, Example 2), comprising:
a three-colored LED light emitting structure (structure of Fig 3, Para [0006] discloses the three LEDs of the structure are LEDs) and comprising:
a first semiconductor layer (n-doped layers as shown in annotated Fig 3 of Kubis ‘606, Para [0039], hereinafter 1stSL);
a first multi-quantum well layer (lowermost MQW as shown in annotated Fig 3 of Kubis ‘606, Para [0038], hereinafter 1stMQW) located on (shown in annotated Fig 3 of Kubis ‘606) the first semiconductor layer (1stSL);
a second semiconductor layer (p-doped layers as shown in annotated Fig 3 of Kubis ‘606, Para [0036], hereinafter 2ndSL) located on (shown in annotated Fig 3 of Kubis ‘606) the first multi-quantum well layer (1stMQW), wherein the first semiconductor layer (1stSL) and the second semiconductor layer (2ndSL) are semiconductors with carriers having opposite electrical polarities (Para [0039] discloses 1stSL as a n-doped semiconductor layer and Para [0036] discloses 2ndSL as a p-doped semiconductor layer);
a second multi-quantum well layer (center MQW as shown in annotated Fig 3 of Kubis ‘606, Para [0038], hereinafter 2ndMQW) located on (shown in annotated Fig 3 of Kubis ‘606) the second semiconductor layer (2ndSL);
a third semiconductor layer (n-doped layer as shown in annotated Fig 3 of Kubis ‘606, Para [0034], hereinafter 3rdSL) located on (shown in annotated Fig 3 of Kubis ‘606) the second multi-quantum well layer (2ndMQW);
a third multi-quantum well layer (uppermost MQW as shown in annotated Fig 3 of Kubis ‘606, Para [0029]), hereinafter 3rdMQW) located on (shown in annotated Fig 3 of Kubis ‘606) the third semiconductor layer (3rdSL); and
a fourth semiconductor layer (p-doped layer as shown in annotated Fig 3 of Kubi ‘606, Para [0028], hereinafter 4thSL) located on (shown in annotated Fig 3 of Kubis ‘606) the third multi-quantum well layer (3rdMQW);
at least one conductive via or conductive pillar extending to and electrically connected to at least one of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer (Para [0044] discloses a contact from top of structure to upper p-metal layer and Para [0015 discloses that the p-metal layer and the p-semiconductor layer form a low Schottky barrier, so there is electrical connection between the contact and the 4thSL, contact hereinafter 1CP);
But Kubis ‘606 fails to expressly disclose a substrate; a first insulation layer located on the fourth semiconductor layer; a first active device layer located on the first insulation layer and comprising at least one transistor; at least one conductive via or conductive pillar extending from the first active device layer and at least one electrode located on the first active device layer.
Nevertheless, in a related endeavor (Fig 6-7 of Park ‘851), Park ‘851 teaches a substrate (201, Fig 7 of Park ‘851, Para [0069] of Park ‘851 translation); a first insulation layer (202, Fig 7 of Park ‘851, Para [0069] of Park ‘851 translation) located on the fourth semiconductor layer (153, Fig 6 of Park ‘851, Para [0057] of Park ‘851 translation); a first active device layer (layer of 203/204/205 with transistor structures of TR1/TR2/TR3 (206/SVL/DVL/CVL), Fig 7 of Park ‘851, Para [0076] of Park ‘851 translation, hereinafter ADL) located on (disclosed in Fig 7 of Park ‘851) the first insulation layer (202) and comprising at least one transistor (TR1, Fig 7 of Park ‘851, Para [0076] of Park ‘851 translation); at least one conductive via or conductive pillar (leftmost CT as shown in Fig 7 of Park ‘851, Para [0076] of Park ‘851 translation) extending from (disclosed in Fig 7 of Park ‘851) the first active device layer (ADL) and at least one electrode (SHL, Fig 7 of Park ‘851, Para [0076] of Park ‘851 translation discloses SHL connected externally) located on (disclosed in Fig 7 of Park ‘851) the first active device layer (ADL).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Park ‘851’s teaching of s a substrate; a first insulation layer located on the fourth semiconductor layer; a first active device layer located on the first insulation layer and comprising at least one transistor; at least one conductive via or conductive pillar extending from the first active device layer and at least one electrode located on the first active device layer into Kubis ‘606’s display element. Kubis ‘606 discloses a stacked LED structure for a display device and Kubis discloses that structure comprises a stack of MQW and n and p doped semiconductor layers with electrical contacts in the structure. Park ‘851 also teaches a stacked LED structure for a display device which consists of MQW and n and p doped semiconductor layers. Park ‘851 further teaches an active layer to control the LED stack over the LED structure and electrical connections from the active layer to the semiconductor layers. The ordinary artisan would have been motivated to modify Kubis ‘606 in the manner set forth above, at least, because, firstly one of ordinary skill in the art would recognize that these devices are constructed on a substrate, secondly the first insulation layer provides dielectric protection from parasitic capacitance between devices, thirdly placing the active layer controlling the LED pixels on top of the LED structure would reduce the footprint of the structure which one of ordinary skill in the art would recognize would lead to an improvement in resolution as the pixels could be closer to each other and fourthly one of ordinary skill in the art would recognize that conductive contacts from the active layer to the semiconductor devices are needed to achieve the well-known advantage of providing control signals from the control transistors to the semiconductor layers of the device and lastly one of ordinary skill in the art would recognize that electrodes are needed on the device to achieve the well-known advantage of providing electrical connection between individual display elements.
As incorporated, the above teachings of Park ‘851 of forming the display element (structure of Fig 3) of Kubis ‘606 on a substrate (201) of Park ;851; a first insulation layer (202) of Park ‘851 located on the fourth semiconductor layer (4thSL) of Kubis ‘606; a first active device layer (ADL) of Park ‘851 located on the first insulation layer (202) of Park ‘851 and comprising at least one transistor (TR1) of Park ‘851; at least one conductive via or conductive pillar (1CP) of Kubis ‘606 extending from the first active device layer (ADL) and at least one electrode (SHL) located on the first active device layer (ADL) are incorporated into the device of Kubis ‘606.
Further, as incorporated, the three-colored LED light emitting structure (structure of Fig 3, Para [0006] discloses the three LEDs of the structure are LEDs) of Kubis ‘606 is located on the substrate (201) of Park ‘851 and a first semiconductor layer (1stSL) of Kubis ‘606 is located on the substrate (201) of Park ‘851.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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