DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Claim(s) 14-15, 17-18 and 20-21 in the reply filed on 06/10/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. DE10 2023 200 039.3, filed on 01/03/2023.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 12/22/2023 and 02/02/2024 is/are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 14-15, 17-18, and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Paul Thorup et al, (hereinafter THORUP), US 20090090966 A1, in view of Oliver Haeberlen et al, (hereinafter HAEBERLEN), US 20160233331 A1.
Regarding Claim 14, THORUP teaches a vertical field-effect transistor structure (Figs. 5E/6A, integrated shielded gate FET, [0015]), comprising:
a semiconductor body (Fig. 5E, N-type silicon substrate (not shown), [0027]) having a surface (annotated Figure 5E), wherein a source zone (Fig. 5E, 522B, source region) located adjacent to the surface (annotated Figure 5E), a channel zone (Fig. 5E, 518, body regions; a vertical channel is formed in each body region, 318/518, [0028]) located on a side (annotated Figure 5E) of the source zone (Fig. 5E, 522, source region) directed away from the surface (annotated Figure 5E), and a drift zone (Fig. 5E, 502) located on a side (annotated Figure 5E) of the channel zone (Fig. 5E, 518, body regions; a vertical channel is formed in each body region, 318/518, [0028]) directed away (annotated Figure 5E) from the source zone (Fig. 5E, 522, source region), are formed in the semiconductor body (Fig. 5E, N-type silicon substrate (not shown), [0027]), and the drift zone (Fig. 5E, 502) has a first doping of a first doping type (Fig. 5E, 502, a doped N-type (N) drift region, 302/502, [0027]);
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multiple first trenches (Fig. 5E, 524, recess dimple region, [0028]) and multiple second trenches (Fig. 5E, 504, trenches, [0027]), wherein one of the second trenches (Fig. 5E, 504, trenches, [0027]) is located between two adjacent (annotated Figure 5E) first trenches (Fig. 5E, 524, recess dimple region, [0028]), and one of the first trenches (Fig. 5E, 524, recess dimple region, [0028]) is located between two adjacent (annotated Figure 5E) second trenches (Fig. 5E, 504, trenches, [0027]) and each of the first (Fig. 5E, 524, recess dimple region, [0028]) and second trenches (Fig. 5E, 504, trenches, [0027]) extends from the surface (annotated Figure 5E) of the semiconductor body (Fig. 5E, N-type silicon substrate (not shown), [0027]) to its trench bottom (annotated Figure 5E) located within the drift zone (Fig. 5E, 502), and wherein the first trenches (Fig. 5E, 524, recess dimple region, [0028]) have at most a first trench depth (annotated Figure 5E, [0028]), and the second trenches (Fig. 5E, 504, trenches, [0027]) have at least a second trench depth (annotated Figure 5E, [0027]), and the second trench depth (annotated Figure 3A, [0027]) is longer (annotated Figure 5E) than the first trench (Fig. 5E, 524, recess dimple region, [0028]) depth (annotated Figure 5E) at least by 50 nm (annotated Figure 5E; the depth of each trench, 504 in range of 0.5-3.0 micrometer, [0036]; 0.5 micrometer = 500 nm);
a shielding region (Fig. 5E, 520, P-type regions, [0053]) adjacent to each of the trench bottoms (annotated Figure 5E) of the first trenches (Fig. 5E, 524, recess dimple region, [0051]), the shielding region (Fig. 5E, 520, P-type regions, [0053]) having a second doping of a second doping type (P-type, [0053]) different from the first doping type (N-type, [0036]) of the drift zone (Fig. 5E, 502, [0036]); and
at least one gate electrode (Fig. 5E, 508) in each of the first (Fig. 5E, 524, recess dimple region, [0051]) and second trenches (Fig. 5E, 504, trenches, [0036]), wherein each of the gate electrodes (Fig. 5E, 508) is electrically insulated at least from an adjacent trench bottom (annotated Figure 5E) and an adjacent trench side wall (annotated Figure 5E) of a relevant trench (Fig. 5E, 504, trenches, [0036]) by at least one insulation dielectric (Fig. 5E, 514, dielectric cap, [0037]); wherein each region of the semiconductor body (Fig. 5E, N-type silicon substrate (not shown), [0027]) that is adjacent to the trench bottoms (annotated Figure 5E) of the second trenches (Fig. 5E, 504, trenches, [0036]) has exclusively the first doping (Fig. 5E, N-type doping) of the drift zone (Fig. 5E, 502, [0036]) and is free from the second doping (Fig. 5E, P-type doping).
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Though THORUP teaches an integrated shielded gate FET, comprising: the trenches, 504 depth is longer than the recess dimple region, 504, THORUP does not explicitly disclose a vertical field-effect transistor structure, comprising: each of the first and second trenches extends from the surface of the semiconductor body to its trench bottom located within the drift zone, and wherein the first trenches have at most a first trench depth, and the second trenches have at least a second trench depth, and the second trench depth is longer than the first trench depth at least by 50 nm.
HAEBERLEN teaches a vertical field-effect transistor structure (Fig. 73, 100, semiconductor device), comprising: each of the first (Fig. 73, 20, second trench) and second trenches (Fig. 73, 10, first trench) extends from the surface of the semiconductor body (annotated Figure 73) to its trench bottom (annotated Figure 73) located within the drift zone (Fig. 73, 40), and wherein the first trenches have at most a first trench depth, and the second trenches have at least a second trench depth (Fig. 73, a vertical depth into which the fir3eld plates, 16 and 26 extend to and further the second gate electrode, 21 extends not as deep into the drift region, 40 as the first gate electrode, 11, [0157]), and the second trench depth is longer than the first trench depth at least by 50 nm (Fig. 73, the first gate electrode, 11 extends about 100 micrometer deeper into the drift region, 40 compared to the second gate electrode, 21, [0157]; 1 micrometer = 1000 nm).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified THORUP to incorporate the teachings of HAEBERLEN, such that a vertical field-effect transistor structure, comprising: each of the first and second trenches extends from the surface of the semiconductor body to its trench bottom located within the drift zone, and wherein the first trenches have at most a first trench depth, and the second trenches have at least a second trench depth, and the second trench depth is longer than the first trench depth at least by 50 nm, so that the charge generation, the risk of charge entrapment in the gate oxide and the risk of latch-up of the MGD during reversed current flow and Avalanche conditions can be reduced (HAEBERLEN, [0157]).
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Regarding Claim 15, THORUP as modified by HAEBERLEN teaches the vertical field-effect transistor structure, according to claim 14.
HAEBERLEN further teaches the vertical field-effect transistor structure (Fig. 73, 100, semiconductor device), wherein a first average dielectric thickness oriented perpendicularly to the surface of the semiconductor body (Fig. 5, vertical thickness, [0087]) is defined for the at least one insulation dielectric covering at least part of an area of all of the trench bottoms of the first trenches (Fig. 5, 22c, vertical thickness of the insulation bottom, 22c below the respective gate electrodes, 21 of the trench, 20, [0087]), and a second average dielectric thickness oriented perpendicularly to the surface of the semiconductor body (Fig. 5, vertical thickness, [0087]) is defined for the at least one insulation dielectric covering at least part of the area of all of the trench bottoms of the second trenches (Fig. 5, 12c, vertical thickness of the insulation bottom, 12c below the respective gate electrodes, 11 of the trench, 10, [0087]), wherein the second average dielectric thickness (Fig. 5, 12c, vertical thickness of the insulation bottom, 12c below the respective gate electrodes, 11 of the trench, 10, [0087]) is greater than the first average dielectric thickness (Fig. 5, 22c, vertical thickness of the insulation bottom, 22c below the respective gate electrodes, 21 of the trench, 20, [0087]) at least by a factor of 1.2 (Fig. 5, typically, the lateral/vertical thickness of the first and second insulating bottom portions, 12c, and 22c is in a range of about 50 nm to about 300 nm, [0087]; For example factor = thickness of 22c/ thickness of 12c = 300 nm / 250 nm = 1.2).
Regarding Claim 17, THORUP as modified by HAEBERLEN teaches the vertical field-effect transistor structure, according to claim 14.
HAEBERLEN further teaches the vertical field-effect transistor structure (Fig. 73, 100, semiconductor device), wherein two of the gate electrodes (Fig. 13, 21, second gate electrode) are located in each first trench of the first trenches (Fig. 13, 20, second trench), wherein the vertical field-effect transistor structure (Fig. 73, 100, semiconductor device) has a metalization (Fig. 13, 60, source metallization) on an upper side of the semiconductor body (annotated Figure 13), and a finger structure (annotated Figure 13) of the metalization (Fig. 13, 60, source metallization) projects (annotated Figure 13) at least into each first trench (Fig. 13, 20, second trench) between the two gate electrodes (Fig. 13, 21, second gate electrode) of the first trench (Fig. 13, 20, second trench), which are electrically insulated from an adjacent finger structure (annotated Figure 13) by the at least one insulation dielectric (Fig. 13, 22, insulating region), and wherein each of the finger structures (annotated Figure 13) projecting into the first trenches (Fig. 13, 20, second trench) extends through the first trench (Fig. 13, 20, second trench) to the adjacent shielding region (Fig. 3, 24, p-type conductive region, [0088]).
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THORUP further teaches a vertical field-effect transistor structure (Figs. 5E/6A, integrated shielded gate FET, [0015]), wherein the vertical field-effect transistor structure (Figs. 5E/6A, integrated shielded gate FET, [0015]) has a metalization (Fig. 3A, 330, interconnect material, [0029]) on an upper side of the semiconductor body (annotated Figure 3A), and a finger structure (annotated Figure 3A) of the metalization (Fig. 3A, 330, interconnect material, [0029]) projects (annotated Figure 3A) at least into each first trench (Fig. 3A, 324, recess dimple region, [0028]) between the two gate electrodes (Fig. 3A, 308) of the first trench (Fig. 3A, 324, recess dimple region, [0028]), which are electrically insulated from an adjacent finger structure (annotated Figure 3A) by the at least one insulation dielectric (Fig. 3A. 314, dielectric caps), and wherein each of the finger structures (annotated Figure 3A) projecting into the first trenches (Fig. 3A, 324, recess dimple region, [0028]) extends through the first trench (Fig. 3A, 324, recess dimple region, [0028]) to the adjacent shielding region (Figs. 3A/5E, 520, P-type regions, [0053]).
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Regarding Claim 18, THORUP as modified by HAEBERLEN teaches the vertical field-effect transistor structure, according to claim 14.
HAEBERLEN further teaches the vertical field-effect transistor structure (Fig. 73, 100, semiconductor device), wherein two of the gate electrodes (Fig. 13, 11, first gate electrode) are located in each second trench of the second trenches (Fig. 13, 10, first trench), wherein a finger structure (annotated Figure 13) of the metalization (Fig. 13, 60, source metallization) projects (annotated Figure 13) at least into each second trench between the two gate electrodes of the second trench (Fig. 13, 10, first trench), which are electrically insulated from the adjacent finger structure (annotated Figure 13) by means the at least one insulation dielectric (Fig. 13, 70, dielectric portions), and wherein each of the finger structures projecting (annotated Figure 13) into the second trenches (Fig. 13, 10, first trench) is electrically insulated from the trench bottom (annotated Figure 13) of the second trench (Fig. 13, 10, first trench) by the at least one insulation dielectric (Fig. 13, 70, dielectric portions).
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THORUP further teaches a vertical field-effect transistor structure (Figs. 5E/6A, integrated shielded gate FET, [0015]), wherein two of the gate electrodes (Fig. 3A, 308) are located in each second trench of the second trenches (Fig. 3A, 304, trenches), wherein a finger structure (annotated Figure 3A) of the metalization (Fig. 3A, 330, interconnect material, [0029]) projects (annotated Figure 3A) at least into each second trench (Fig. 3A, 304, trenches) between the two gate electrodes (Fig. 3A, 308) of the second trench (Fig. 3A, 304, trenches), which are electrically insulated from the adjacent finger structure (annotated Figure 3A) by means the at least one insulation dielectric (Fig. 3A. 314, dielectric caps), and wherein each of the finger structures projecting (annotated Figure 3A) into the second trenches (Fig. 3A, 304, trenches) is electrically insulated from the trench bottom (annotated Figure 3A) of the second trench (Fig. 3A, 304, trenches) by the at least one insulation dielectric (Fig. 3A. 314, dielectric caps).
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Regarding Claim 20, THORUP as modified by HAEBERLEN teaches the vertical field-effect transistor structure, according to claim 14.
THORUP further teaches a vertical field-effect transistor structure (Figs. 5E/6A, integrated shielded gate FET, [0015]), wherein the channel zone (Fig. 5E, 518, body regions; a vertical channel is formed in each body region, 318/518, [0028]) is doped with ions of the same second doping type (Fig. 5E, P-type body regions, 318, [0028]) as the shielding regions (Fig. 5E, 520, P-type regions, [0053]).
Regarding Claim 21, THORUP as modified by HAEBERLEN teaches the vertical field-effect transistor structure, according to claim 14.
THORUP further teaches a vertical field-effect transistor structure (Figs. 5E/6A, integrated shielded gate FET, [0015]), wherein the shielding regions (Fig. 5E, 520, P-type regions, [0053]) have a maximum depth (Fig. 5E, p-type regions, 520 is etched to form dimples terminating in p-type regions, 520 at a depth similar to the depth of dimples, 824 in Fig. 8, [0053]), oriented perpendicularly to the surface (annotated Figure 5E) of the semiconductor body (Fig. 5E, N-type silicon substrate (not shown), [0027]), which is greater than or equal to 50% of a difference between the second trench depth minus the first trench depth (annotated Figure 5E).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
DE 10224201 A1 – Figure 1
STATEMENT OF RELEVANCE – A section of a semiconductor device, an n-type trench MOSFET with breakdown structure partially arranged in the trench or trenches.
US 20090008709 A1 – Figure 3B
STATEMENT OF RELEVANCE – A dual trench MOSFET with the shielded gate structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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