DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicants’ election without traverse of Group I (claims 1-14) in the reply filed on 28 April 2026 is acknowledged. Claims 15 and 16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. The restriction requirement is deemed proper and made final. Applicants are reminded to indicate the withdrawn status of claims 15 and 16 in their next submission of a claim listing.
Response to Amendment
The Office acknowledges receipt on 22 December 2023 of Applicant’s amendments in which the abstract and claims 1-16 are amended.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1, lines 8 and 9, recites “opening opening,” which should read “opening.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 6, recites “the superficial semiconductive layer,” which is indefinite because it lacks a proper antecedent basis. For the purpose of compact prosecution and to better comport with the remainder of the claim, the claim will be interpreted to recite “the semiconductive layer.” Claims 2-14 are rejected due to their dependence from base claim 1.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, lines 23-25 of claim 1 recites the broad recitation “said isolating material extends at least to within the sacrificial layer of the stack,” and the claim also recites “preferably to within the support layer of the stack” which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims. For the purpose compact prosecution, the claim will be interpreted to recite “said isolating material extends at least to within the sacrificial layer of the stack or within the support layer of the stack.” Claims 2-14 are rejected due to their dependence from base claim 1.
Claim 3, lines 8-11, recites “a simultaneous removal of the first and second sacrificial coating layer portions, so as to form a first back gate under the semiconductive device and a second back gate under the second semiconductive device,” which is indefinite because it is unclear how the removal of coating layer portions can form (e.g., create) first and second back gates. The instant application discloses such removal is one of multiple operations performed so that a conductive layer may be formed within a cavity to thereby form first and/or second back gates. But the removal operation itself does not form the back gates. For the purpose of compact prosecution and to better comport with the application, the claim will be interpreted to recite “a simultaneous removal of the first and second sacrificial coating layer portions.”
Claim 4, lines 8-12, recites “a removal of the first sacrificial coating layer portion only, without removal of the second sacrificial coating layer portion, so as to form the back gate only under the semiconductive device, by preserving a sacrificial layer portion under the second semiconductive device,” which is indefinite because it is unclear how the removal of a coating layer portion and/or preserving a sacrificial layer portion under a second semiconductive device can form (e.g., create) a first back gate. The instant application discloses such removal is one of multiple operations performed so that a conductive layer may be formed within a cavity to thereby form a first back gate. But neither the removal operation nor the preservation operation, alone or in combination, forms the back gate. Moreover, the instant application (see e.g., Fig. 13A) discloses that additional features (e.g., 41, 42) other than the first sacrificial coating layer are also removed by the removal. For the purpose of compact prosecution and to better comport with the application, the claim will be interpreted to recite “a removal of the first sacrificial coating layer portion, without removal of the second sacrificial coating layer portion.”
Claim 9, lines 2 and 3, recites “the sacrificial coating layer is chosen with the basis of a first dielectric material, for example, SiN or SiC,” which is indefinite because its meaning is unclear. For the purpose of compact prosecution and to better comport with the application, the claim will be interpreted to recite “the sacrificial coating layer is chosen to be a different material than SiN or SiC.”
Claim 11, lines 3-5, recites “a compatible deposition of a layer made of a second dielectric material on exposed walls of the cavity, for example, by chemical vapour deposition (CVD),” which is indefinite because it is unclear whether the example is intended to limit the scope of the claimed subject matter. For the purpose compact prosecution, the claim will be interpreted to recite “a compatible deposition of a layer made of a second dielectric material on exposed walls of the cavity.” Claim 12 is rejected due to its dependence from intermediate claim 11.
Claim 12, lines 2-5, recites “the layer made of a second dielectric material has a thickness e51, the sacrificial coating layer has a thickness e15, the electrically conductive material has a thickness e5, such that e51<e15/3 and e51<e5/3, and preferably such that e51<e15/4 and e51<e5/4,” which is indefinite because it is unclear whether the preference is intended to limit the scope of the claimed subject matter. For the purpose compact prosecution, the claim will be interpreted to recite “the layer made of a second dielectric material has a thickness e51, the sacrificial coating layer has a thickness e15, the electrically conductive material has a thickness e5, such that e51<e15/3 and e51<e5/3 or such that e51<e15/4 and e51<e5/4.”
Claim 13, lines 2 and 3, recites “the isolating material of the isolation trenches is chosen with the basis of SiO2,” which is indefinite because its meaning is unclear. For the purpose of compact prosecution and to better comport with the application, the claim will be interpreted to recite “the isolating material of the isolation trenches is chosen to be a material of SiO2.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fenouillet-Beranger et al. (US20110108942A1) in view of Henson et al. (US20110147885A1) and Chang et al. (US20040222489A1).
Regarding claim 1, as interpreted in view of the indefiniteness rejection, Fenouillet-Beranger teaches a method for producing a back gate (5) under a semiconductive device (4/4a), said semiconductive device (4/4a) being formed on a semiconductive layer (3) of a stack successively comprising a support layer (1), a sacrificial layer (13) and the semiconductive layer (3) {Figs. 18, 23; [0055, 0058, 0065]}, said method comprising:
a formation of isolation trenches (6, 15) around the semiconductive device (4/4a), said isolation trenches (6, 15) passing through the semiconductive layer (3) and the sacrificial layer (13), and extending to the support layer (1) {Figs. 7-9, 22;[0040, 0041]},
a partial etching of the isolation trenches (6, 15) so as to form an opening (opening in 15) opening onto the sacrificial layer (13) {Figs. 14-16; [0047, 0048]},
a removal of the sacrificial layer (13) selectively at the semiconductive layer (3), at the support layer (1) and at the isolation trenches (6, 15), so as to form a cavity (18) under the semiconductive device (4) {Fig. 16; [0051]}, and
a filling of the cavity (18) with an electrically conductive material (material of 5), so as to form the back gate (5) under the semiconductive device (4/4a) {Fig. 18; [0058]}.
Fenouillet-Beranger does not teach wherein the formation of the isolation trenches comprises:
a first etching configured to form at least one trench pattern having a bottom and flanks,
a formation of a sacrificial coating layer at least on the flanks of the at least one trench pattern, in contact with the sacrificial layer of the stack, and
a filling of the at least one trench pattern with an isolating material, configured such that said isolating material extends at least to within the sacrificial layer or within the support layer of the stack, and
the partial etching of the isolation trenches comprises a removal of the sacrificial coating layer selectively at the isolating material.
In an analogous art, Henson teaches a formation of isolation trenches comprises: a first etching configured to form at least one trench pattern (30) having a bottom and flanks {Fig. 6A; [0053, 0054]}, a formation of a sacrificial coating layer (19) at least on the flanks of the at least one trench pattern (30), in contact with a sacrificial layer (13) of a stack (12, 13, 16) {Fig. 8; [0057]}, and a filling of the at least one trench pattern (30) with an isolating material (20), configured such that said isolating material (20) extends at least to within the sacrificial layer (13) of the stack (12, 13, 16) or within the support layer (12) of the stack (12, 13, 16) {Figs. 11, 12; [0064]}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fenouillet-Beranger’s method based on the teachings of Henson, to achieve the above-identified operations, because applying a known technique (e.g., as taught by Henson) in the same way to enhance another known technique (e.g., as taught by Fenouillet-Beranger) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Moreover, the modification would be obvious for creating a semiconductor-on-insulator (SOI) substrate comprising one or more device regions, each of which comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween. Henson [0011].
Fenouillet-Beranger as modified by Henson does not teach the partial etching of the isolation trenches comprises a removal of the sacrificial coating layer selectively at the isolating material.
In an analogous art, Chang teaches in Figs. (3E, 3F)/(4C, 4D) and paragraphs [0022, 0031] a partial etching of an isolation trench (130) comprises a removal of a sacrificial coating layer (140B/240B) selectively at an isolating material (150B/250B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fenouillet-Beranger’s method as modified by Henson based on the teachings of Chang, to achieve the above-identified operation, because applying a known technique (e.g., as taught by Chang) in the same way to enhance another known technique (e.g., as taught by Fenouillet-Beranger and Henson) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Moreover, the modification would be obvious for: (1) eliminat[ing] … leaking [current] passages around the trench {Chang [0026]} and/or (2) avoiding sneakage current in the STI structure {Chang [0036]}.
Regarding claim 2, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 1, and Fenouillet-Beranger further teaches wherein the semiconductive device is a quantum device {see Examiner’s Note}, and wherein the electrically conductive material (material of 5) is metal {[0057]}.
Examiner’s Note: The limitation whereby “the semiconductive device is a quantum device” is directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, does not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding claim 3, as interpreted in view of the indefiniteness rejection, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 1, and Fenouillet-Beranger further teaches wherein the semiconductive device (4a) is adjacent to a second semiconductive device (4b) separated from the semiconductive device (4a) by an isolation trench (15) having a first flank on the side of the semiconductive device (4a) and a second flank on the side of the second semiconductive device (4b) {Fig. 10; [0043]}.
Fenouillet-Beranger does not teach:
the isolation trench comprising a first sacrificial coating layer portion on the first flank and a second sacrificial coating layer portion on the second flank, and
wherein the partial etching of said isolation trench comprises a simultaneous removal of the first and second sacrificial coating layer portions.
Chang teaches in Figs. 4C and 4D an isolation trench (130) comprising a first sacrificial coating layer portion (portion of 240B subsequently removed from left side of trench to create 240C) on a first flank and a second sacrificial coating layer portion (portion of 240B subsequently removed from right side of trench to create 240C) on a second flank, and wherein a partial etching of an isolation trench (130) comprises a simultaneous removal of the first and second sacrificial coating layer portions. The motivation for this modification is identified with respect to base claim 1.
Regarding claim 4, as interpreted in view of the indefiniteness rejection, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 1, and Fenouillet-Beranger further teaches wherein the semiconductive device (4a) is adjacent to a second semiconductive device (4b) separated from the semiconductive device (4a) by an isolation trench (15) having a first flank on the side of the semiconductive device (4a) and a second flank on the side of the second semiconductive device (4b) {Fig. 10; [0043]}.
Fenouillet-Beranger does not teach:
said isolation trench comprising a first sacrificial coating layer portion on the first flank and a second sacrificial coating layer portion on the second flank, and
wherein the partial etching of said isolation trench comprises a removal of the first sacrificial coating layer portion, without removal of the second sacrificial coating layer portion.
Chang teaches in Figs. 4C and 4D said isolation trench (130) comprising a first sacrificial coating layer portion (portion of 240B subsequently removed from left side of trench to create 240C) on the first flank and a second sacrificial coating layer portion (portion of 240B not subsequently removed from right side of trench to create 240C) on the second flank, and wherein a partial etching of said isolation trench (130) comprises a removal of the first sacrificial coating layer portion (portion of 240B subsequently removed from left side of trench to create 240C), without removal of the second sacrificial coating layer portion (portion of 240B subsequently removed from left side of trench to create 240C). The motivation for this modification is identified with respect to base claim 1.
Regarding claim 5, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 1, but Fenouillet-Beranger does not teach wherein the formation of the sacrificial coating layer is done by compatible deposition on the flanks and the bottom of the at least one trench pattern.
Henson teaches in Fig. 8 and paragraph [0057] a formation of a sacrificial coating layer (19) is done by compatible deposition on the flanks and the bottom of the at least one trench pattern (30). The motivation for this modification is identified with respect to base claim 1.
Regarding claim 6, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 1, but Fenouillet-Beranger does not teach wherein the removal of the sacrificial coating layer is only partial and configured to preserve a portion of the sacrificial coating layer located on the bottom of the at least one trench pattern.
Chang teaches in Figs. 4C and 4D a removal of a sacrificial coating layer (240B) is only partial and configured to preserve a portion (240C) of the sacrificial coating layer (240B) located on the bottom of the least one trench pattern (130). The motivation for this modification is identified with respect to base claim 1.
Regarding claim 7, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 1, but Fenouillet-Beranger does not teach wherein the formation of the sacrificial coating layer comprises a compatible deposition on the flanks and the bottom of the at least one trench pattern, followed by an anisotropic etching configured to remove a portion of the sacrificial coating layer located on the bottom of the at least one trench pattern, such that the sacrificial coating layer only covers the flanks of the at least one trench pattern, before filling the at least one trench pattern with the isolating material.
Chang teaches in Figs. 3B and 3C and paragraph [0020] a formation of a sacrificial coating layer (140A) comprises a compatible deposition on the flanks and the bottom of at least one trench pattern (130), followed by an anisotropic etching configured to remove a portion of the sacrificial coating layer (140A) located on the bottom of the at least one trench pattern (130), such that the sacrificial coating layer (140A) only covers the flanks of the at least one trench pattern (130). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fenouillet-Beranger’s method as modified by Henson based on the teachings of Chang, to achieve the above-identified operation, because applying a known technique (e.g., as taught by Chang) in the same way to enhance another known technique (e.g., as taught by Fenouillet-Beranger and Henson) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Moreover, the modification would be obvious for: (1) eliminat[ing] … leaking [current] passages around the trench {Chang [0026]} and/or (2) avoiding sneakage current in the STI structure {Chang [0036]}.
Fenouillet-Beranger as modified by Chang above does not teach performing the anisotropic etching before filling the at least one trench pattern with an isolating material. However, the combination of teachings identified with respect to claim 1 teaches all of the claimed limitations except for the specific order recited in claim 7. And the selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result. MPEP 2144.04(IV)(C).
Regarding claim 8, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 7, and Fenouillet-Beranger further teaches wherein the removal of the sacrificial coating layer (13) is total {Fig. 16; [0051]}.
Regarding claim 9, as interpreted in view of the indefiniteness rejection, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 1, and Fenouillet-Beranger further teaches wherein the sacrificial coating layer (13) is chosen to be a different material (e.g., SiGe) than SiN or SiC {[0032]}.
Regarding claim 10, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 1, but Fenouillet-Beranger does not teach wherein the formation of the sacrificial coating layer is configured, such that the sacrificial coating layer has a thickness e15 in a direction transverse to the flanks of the at least one trench pattern, and the filling of the at least one trench pattern with the isolating material is configured such that the isolating material has a thickness e16 in said transverse direction, such that e15<e16/3.
Henson teaches in Fig. 12 and paragraph [0070] a formation of a sacrificial coating layer (19/22) is configured, such that the sacrificial coating layer (19/22) has a thickness e15 in a direction (horizontal) transverse to the flanks of at least one trench pattern (30), and the filling of the at least one trench pattern (30) with the isolating material (20) is configured such that the isolating material (20) has a thickness e16 in said transverse direction (horizontal). The motivation for this modification is identified with respect to base claim 1.
Fenouillet-Beranger as modified by Henson does not teach the thicknesses have a ratio of e15<e16/3. However, the instant application does not identify a performance/operational difference achieved by the dimensional limitations. [Where] the dimensional limitations [of the claimed device] d[o] not specify a device which perform[s] and operate[s] any differently from the prior art, a difference between such claimed dimensional limitations and those existing in the prior art is insufficient to render the claimed device non-obvious over the prior art. Gardner v. TEC Systems, Inc., 725 F.2d 1338, 1345, 1349 (Fed. Cir. 1984); see also MPEP 2144.04(IV)(A).
Regarding claim 11, as interpreted in view of the indefiniteness rejection, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 1, and Fenouillet-Beranger further teaches further comprising, after removal of the sacrificial layer (13) and before filling the cavity with an electrically conductive material (5), a compatible deposition of a layer (layer of 11) made of a second dielectric material (11) on exposed walls of the cavity (18) {Fig. 17; [0055]}.
Regarding claim 12, as interpreted in view of the indefiniteness rejection, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 11, and Fenouillet-Beranger further teaches wherein the layer (layer of 11) made of a second dielectric material (11) has a thickness e51 and the electrically conductive material (5) has a thickness e5, such that e51<e5/3 or such that e51<e5/4 {Fig. 18}. “The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
Fenouillet-Beranger does not teach the sacrificial coating layer has a thickness e15.
Henson teaches in Fig. 8 and paragraph [0057] a sacrificial coating layer (19) has a thickness e15 (implicit). The motivation for this modification is identified with respect to base claim 1.
Fenouillet-Beranger as modified by Henson above does not teach the ratio of thicknesses for the layers is such that e51<e15/3 or e51<e15/4. However, the instant application does not identify a performance/operational difference achieved by the dimensional limitations. [Where] the dimensional limitations [of the claimed device] d[o] not specify a device which perform[s] and operate[s] any differently from the prior art, a difference between such claimed dimensional limitations and those existing in the prior art is insufficient to render the claimed device non-obvious over the prior art. Gardner v. TEC Systems, Inc., 725 F.2d 1338, 1345, 1349 (Fed. Cir. 1984); see also MPEP 2144.04(IV)(A).
Regarding claim 14, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 1, and Fenouillet-Beranger further teaches wherein the sacrificial layer (13) is formed on the support layer (1) by epitaxy, said sacrificial layer (13) being SiGe-based {Fig. 9; [0033]}.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fenouillet-Beranger in view of Henson et al. (US20110147885A1) and Chang as applied to claim 1 above, and further in view of Clifton et al. (US20200273991A1).
Regarding claim 13, as interpreted in view of the indefiniteness rejection, Fenouillet-Beranger as modified by Henson and Chang teaches the method according to claim 1, but Fenouillet-Beranger does not teach wherein the isolating material of the isolation trenches is chosen to be a material of SiO2.
Henson teaches in paragraph [0047] an isolating material (20) of the isolation trenches (30) is field oxide. Clifton teaches in paragraph [0051] that SiO2 is a field oxide. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fenouillet-Beranger’s method as modified by Henson and Chang based on the further teachings of Henson and Clifton – such that the isolating material of the isolation trenches is chosen to be a material of SiO2 – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, all the claimed elements (e.g., isolating material, isolation trenches, SiO2) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Henson and Clifton) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Coronel (US20150249014A1) teaches a substrate of SOI type is covered by an etching mask defining three distinct semiconductor patterns. A lateral spacer is formed around the three patterns and performs the connection between two adjacent patterns. The buried insulating layer is eliminated so as to define a cavity which suspends a part of a first pattern. The first etching mask is eliminated. A gate dielectric is formed on two opposite main surfaces of the first pattern. The resist is deposited in the cavity and on the first pattern and is then exposed to form two patterns defining the bottom and top gates. An electrically conducting material is deposited in the cavity and on the first pattern so as to form the bottom gate and the top gate on each side of the first semiconductor material pattern.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID WARD whose telephone number is (703)756-1382. The examiner can normally be reached 6:30-3:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights