DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicants’ submission filed on November 20, 2025 has been entered.
Response to Amendment
The Amendment filed November 20, 2025 has been entered. Although the first paragraph on page 6 of Remarks indicates that claims 1,10, and 24 are amended, no amendments to claims are found except for the addition of claim 29. Claims 1, 3-12, 14-25, and 27-29 are pending in the application.
Response to Arguments
Applicant’s arguments, see pages 6-9 or Remarks, filed November 20, 2025, with respect to the rejection(s) of claim(s) 1, 10, and 24 and their dependent claims under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, in the case of claim 1, upon further consideration, a new ground(s) of rejection is made in view of additional prior art, in combination with that previously cited.
In the case of claim 10, the Applicants’ argument that the cited paragraphs and figures of Giuliano in the prior office action fail to establish how directly bonding without an intervening adhesive is taught, is persuasive. However, the Examiner believes that directly bonding is taught by Giuliano, and has updated the claim rejections below to cite the corresponding paragraphs and figures which establish this.
Please see the claim rejections below.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4, 6-9 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Chow et al (US 2006/0279905; hereinafter Chow) in view of Haraguchi et al (US 11,038,012; hereinafter Haraguchi) and Barth; Karl W. et al. (US 2011/0101537; hereinafter Barth).
Regarding claim 1, Chow (Fig. 2) discloses a passive electronic component (a capacitor; in particular Fig 2; ¶ [0022-43]; entire document), comprising:
the capacitor having a first electrode (200, 230; Fig 2; ¶ [0031]), a second electrode 210; Fig 2; ¶ [0031]), and a dielectric material (220; Fig 2; ¶ [0031]) disposed between the first and second electrodes, the first electrode comprising a first conductive layer (200) and a plurality of conductive fibers (230; ¶ [0031-32]) extending from and electrically connected to the first conductive layer, the second electrode conformally coating (¶ [0033]) the dielectric material .
Chow does not disclose the capacitor is embedded within a nonconductive material, and
providing a first conductive via that extends through the passive electronic component from a first surface to a second surface, the first conductive via electrically connected to the first electrode.
In the same field of endeavor, Haraguchi discloses a method (Figs 1-16; Col 8, line 20 – Col 12, line 38; entire document) comprising: providing a passive electronic component (30-1; Fig 15; Col 11, line 61 – Col 12, line 38) comprising a first surface (upper surface of 12; Fig 2 {unlabeled; Figs 14-15), a second surface opposite the first surface (lower surface of 2-1; Figs 14-15), and a capacitor (30-1{30}; Figs 15{1,2}) embedded within a nonconductive material (unlabeled; Fig 15; {12; Fig 2; Col 9, lines 20-21}); and providing a first conductive via (10; Figs 15; Col 12, lines 24-28) that extends through the passive electronic component from the first surface to the second surface, the first conductive via electrically connected to a first electrode (2-1; Fig 15; Col 12, lines 24-28). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitor of Chow by embedding the capacitor within a nonconductive material, and to provide a first conductive via that extends through the passive electronic component and electrically connects to the first electrode, in order to form a passive electronic component having external connection terminals exposed on an upper surface of the passive electronic component, as taught by Haraguchi (Col 9, lines 33-45). One would have had a reasonable expectation of success because of the similar configuration of the capacitor structures, having vertically extending portions from a lower planar electrode, of Haraguchi and Chow.
Neither Chow nor Haraguchi disclose directly bonding the passive electronic component to an element without an intervening adhesive to form a bonded structure.
In the same field of endeavor, Barth discloses a method of forming (Figs 1-7; ¶ [0025-60]) a bonded structure (Fig 7; ¶ [0057]), comprising a passive electronic component (100, comprising 120, which may be capacitor; Figs 1-7; ¶ [0025-29]) having a first conductive via (330; Fig 7; ¶ [0053-56]) extending through the passive electronic component 100, and directly bonding (¶ [0046-47]) the passive electronic component to an element (200; Figs 1-7; ¶ [0025-29,0057]) without an intervening adhesive to form a bonded structure.
Accordingly, it would have been obvious to a person having ordinary skill in the art to have used the direct bonding method of Barth to form the bonded structure comprising the modified passive electronic component of Chow in view of Haraguchi (substituting the modified capacitor of Chow/Haraguchi for the capacitor 120 of Barth having electrical connection to the direct bonding pad 160 (Barth; ¶ [0039-40). One would have been motivated to do this as a means to enable the smaller footprint of a three-dimensionally integrated component/element stack (or chip stack, as shown by Barth) comprising the passive electronic component and another element, while enabling flexibility of sourcing or providing the another element that may not be available in the stacking method disclosed by Haraguchi (Fig 15), which may be limited by capabilities of the manufacturing line which produces the passive electronic component. (Haraguchi discloses repeating manufacturing steps in the manufacturing of the passive electronic component in order to form a stacked structure; the direct bonding method of Barth may enable stacking the passive electronic component with a broader selection of elements which may be fabricated independently, as is known in the art).
Regarding claim 4, Chow in view of Haraguchi and Barth discloses the method of Claim 1, wherein providing the passive electronic component comprises directly bonding a plurality of passive components to one another (Barth discloses directly bonding the passive electronic component 100 to another passive electronic component 200, and Haraguchi discloses the passive electronic component 30-1 bonded to another passive electronic component 30-2; as applied to claim 1, the modified passive electronic component of Chow in view of Haraguchi is directly bonded to another passive electronic component which constitutes the element of claim 1 according to the direct bonding method disclosed by Barth).
Regarding claim 7, Chow in view of Haraguchi and Barth discloses the method of Claim 1, further comprising directly bonding the passive electronic component to the element before providing the first conductive via (Barth; Figs 5-7; ¶ [0046-53]).
Regarding claim 8, Chow in view of Haraguchi and Barth discloses the method of Claim 7, further comprising, after directly bonding, forming an opening through a plurality of stacked and bonded passive components and providing a conductive material in the opening to define the first conductive via (Barth; Figs 5-7; ¶ [0046-53]).
Regarding claim 9, Chow in view of Haraguchi and Barth discloses the method of Claim 8, further comprising connecting the conductive material to a corresponding electrical contact on the element (Barth discloses connecting the material of via 330 of passive electronic component 100 to the corresponding via 330 {an electrical contact} of element 200; it would have been obvious to a person having ordinary skill in the art to have made such connection according to claim 9 in order for the bonded structure to function as a circuit comprising the passive electronic component and the element).
Regarding claim 29, Chow in view of Haraguchi and Barth discloses the method of Claim 1, but does not disclose wherein the first conductive via is electrically connected to a first terminal at the first surface and a second terminal at the second surface.
However, Haraguchi discloses that three or more capacitor cells may be stacked and connected in parallel by forming the vias 10 (Fig 15) as through vias (¶ [0101]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have formed such a capacitor cell stack using the direct bonding method according to claim 1. It would be further obvious that each end of the through via 10 of each capacitor cell would be electrically connected to a terminal to facilitate the parallel connection for the stacked device to function.
Claims 10-12, and 14-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chow et al (US 2006/0279905) in view of Haraguchi et al (US 11,038,012) and Giuliano (US 2017/0179089; hereinafter Giuliano).
Regarding claim 10, Chow (Fig. 2) discloses a method of forming a passive electronic component (a capacitor; in particular, Fig 2; ¶ [0022-43]; entire document), the method comprising:
forming a first conductive layer (200; Fig 2; ¶ [0031]);
growing a plurality of conductive fibers (230; Fig 2; ¶ [0008,0031]) on the first conductive layer 200 such that the plurality of conductive fibers 230 extend non-parallel relative to a surface of the first conductive layer 200;
providing a second nonconductive layer (220; Fig 2; ¶ [0031,0033]) conformally over the plurality of conductive fibers 230; and
providing a second conductive layer (210; Fig 2; ¶ [0031]) conformally over the second nonconductive layer 220.
Chow does not disclose the first conductive layer 200 formed at a portion of a first nonconductive layer.
In the same field of endeavor, Haraguchi discloses a method of forming a passive electronic component (Figs 1-16; Col 8, line 20 – Col 12, line 38; entire document) comprising forming a first conductive layer (2; Figs 2,4; Col 9, lines 62-66) at a portion of a first nonconductive layer (1; Figs 2,4; Col 9, lines 62-66). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first conductive layer of Chow at a portion of a first nonconductive layer because as is well known, such first nonconductive layer would function as a support layer for supporting the capacitor component formed thereon.
Neither Chow nor Haraguchi discloses directly bonding the passive electronic component to an integrated device die without an intervening adhesive.
However, Giuliano (Figs 8A,8B) teaches a method comprising directly bonding a passive electronic component (41A; Figs 8A,8B; ¶ [0066]) to an integrated device die (42A; Figs 8A,8B; ¶ [0066]) without an intervening adhesive (¶ [0100]), claims 25,26; the described copper-copper and oxide-oxide bonding are direct bonding methods known in the art. As reference, one may consult ¶ [0002] of Barth; Karl W. et al. {US 2011/0101537}). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the device of Chow in view of Haraguchi by directly bonding the passive electronic component to an integrated device die in order to provide an electronic device such as a power converter having a compact structure (as taught by Giuliano; ¶ [0002]), because it is an intended use depending upon the desired electronic applications. One would have had a reasonable expectation of success because of the similar passive electronic components of Giuliano, Chow, and Haraguchi and the bonding method known in the art.
Regarding claim 11, Chow, in view of Haraguchi and Guiliano discloses the method of Claim 10, wherein the first conductive layer (Chow; 200; Fig 2) and the plurality of conductive fibers comprise different materials (Chow; 230; Fig 2; the electrode surface {200} and nanofibers {230} are different materials, in some embodiments; ¶ [0008]).
Regarding claim 12, Chow, in view of Haraguchi and Guiliano discloses the method of Claim 10, wherein the second nonconductive layer (Chow; 220; Fig 2) contacts the first conductive layer (Chow; 200; as shown in Fig 2; 200 is coated with 220; ¶ [0031]).
Regarding claim 14, Chow, in view of Haraguchi and Guiliano discloses the method of Claim 10, further comprising providing a precursor over the first conductive layer prior to providing the plurality of conductive fibers (Chow; for example, silane, NH.sub.3 {¶ [0099]}, metal organic or another precursor or catalytic surface {¶ [0100]}).
Regarding claim 15, Chow, in view of Haraguchi and Guiliano discloses the method of Claim 14, wherein the precursor is grown into the plurality of conductive fibers by way of thermal chemical vapor deposition (CVD) (Chow; ¶ [0100]).
Regarding claim 16, Chow, in view of Haraguchi and Guiliano discloses the method of Claim 10, wherein the plurality of conductive fibers (Chow; 230; Fig 2) comprise a carbon nanotube (Chow; ¶ [0052]).
Regarding claim 17, Chow, in view of Haraguchi and Guiliano discloses the method of Claim 10, wherein the plurality of conductive fibers (Chow; 230; Fig 2) have curls or waves along their lengths (Chow; ¶ [0079]).
Regarding claim 18, Chow, in view of Haraguchi and Guiliano discloses the method of Claim 10, but does not disclose wherein the plurality of conductive fibers (Chow; 230; Fig 2) include a first fiber and a second fiber that are spaced apart from one another by a spacing in a range of 40 nanometers and 150 nanometers.
However, Chow further discloses that the capacitors can have a number of different densities of nanofibers per unit area outline (¶ [0012]). Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. in re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to form the first and second fibers of Chow spacing apart from one another in a range as claimed because such spacing dimensions could be optimized during routine experimentation according to the requirements of the desired sizes and materials of the fibers and the capacitances which are desired for the capacitor.
Regarding claim 19, Chow, in view of Haraguchi and Guiliano discloses the method of Claim 18, wherein the first and second fibers (Chow; 230; Fig 2) extend non-parallel to one another (see Fig. 3B and ¶ [0079]).
Regarding claim 20, Chow, in view of Haraguchi and Guiliano discloses the method of Claim 10, wherein each of the plurality of conductive fibers has a length in a range of 1 micrometer to 30 micrometers (Chow; ¶ [0013]).
Regarding claim 21, Chow, in view of Haraguchi and Guiliano discloses the method of Claim 10, wherein each of the plurality of conductive fibers has a width in a range of 40 nanometers to 150 nanometers (Chow; ¶ [0013]).
Regarding claim 22, Chow, in view of Haraguchi and Guiliano discloses the method of Claim 10, wherein a first capacitance is defined between the first conductive layer (Chow; 200; Fig 2) and a first portion of the second conductive layer (Chow; 210; Fig 2; in a vertical direction, across horizontal portions of 220) and a second capacitance is defined between the plurality of conductive fibers (Chow; 230; Fig 2) and a second portion of the second conductive layer (210; in a horizontal direction across vertical portions of 220; Fig 2).
Regarding claim 23, Chow, in view of Haraguchi and Guiliano discloses the method of Claim 10, wherein the first nonconductive layer (Haraguchi; 1; Figs 2,4) is a silicon oxide layer (Haraguchi; column 8, lines 51-53) deposited over a carrier (Haraguchi; 16; Fig 4; column 11, lines 28-30).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 10 and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 24-26 of U.S. Patent No. 11,901,281. Although the claims at issue are not identical, they are not patentably distinct from each other because the patent includes all the limitations of the specified claims of the present application. Moreover, the claims in the instant application are either broader version of the claims in U.S. Patent ‘281 or are obvious variations thereof.
Regarding independent claim 1, the U.S. Patent ‘281 claims a method of forming a bonded structure, the method comprising: providing a passive electronic component comprising a first surface, a second surface opposite the first surface, and a capacitor embedded within a nonconductive material, the capacitor having a first electrode, a second electrode, and a dielectric material disposed between the first and second electrodes, the first electrode comprising a first conductive layer and a plurality of conductive fibers extending from and electrically connected to the first conductive layer (column 34, claim 24, lines 26-35 and column 35, claim 25), the second electrode conformally coating the dielectric material (column 35, claim 26); providing a first conductive via that extends through the passive electronic component from the first surface to the second surface, the first conductive via electrically connected to the first electrode (column 34, claim 24, lines 53-57); and directly bonding the passive electronic component to an element without an intervening adhesive (column 34, claim 24, lines 58-59).
Regarding independent claim 10, the U.S. Patent ‘281 claims a method of forming a bonded structure comprising a passive electronic component, the method comprising: forming the passive electronic component by: forming a first conductive layer at a portion of a first nonconductive layer (column 34, claim 24, lines 26-35); growing a plurality of conductive fibers on the first conductive layer such that the plurality of conductive fibers extend non-parallel relative to a surface of the first conductive layer (column 34, claim 24, lines 60-62 and column 35, claim 25); providing a second nonconductive layer conformally over the plurality of conductive fibers (column 35, claim 26); and providing a second conductive layer conformally over the second nonconductive layer (column 35, claim 26); and directly bonding the passive electronic component to an integrated device die without an intervening adhesive (column 34, claim 24, lines 58-59).
Regarding dependent claim 16, the U.S. Patent ‘281 does not claims the plurality of conductive fibers comprise a carbon nanotube. However, it would have been obvious to use a carbon nanotube as a material for the plurality of conductive fibers because as is well known, such carbon nanotube would have high tensile strength and increase the capacitance area surfaces of the capacitors.
Allowable Subject Matter
Claims 24-25 and 27-28 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 24, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “forming a conductive via after directly bonding the passive electronic component to the integrated device die, the conductive via electrically connected to the first conductive layer and extending through the passive electronic component”, in combination with the additional limitations of the claim.
The prior art Chow discloses a related method (Figs 14-16, and associated description) wherein directly bonding without an intervening adhesive is not disclosed and conductive vias are formed before bonding rather than after.
The prior art Barth discloses a related method (Figs 1-7; ¶ [0025-60]) comprising forming a conductive via after directly bonding without an intervening adhesive; however, the conductive via is not electrically connected with a first conductive layer of a passive electronic component; rather a capacitor is electrically connected to a pad which is directly bonded to a corresponding pad of an integrated device, and the conductive via passes through without connection to the capacitor.
The Examiner does not find that the prior art reviewed discloses nor renders obvious the particular limitation.
Claims 5 and 6 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the nonstatutory double patenting rejection is additionally overcome.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein each passive component of the plurality of passive components comprises a corresponding conductive via, the method further comprising directly bonding respective terminals of the corresponding conductive vias to one another to define the first conductive via”.
Regarding claim 6, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “forming an opening through the plurality of passive components and providing a conductive material in the opening to define the first conductive via”, and the first conductive via electrically connected to the first electrode (according to claim 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights