Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10, 15-17, 20, and 22 in the reply filed on April 1, 2026 is acknowledged. Claims 11-13 and 18-19 are withdrawn from further consideration.
Information Disclosure Statement
The information disclosure statements (IDS)s submitted on December 22, 2023 and January 19, 2024 were filed before the mailing of a first Office action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “510” has been used to designate both a vapor chamber with a continuous internal space in in figures 1, 4-12 and 13b and a vapor chamber with an internal space divided into a plurality of sub-spaces in figure 10 and reference character “511” has been used to designate both a chamber body without a mounting groove for a heat pipe in figures 1-2 and 4-12 and 13b and a chamber body with a mounting groove for a heat pipe in figure 3. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 8 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
7. Claim 8 recites the limitations “an internal space in which a first working fluid flows,” on page 3 lines 14-15 and “an internal space in which a second working fluid flows,” on page 3 lines 16-17. These limitations render the claim indefinite because these limitations recite the act of fluid flow. When both an apparatus and a method are claimed in the same claim it is unclear whether infringement occurs when the apparatus is constructed or when the apparatus is used. For examination purposes, these limitations will be treated as an internal space containing a first working fluid and an internal space containing a second working fluid.
8. Claim 22 recites the limitation “an internal space in which a first working fluid flows,” on page 6 line 5. This limitation renders the claim indefinite because this limitation recites the act of fluid flow. When both an apparatus and a method are claimed in the same claim it is unclear whether infringement occurs when the apparatus is constructed or when the apparatus is used. For examination purposes, this limitation will be treated as an internal space containing a first working fluid.
Claim Rejections - 35 USC § 102
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
10. Claims 1-2, 4-7, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cherian (US 2013/0199770).
Regarding Claim 1:
Cherian discloses a semiconductor package comprising:
a package substrate (PCB, See fig. 75, ref. no. PCB)
a semiconductor device (chip in a chip carrier mounted on PCB, See fig. 75 and paragraph 391) mounted on the package substrate; and
a heat dissipation structure (heat pipes and vertically stacked vapor chambers attached to the cover of the chip carrier, See fig. 75, ref. no. VC, paragraphs 391 and 393-394) attached to the semiconductor device, wherein the heat dissipation structure comprises
a plurality of vapor chambers (three vertically stacked vapor chambers, See fig. 75, ref. no. VC, paragraphs 391 and 393-394) at different levels in a vertical direction, and
a plurality of heat pipes (the heat pipes between the vapor chambers, See fig. 75, paragraphs 391, and 393-394) between the plurality of vapor chambers.
Regarding Claim 2:
Cherian discloses a first thermally conductive adhesive layer (solder between the heat pipes below the bottom vapor chamber and the bottom vapor chamber, See figs. 75, 77-A, and paragraphs 393-394) between a lowermost vapor chamber of the plurality of vapor chambers and the semiconductor device.
Regarding Claim 4:
Cherian discloses wherein the plurality of vapor chambers comprise three vapor chambers stacked in the vertical direction (three vertically stacked vapor chambers, See fig. 75, ref. no. VC, paragraphs 391 and 393-394), and wherein two vapor chambers neighboring one another in the vertical direction of the three vapor chambers are connected to one another through corresponding heat pipes of the plurality of heat pipes (the three vertically stacked vapor chambers are connected to one another through corresponding heat pipes, See fig. 75, paragraphs 391 and 393-394).
Regarding Claims 5-6:
Cherian discloses wherein each of the plurality of vapor chambers is coupled to corresponding heat pipes among the plurality of heat pipes by solder (the heat pipes are joined to the vapor chambers using solder, See fig. 77-A and paragraphs 393-394).
Regarding Claim 7:
Cherian discloses wherein each vapor chamber of the plurality of vapor chambers comprises a chamber body (structure of the vaper chamber surrounding the interior chamber, See figs. 75, 77-A, ref. no. VC) and wherein the chamber body of each vapor chamber has a mounting groove (pocket to accept heat pipe, See fig. 77-A, ref. no. VC and paragraph 393) into which a corresponding heat pipe of the plurality of heat pipes is inserted.
Regarding Claim 20:
Cherian discloses a heat dissipation structure comprising:
a plurality of vapor chambers (three vertically stacked vapor chambers, See fig. 75, ref. nos. VC and paragraphs 391, 393-394) at different levels in a vertical direction; and
a plurality of heat pipes (heat pipes between the vapor chambers, See fig. 75, paragraphs 391 and 393-394) between the plurality of vapor chambers.
11. Claims 15-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US 2024/0274504).
Regarding Claim 15:
Lin discloses a semiconductor package comprising:
a package substrate (package substrate, See fig. 1A, ref. no. 110 and paragraphs 37-38);
a semiconductor device (second semiconductor die, See fig. 1A, ref. no. 124 and paragraph 52) mounted on the package substrate; and
a heat dissipation structure (package lid, See fig. 1A, ref. no. 180 and paragraph 37) attached onto the semiconductor device,
wherein the heat dissipation structure comprises
a vapor chamber (vapor chamber base, See fig. 1A, ref. no. 130 and paragraphs 62-63) on the semiconductor device, and
a boiling enhancing layer (enhancement surface, See figs. 1A, 1C, ref. no. 170 and paragraphs 78-79) provided on an outer surface of the vapor chamber and comprising at least one of a porous structure (porous surface, See paragraph 79) or a structure having an uneven surface (uneven upper surface, See paragraph 79).
Regarding Claim 16:
Lin discloses wherein the vapor chamber is attached to an upper surface of the semiconductor device (upper surface of second semiconductor die, See fig. 1A, ref. no. 124) by a thermally conductive adhesive layer (thermal interface layer, See fig. 1A, ref. no. 140 and paragraph 57) extending along the upper surface of the semiconductor device.
12. Claims 20 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lan (US 2017/0347489).
Regarding Claim 20:
Lan discloses a heat dissipation structure comprising:
a plurality of vapor chambers (a bottom vapor chamber formed by a first housing and a top vapor chamber formed by a second housing, See figs. 1-2, ref. nos. 10, 12, and paragraphs 30-31) at different levels in a vertical direction; and
a plurality of heat pipes (at least one integrally formed pipe, See figs. 1-2, ref. no. 11 and paragraph 30. The examiner notes that at least one integrally formed pipes discloses two. The examiner also notes that Lan discloses the number of pipes can be changed according to actual needs. See paragraph 30.) between the plurality of vapor chambers.
Regarding Claim 22:
Lan discloses wherein each vapor chamber of the plurality of vapor chambers comprises: a chamber body (the first housing provides a first inner space in which a first working fluid flows and the second housing provides a second chamber in which a second working fluid flows, See fig. 3, ref. nos. 14, 15, 103a, 123 and paragraphs 30-31) providing an internal space in which a first working fluid flows; and
a first wick structure (a first wick structure provided on an inner wall of the first inner space and a third wick structure provided on an inner wall of the second chamber, See fig. 3, ref. nos. 104, 124, and paragraphs 30-31) extending along an inner wall surface of the chamber body.
Claim Rejections - 35 USC § 103
13. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Ku et al. (US 2021/0233833) in view of Lan (US 2017/0347489).
Regarding Claim 1:
Ku discloses a semiconductor package comprising:
a package substrate (three dimensional integrated circuit package substrate, See fig 1A, ref. no. 103 and paragraph 21);
a semiconductor device (processor, See fig. 1A, ref. no. 115 and paragraph 26) mounted on the package substrate; and
a heat dissipation structure (vapor chamber lid, See fig. 1A, ref. no. 131, paragraphs 30 and 40) attached to the semiconductor device.
Ku does not disclose wherein the heat dissipation structure comprises a plurality of vapor chambers at different levels in a vertical direction, and a plurality of heat pipes between the plurality of vapor chambers.
Lan discloses the heat dissipation structure comprises a plurality of vapor chambers at different levels in a vertical direction (a bottom vapor chamber formed by a first housing and a top vapor chamber formed by a second housing, See figs. 1-2, ref. nos. 10, 12, and paragraphs 30-31), and a plurality of heat pipes (at least one integrally formed pipe, See figs. 1-2, ref. no. 11 and paragraph 30. The examiner notes that at least one integrally formed pipes discloses two. The examiner also notes that Lan discloses the number of pipes can be changed according to actual needs. See paragraph 30.) between the plurality of vapor chambers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Ku to include wherein the heat dissipation structure comprises a plurality of vapor chambers at different levels in a vertical direction, and a plurality of heat pipes between the plurality of vapor chambers as taught by Lan in order to provide heat dissipation at a remote distance. (See Lan paragraph 8.)
Regarding Claim 2:
Ku discloses a first thermally conductive adhesive layer (second thermal interface material, See fig. 1A, ref. no. 113, paragraphs 27-28 and 30) between a lowermost vapor chamber of the plurality of vapor chambers and the semiconductor device.
15. Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Ku et al. (US 2021/0233833) in view of Lan (US 2017/0347489) herein after Lan ‘489 further in view of Lan (US 2017/0343295) herein after Lan ‘295.
Regarding Claim 3:
The above stated combination of Ku and Lan ‘489 discloses the above stated semiconductor package.
The above stated combination of Ku and Lan ‘489 does not disclose wherein lengths of the plurality of vapor chambers in a horizontal direction are different from each other.
Lan ‘295 discloses wherein lengths of the plurality of vapor chambers (a second case has a length greater than a third case, See fig. 1A, ref. nos. 12, 13, paragraphs 14 and 34) in a horizontal direction are different from each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Ku and Lan ‘489 to include wherein the length of the top vapor chamber is greater than the length of the bottom vapor chamber as taught by Lan ‘295 in order to increase heat dissipation area. (See Lan ‘295 paragraph 14.)
Regarding Claim 4:
The above stated combination of Ku and Lan ‘489 discloses the above stated semiconductor package.
The above stated combination of Ku and Lan ‘489 does not disclose wherein the plurality of vapor chambers comprise three vapor chambers stacked in the vertical direction, and wherein two vapor chambers neighboring one another in the vertical direction of the three vapor chambers are connected to one another through corresponding heat pipes of the plurality of heat pipes.
Lan ‘295 discloses three vapor chambers stacked the vertical direction (a first case, a second case, and a third case See fig. 1A, ref. nos. 11, 12, 13 and paragraph 34) and wherein the middle vapor chamber is connected to the top vapor chamber by a plurality of heat pipes (the first case is connected to the second case by two second heat pipes, See fig. 1A, ref. nos. 11, 12, 15, and paragraph 34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Ku and Lan ‘489 to include three vapor chambers stacked the vertical direction and wherein the middle vapor chamber is connected to the top vapor chamber by a plurality of heat pipes as taught by Lan ‘295 in order to increase heat dissipation area. (See Lan ‘295 paragraph 14.)
16. Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Refai-Ahmed (US 2010/0230805) in view of Cherian (US 2013/0199770).
Regarding Claim 1:
Refai-Ahmed discloses a semiconductor package comprising:
a package substrate (substrate, See fig 8, ref. no. 12’’, paragraphs 22 and 51);
a semiconductor device (die, See fig. 8, ref. no. 22’’, paragraphs 28 and 51) mounted on the package substrate; and
a heat dissipation structure (lid including a vapor chamber, See fig. 8, ref. no. 112 and paragraph 51) attached to the semiconductor device.
Refai-Ahmed does not disclose wherein the heat dissipation structure comprises a plurality of vapor chambers at different levels in a vertical direction, and a plurality of heat pipes between the plurality of vapor chambers.
Cherian discloses a heat dissipation structure comprises a plurality of vapor chambers at different levels in a vertical direction (vertically stacked vapor chambers, See fig. 75, ref. no. VC, paragraphs 391 and 393-394), and a plurality of heat pipes (the heat pipes between the vapor chambers, See fig. 75, paragraphs 391 and 393-394) between the plurality of vapor chambers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Refai-Ahmed to include wherein the heat dissipation structure comprises a plurality of vapor chambers at different levels in a vertical direction, and a plurality of heat pipes between the plurality of vapor chambers as taught by Cherian in order to provide heat dissipation at a remote distance.
Regarding Claim 2:
Refai-Ahmed discloses a first thermally conductive adhesive layer (heat conductive bonding material, See fig. 8, ref. no. 36’’, paragraphs 39 and 51) between a lowermost vapor chamber of the plurality of vapor chambers and the semiconductor device.
17. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Refai-Ahmed (US 2010/0230805) in view of Cherian (US 2013/0199770) further in view of Lin et al. (US 2024/0274504).
Regarding Claim 9:
The above stated combination of Refai-Ahmed and Cherian discloses the above stated semiconductor package.
The above stated combination of Refai-Ahmed and Cherian does not disclose wherein the heat dissipation structure comprises a porous structure extending along outer surfaces of the plurality of vapor chambers.
Lin discloses a porous structure extending along outer surface of a vapor chamber (enhancement layer including a porous surface on an outer wall of a vapor chamber enclosure, See fig. 1A, 1C, ref. nos. 130a, 170, and paragraphs 78-79).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Refai-Ahmed and Cherian to include enhancement layers including a porous surface on outer walls of each of the vapor chambers such as that taught by Lin in order to enhance heat spreading. (See Lin paragraph 34.)
18. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Refai-Ahmed (US 2010/0230805) in view of Cherian (US 2013/0199770) further in view of Joshi et al. (US 11,415,370).
Regarding Claim 10:
The above stated combination of Refai-Ahmed and Cherian discloses the above stated semiconductor package.
The above stated combination of Refai-Ahmed and Cherian does not disclose wherein the heat dissipation structure comprises a plurality of protruding patterns provided on outer surfaces of the plurality of vapor chambers.
Joshi discloses an expandable vapor chamber having a heat plate comprising a plurality of fins on a curved outer surface of the expandable vapor chamber (See fig. 5B, ref. no. 201, 282, and col. 9 lines 12-34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Refai-Ahmed and Cherian to include a plurality of fins on an outer surface of each of the vapor chambers such as that taught by Joshi in order to enhance heat dissipation.
19. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cherian (US 2013/0199770) in view of Refai-Ahmed (US 2010/0230805).
Regarding Claim 8:
Cherian discloses the above stated semiconductor package. Cherian further discloses each vapor chamber of the plurality of vapor chambers comprises a chamber body providing an internal space (the three vertically stacked vapor chambers have structures surrounding interior chambers, See figs. 75, 77-A, ref. no. VC).
Cherian does not disclose wherein each vapor chamber of the plurality of vapor chambers comprises a chamber body providing an internal space in which a first working fluid flows and wherein each heat pipe of the plurality of heat pipes comprises a pipe body providing an internal space in which a second working fluid flows.
Refai-Ahmed discloses wherein each vapor chamber (vapor chamber having an internal space containing a liquid, See fig. 8, ref. nos. 112, 116 and paragraph 51) of the plurality of vapor chambers comprises a chamber body providing an internal space in which a first working fluid flows, and wherein each heat pipe (heat pipe having an internal space containing a liquid, See fig. 8, ref. nos. 114, 116, and paragraph 51) of the plurality of heat pipes comprises a pipe body providing an internal space in which a second working fluid flows.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Cherian to include wherein each vapor chamber of the plurality of vapor chambers comprises a chamber body providing an internal space in which a first working fluid flows and wherein each heat pipe of the plurality of heat pipes comprises a pipe body providing an internal space in which a second working fluid flows as taught by Refai-Ahmed in order to increase transfer of heat through the heat dissipation structure.
20. Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Refai-Ahmed (US 2010/0230805) in view of Lin et al. (US 2024/0274504).
Regarding Claim 15:
Refai-Ahmed discloses a semiconductor package comprising:
a package substrate (substrate, See fig 8, ref. no. 12’’, paragraphs 22 and 51);
a semiconductor device (die, See fig. 8, ref. no. 22’’, paragraphs 28 and 51) mounted on the package substrate; and
a heat dissipation structure (lid including a vapor chamber, See fig. 8, ref. no. 112 and paragraph 51) attached to the semiconductor device,
wherein the heat dissipation structure comprises
a vapor chamber on the semiconductor device (vapor chamber, See fig. 8, ref. no. 112 and paragraph 51).
Refai-Ahmed does not disclose a boiling enhancing layer provided on an outer surface of the vapor chamber and comprising at least one of a porous structure or a structure having an uneven surface.
Lin discloses a boiling enhancing layer (enhancement surface, See figs. 1A,1C, ref. no. 170 and paragraphs 78-79) provided on an outer surface of the vapor chamber and comprising at least one of a porous structure (porous surface, See paragraph 79) or a structure having an uneven surface (uneven upper surface, See paragraph 79).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Refai-Ahmed to include a boiling enhancing layer provided on an outer surface of the vapor chamber and comprising at least one of a porous structure or a structure having an uneven surface as taught by Lin in order to enhance heat spreading. (See Lin paragraph 34)
Regarding Claim 16:
Refai-Ahmed discloses wherein the vapor chamber is attached to an upper surface of the semiconductor device (upper surface of die, See fig. 8, ref. no. 22’’) by a thermally conductive adhesive layer (thermal interface layer, See fig. 8, ref. no. 36’’ and paragraph 39 and 51) extending along the upper surface of the semiconductor device.
21. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Refai-Ahmed (US 2010/0230805) in view of Lin et al. (US 2024/0274504) further in view of Cherian (US 2013/0199770).
Regarding Claim 17:
The above stated combination of Refai-Ahmed and Lin discloses the above stated semiconductor package.
The above stated combination of Refai-Ahmed and Lin does not disclose an upper vapor chamber on the vapor chamber; and a heat pipe between the vapor chamber and the upper vapor chamber, wherein the boiling enhancing layer is provided on an outer surface of the heat pipe.
Cherian discloses an upper vapor chamber (middle vapor chamber of the vertically stacked vapor chamber, See fig. 75, ref. no. VC, paragraphs 391 and 393-394) on the vapor chamber and a heat pipe (heat pipe between the bottom vapor chamber and the middle vapor chamber, See figs. 75, 77-A paragraphs 391 and 393-394) between the vapor chamber and the upper vapor chamber.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Refai-Ahmed and Lin to include an upper vapor chamber on the vapor chamber and a heat pipe between the vapor chamber and the upper vapor chamber as taught by Cherian in order to provide heat dissipation at a remote distance.
The above stated combination of Refai-Ahmed, Lin, and Cherian does not disclose wherein the boiling enhancing layer is provided on an outer surface of the heat pipe.
Lin discloses an enhancement surface on substantially the entire surface of a structure for cooling the semiconductor dies (See fig. 1A, ref. nos. 100, 170, paragraphs 52, 78-79, 81)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Refai-Ahmed, Lin, Cherian to include the boiling enhancing layer on an outer surface of the heat pipe as taught by Lin in order to enhance heat spreading. (See Lin paragraph 34)
22. Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Cherian (US 2013/0199770) in view of Lin et al. (US 2024/0274504).
Regarding Claim 22:
Cherian discloses the above stated heat dissipation structure. Cherian further discloses each vapor chamber of the plurality of vapor chambers comprises a chamber body providing an internal space (the three vertically stacked vapor chambers have structures surrounding interior chambers, See figs. 75, 77-A, ref. no. VC).
Cherian does not disclose wherein each vapor chamber of the plurality of vapor chambers comprises a chamber body providing an internal space in which a first working fluid flows and a first wick structure extending along an inner wall surface of the chamber body.
Lin discloses a vapor chamber base (vapor chamber base, See fig. 1A, ref. no. 130, and paragraph 62) comprises a chamber body (vapor chamber enclosure, See fig. 1A, ref. no. 130a, and paragraph 62) providing an internal space in which a first working (vapor chamber working fluid, See fig. 1A, ref. no. 135 and paragraph 62) fluid flows, and a first wick structure (vapor chamber wick structure, See fig. 1A, ref. no. 130c and paragraph 62) extending along an inner wall surface of the chamber body.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify heat dissipation structure of Cherian to include each vapor chamber of the plurality of vapor chambers comprises a chamber body providing an internal space in which a first working fluid flows and a first wick structure extending along an inner wall surface of the chamber body as taught by Lin in order increase transfer of heat through the heat dissipation structure.
Conclusion
23. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRETT SQUIRES whose telephone number is (571)272-8214. The examiner can normally be reached Mon-Fri 8:00am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
Prosecution Insights