DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, lines 11-13 of the claim recites the claim feature “wherein the remaining receiver circuits are further configured to phase-shift the reference clock based on the respective time-multiplexed phase offsets to provide the respective receiver clocks”. It is unclear how the remaining receiver circuits phase-shift the reference clock based on the respective time-multiplexed phase offsets, when the determined time-multiplexed phase offsets are determined to be applied for the remaining receiver circuits and not the reference clock of the reference receiver circuit in claim 1 for providing the respective receiver clocks. For example in light of the applicants specification, Para’s [0039] & [0041] discloses i.e., the time-interleaved de-skew circuitry 130 that determines time-interleaved phase offsets 132 for the remaining receiver circuits 110. According to Fig. 1 and Para [0056] of the applicants disclosure, the de-skew circuit 402 determines the phase offsets 132 for all but the reference receiver. Therefore it is unclear how the remaining receiver circuits 110 phase shift the reference clock based on the respective phase offsets to provide their respective phase-appropriate receiver clocks (i.e., see Para [0039] of applicants specification). For purposes of examination, the examiner interprets the claim feature to be the remaining receiver circuits phase shifting their own receiver clocks based on the determined phase offsets relative to the reference clock in order to provide their respective phase-appropriate receiver clocks. Clarification is required.
If applicant has reasoning as to how the remaining receiver circuits 110 phase-shift the reference clock based on the determined phase offsets to provide their respective receiver clocks, the examiner asks the applicant to clarify the claim feature of “wherein the remaining receiver circuits are further configured to phase-shift the reference clock based on the respective time-multiplexed phase offsets to provide the respective receiver clocks”. Independent claims 8 and 15 which recites the same claim feature as claim 1, are also rejected under 35 U.S.C. 112(b) for the same reason as claim 1. The dependent claims 2-7, 9-14, and 16-20 are also rejected under 35 U.S.C. 112(b) based on their dependence to independent claims 1, 8, and 15.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-10, 15, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939).
Regarding Claim 1, Hossain discloses a system (see Fig. 3), comprising: a plurality of receiver circuits (see Fig. 3 i.e., receivers including samplers 61-64 on each communication line 11-14) configured to sample signals based on respective receiver clocks, (see Fig. 3 & Para’s [0025], [0035] i.e., while the per-lane, local clock recovery circuits & [0036] i.e., the second integrated circuit 60 includes a receiver on each one of the communication lines 11-14. These receivers include corresponding samplers 41-44, using local recovered clocks, and producing the corresponding data streams “D1” to “D4”)
a reference receiver circuit (see Fig. 3 i.e., global clock recovery circuit including frequency tracker and phase adjuster & Para [0036]) and remaining receiver circuits (see Fig. 3 i.e., receivers 61-64 & Para [0036]),
and wherein a receiver clock of the reference receiver circuit comprises a reference clock, (see Fig. 3 i.e., R-CK (i.e., “reference clock”) & Para’s [0025] i.e., A global clock recovery circuit 45 produces a global recovered clock R-CK (i.e., “reference clock”) shared by all lanes to produce a respective, local recovered clock to control local sampling times at the respective samplers 41-44, [0036] i.e., Each local phase adjuster 71-74 receives the global recovered clock (i.e., “reference clock”) across line 69, [0037] i.e., global recovered clock R-CK is provided to each of the local clock recovery circuits & [0040])
a clock and data recovery (CDR) circuit (see Fig. 3 i.e., global clock recovery circuit including Frequency tracker 65 & Phase adjuster 72) configured to control a phase of the reference clock based on outputs of the reference receiver circuit; (see Para [0036] i.e., The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66)
and time-multiplexed de-skew circuitry (see Fig. 3 i.e., local phase adjuster 71-74) configured to determine time-multiplexed phase offsets for the remaining receiver circuits (see Fig. 3 i.e., receivers 61-64) based on time-multiplexed outputs of the remaining receiver circuits; (see Fig. 3 & Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74 & [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66 & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators)
wherein the remaining receiver circuits (see Fig. 3 i.e., receivers 61-64) are further configured to phase-shift the reference clock based on the respective time-multiplexed phase offsets to provide the respective receiver clocks, (see Fig. 3 & Para’s [0028], [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74, [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine and apply “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66, [0038] i.e., digital phase interpolator, which produces the local recovered clock used for sampling data & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators)
While Hossain discloses the global clock recovery circuit which includes the reference clock provided to the remaining receiver circuits for performing the phase-shift based on determined phase offsets, Hossain does not disclose the global clock recovery circuit is included in a reference receiver circuit of the receiver circuits and the claim feature of wherein the receiver circuits comprise a reference receiver circuit. However the claim features would be rendered obvious in view of Wolkovitz et al. USP (11,031,939).
Wolkovitz discloses a clock data recovery circuit (CDR) is included in a reference receiver circuit of receiver circuits (see Fig. 3 i.e., Clock-Data-Recovery circuit (CDR) 116 (i.e., “reference receiver circuit”) which samples data on lane 3 among remaining receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57 i.e., Clock-Data-Recovery circuit (CDR) 116 that is coupled to lane 3, and samplers 118, which are coupled to lanes 1, 2, 4, and 5…the CDR is further configured to output phase correction signaling, which indicates phase corrections to the Receiver Clock that are needed to properly sample the data…the samplers receive phase correction signaling from the CDR, and sample data from the respective lanes)
wherein the receiver circuits comprise a reference receiver circuit (see Fig. 3 i.e., CDR 116 coupled to lane 3 may be a reference receiver circuit among the receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57)
(Wolkovitz suggests the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase, (see Col. 4 line 39-57)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the global clock recovery circuit which includes the reference clock that is provided to the remaining receiver circuits for performing the phase-shift based on the determined phase offsets as disclosed in Hossain to be included in a reference receiver circuit of the plurality of receiver circuits based on the teachings of Wolkovitz who discloses a clock data recovery circuit (CDR) is included in a reference receiver circuit of a plurality of receiver circuits, which results in controlling the phase of the reference clock based on outputs of the reference receiver circuit, because the motivation lies in Wolkovitz that the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase.
Regarding Claim 2, Hossain discloses the system of claim 1, but does not disclose the claim feature of further comprising: reference channel selection circuitry configured to select one of the receiver circuits as the reference receiver circuit. However the claim features would be rendered obvious in view of Wolkovitz et al. USP (11,031,939).
Wolkovitz discloses reference channel selection circuitry configured to select one of the receiver circuits as the reference receiver circuit (see Col. 9 lines 3-13 i.e., hardware such as ASIC or FPGA may configure or select the CDR 116 ( i.e., reference receiver circuit)).
(Wolkovitz suggests the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase, (see Col. 4 line 39-57)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the system disclosed in Hossain to include reference channel selection circuitry configured to select one of the receiver circuits as the reference receiver circuit as disclosed in Wolkovitz, because the motivation lies in Wolkovitz that the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase
Regarding Claim 3, Hossain discloses the system of claim 1, wherein the time-multiplexed de-skew circuitry (see Fig. 3 i.e., local phase adjuster 71-74) is further configured to determine the time-multiplexed phase offsets for enabled ones of the remaining receiver circuits, (see Fig. 3 i.e., receivers 61-64 which performs phase adjustment may be enabled ones of the remaining receiver circuits & Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74 & [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66 & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators)
Regarding Claim 8, Hossain discloses a method, comprising: extracting data from a plurality of signals with respective receiver circuits based on respective receiver clocks, (see Fig. 3 i.e., receivers including samplers 61-64 on each communication line 11-14 & Para’s [0025], [0035] i.e., while the per-lane, local clock recovery circuits & [0036] i.e., the second integrated circuit 60 includes a receiver on each one of the communication lines 11-14. These receivers include corresponding samplers 41-44, using local recovered clocks, and producing the corresponding data streams “D1” to “D4”)
a reference receiver circuit (see Fig. 3 i.e., global clock recovery circuit including frequency tracker and phase adjuster) and remaining receiver circuits (see Fig. 3 i.e., receivers 61-64),
and wherein a receiver clock of the reference receiver circuit comprises a reference clock, (see Fig. 3 i.e., R-CK (i.e., “reference clock”) & Para’s [0025] i.e., A global clock recovery circuit 45 produces a global recovered clock R-CK (i.e., “reference clock”) shared by all lanes to produce a respective, local recovered clock to control local sampling times at the respective samplers 41-44, [0036] i.e., Each local phase adjuster 71-74 receives the global recovered clock (i.e., “reference clock”) across line 69, [0037] i.e., global recovered clock R-CK is provided to each of the local clock recovery circuits & [0040])
controlling a frequency of the reference clock based on outputs of the reference receiver circuit; (see Fig. 3 i.e., global clock recovery circuit including Frequency tracker 65 & Phase adjuster 72 Para [0036] i.e., The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66)
determining time-multiplexed phase offsets for the remaining receiver circuits (see Fig. 3 i.e., receivers 61-64) based on time-multiplexed outputs of the remaining receiver circuits; (see Fig. 3 i.e., local phase adjuster 71-74 & Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74 & [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66 & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators)
phase-shifting the reference clock for the remaining receiver circuits based on the respective phase offsets to provide the respective receiver clocks, (see Fig. 3 & Para’s [0028], [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74, [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine and apply “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66, [0038] i.e., digital phase interpolator, which produces the local recovered clock used for sampling data & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators)
While Hossain discloses the global clock recovery circuit which includes the reference clock provided to the remaining receiver circuits for performing the phase-shift based on determined phase offsets, Hossain does not disclose the global clock recovery circuit is included in a reference receiver circuit of the receiver circuits and the claim feature of wherein the receiver circuits comprise a reference receiver circuit. However the claim features would be rendered obvious in view of Wolkovitz et al. USP (11,031,939).
Wolkovitz discloses a clock data recovery circuit (CDR) is included in a reference receiver circuit of receiver circuits (see Fig. 3 i.e., Clock-Data-Recovery circuit (CDR) 116 (i.e., “reference receiver circuit”) which samples data on lane 3 among remaining receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57 i.e., Clock-Data-Recovery circuit (CDR) 116 that is coupled to lane 3, and samplers 118, which are coupled to lanes 1, 2, 4, and 5…the CDR is further configured to output phase correction signaling, which indicates phase corrections to the Receiver Clock that are needed to properly sample the data…the samplers receive phase correction signaling from the CDR, and sample data from the respective lanes)
wherein the receiver circuits comprise a reference receiver circuit (see Fig. 3 i.e., CDR 116 coupled to lane 3 may be a reference receiver circuit among the receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57)
(Wolkovitz suggests the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase, (see Col. 4 line 39-57)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the global clock recovery circuit which includes the reference clock that is provided to the remaining receiver circuits for performing the phase-shift based on the determined phase offsets as disclosed in Hossain to be included in a reference receiver circuit of the plurality of receiver circuits based on the teachings of Wolkovitz who discloses a clock data recovery circuit (CDR) is included in a reference receiver circuit of a plurality of receiver circuits, which results in controlling the frequency of the reference clock based on outputs of the reference receiver circuit, because the motivation lies in Wolkovitz that the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase.
Regarding Claim 9, the claim is directed towards a method which performs the same claim features as the system of claim 2. Therefore claim 9 is rejected as obvious over the combination of Hossain in view of Wolkovitz as in claim 2.
Regarding Claim 10, the claim is directed towards a method which performs the same claim features as the system of claim 3. Therefore claim 10 is rejected as obvious over the combination of Hossain in view of Wolkovitz as in claim 3.
Regarding Claim 15, Hossain discloses a system (see Fig. 3), comprising: a first integrated circuit (IC) device (see Fig. 3 i.e., integrated circuit 60 & Para [0036]), comprising a plurality of receiver circuits (see Fig. 3 i.e., receivers including samplers 61-64 on each communication line 11-14) and a clock and data recovery (CDR) system (see Fig. 3 & Para’s [0035-0036]),
wherein, the receiver circuits are configured to sample signals based on respective receiver clocks, (see Fig. 3 & Para’s [0025], [0035] i.e., while the per-lane, local clock recovery circuits & [0036] i.e., the second integrated circuit 60 includes a receiver on each one of the communication lines 11-14. These receivers include corresponding samplers 41-44, using local recovered clocks, and producing the corresponding data streams “D1” to “D4”)
a reference receiver circuit (see Fig. 3 i.e., global clock recovery circuit including frequency tracker and phase adjuster & Para [0036]) and remaining receiver circuits (see Fig. 3 i.e., receivers 61-64 & Para [0036]),
and a receiver clock of the reference receiver circuit comprises a reference clock, (see Fig. 3 i.e., R-CK (i.e., “reference clock”) & Para’s [0025] i.e., A global clock recovery circuit 45 produces a global recovered clock R-CK (i.e., “reference clock”) shared by all lanes to produce a respective, local recovered clock to control local sampling times at the respective samplers 41-44, [0036] i.e., Each local phase adjuster 71-74 receives the global recovered clock (i.e., “reference clock”) across line 69, [0037] i.e., global recovered clock R-CK is provided to each of the local clock recovery circuits & [0040])
the CDR system comprises a CDR circuit (see Fig. 3 i.e., global clock recovery circuit including Frequency tracker 65 & Phase adjuster 72) configured to control a phase of the reference clock based on outputs of the reference receiver circuit, (see Para [0036] i.e., The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66)
and time-multiplexed de-skew circuitry (see Fig. 3 i.e., local phase adjuster 71-74) configured to determine time-multiplexed phase offsets for the remaining receiver circuits (see Fig. 3 i.e., receivers 61-64) based on time-multiplexed outputs of the remaining receiver circuits, (see Fig. 3 & Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74 & [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66 & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators)
and the remaining receiver circuits (see Fig. 3 i.e., receivers 61-64) are further configured to phase-shift the reference clock based on the respective time-multiplexed phase offsets to provide the respective receiver clocks; (see Fig. 3 & Para’s [0028], [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74, [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine and apply “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66, [0038] i.e., digital phase interpolator, which produces the local recovered clock used for sampling data & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators)
and a second IC device configured to receive outputs of the receiver circuits, (see Fig. 3 i.e., global clock recovery circuit may be a second IC device (i.e., Fig. 4, 98) which receives error signal output from receivers 61-64 & Para’s [0037-0039] & [0042-0043])
While Hossain discloses the global clock recovery circuit which includes the reference clock provided to the remaining receiver circuits for performing the phase-shift based on determined phase offsets, Hossain does not disclose the global clock recovery circuit is included in a reference receiver circuit of the receiver circuits and the claim feature of wherein the receiver circuits comprise a reference receiver circuit. However the claim features would be rendered obvious in view of Wolkovitz et al. USP (11,031,939).
Wolkovitz discloses a clock data recovery circuit (CDR) is included in a reference receiver circuit of receiver circuits (see Fig. 3 i.e., Clock-Data-Recovery circuit (CDR) 116 (i.e., “reference receiver circuit”) which samples data on lane 3 among remaining receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57 i.e., Clock-Data-Recovery circuit (CDR) 116 that is coupled to lane 3, and samplers 118, which are coupled to lanes 1, 2, 4, and 5…the CDR is further configured to output phase correction signaling, which indicates phase corrections to the Receiver Clock that are needed to properly sample the data…the samplers receive phase correction signaling from the CDR, and sample data from the respective lanes)
wherein the receiver circuits comprise a reference receiver circuit (see Fig. 3 i.e., CDR 116 coupled to lane 3 may be a reference receiver circuit among the receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57)
(Wolkovitz suggests the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase, (see Col. 4 line 39-57)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the global clock recovery circuit which includes the reference clock that is provided to the remaining receiver circuits for performing the phase-shift based on the determined phase offsets as disclosed in Hossain to be included in a reference receiver circuit of the plurality of receiver circuits based on the teachings of Wolkovitz who discloses a clock data recovery circuit (CDR) is included in a reference receiver circuit of a plurality of receiver circuits, which results in controlling the phase of the reference clock based on outputs of the reference receiver circuit, because the motivation lies in Wolkovitz that the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase.
Regarding Claim 19, the claim is directed towards a system which performs the same claim features as the system of claim 2. Therefore claim 19 is rejected as obvious over the combination of Hossain in view of Wolkovitz as in claim 2.
Regarding Claim 20, the claim is directed towards a method which performs the same claim features as the system of claim 3. Therefore claim 20 is rejected as obvious over the combination of Hossain in view of Wolkovitz as in claim 3.
Claims 4-5, 11-12, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939) as applied to claim 1 above, and further in view of Moshe et al. US (2024/0143518).
Regarding Claim 4, the combination of Hossain in view of Wolkovitz discloses the system of claim 1, but does not disclose the claim feature of further comprising: time-multiplexed calibration circuitry configured to determine time-multiplexed channel-specific parameters for the receiver circuits based on time-multiplexed outputs of the receiver circuits. However the claim feature would be rendered obvious in view of Moshe et al. US (2024/0143518).
Moshe discloses time-multiplexed calibration circuitry configured to determine time-multiplexed channel-specific parameters for the receiver circuits based on time-multiplexed outputs of the receiver circuits (see Para [0060] i.e., For example, each link, lane, and/or channel may include receive filters and transmitter filters with coefficients (i.e., “parameters”) that are configured to establish data signal integrity meeting the predefined BER threshold. These sets of coefficient values may be determined and verified by link state machine 532.1 (i.e., “calibration circuitry”)…For example, coefficient value logic 532.2 may check a register managed by configuration service 542 for previously used coefficient values(i.e., “parameters”) (i.e., previously used coefficient values for meeting the predetermined BER threshold is based on the receiver output of each lane)).
(Moshe suggests the coefficients are configured for each receiver lane for meeting the predefined BER threshold for establishing data signal integrity, (see Para [0060])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the receiver circuits in each of the lanes as disclosed in the system of Hossain in view of Wolkovitz to comprise the time-multiplexed calibration circuitry configured to determine time-multiplexed channel-specific parameters for the receiver lanes based on time-multiplexed outputs of the receiver circuits as disclosed in Moshe, because the motivation lies in Moshe that the coefficients are configured for each receiver lane for meeting the predefined BER threshold for establishing data signal integrity.
Regarding Claim 5, the combination of Hossain in view of Wolkovitz discloses the system of claim 4, but does not disclose the claim feature of wherein the calibration circuitry is further configured to determine the channel-specific parameters for enabled ones of the receiver circuits. However the claim feature would be rendered obvious in view of Moshe et al. US (2024/0143518).
Moshe discloses wherein the calibration circuitry is further configured to determine the channel-specific parameters for enabled ones of the receiver circuits (see Para [0060] i.e., For example, each link, lane, and/or channel (i.e., enabled receiver circuits on each lane) may include receive filters and transmitter filters with coefficients (i.e., “parameters”) that are configured to establish data signal integrity meeting the predefined BER threshold)
(Moshe suggests the coefficients are configured for each receiver lane for meeting the predefined BER threshold for establishing data signal integrity, (see Para [0060])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the receiver circuits in each of the lanes as disclosed in the system of Hossain in view of Wolkovitz to comprise the time-multiplexed calibration circuitry configured to determine time-multiplexed channel-specific parameters for enabled one of the receiver lanes of the receiver circuits as disclosed in Moshe, because the motivation lies in Moshe that the coefficients are configured for each receiver lane for meeting the predefined BER threshold for establishing data signal integrity.
Regarding Claim 11, the claim is directed towards a system which performs the same claim features as the system in claim 4. Therefore claim 11 is rejected as obvious over the combination of Hossain in view of Wolkovitz, and further in view of Moshe as in claim 4.
Regarding Claim 12, the claim is directed towards a system which performs the same claim features as the system in claim 5. Therefore claim 12 is rejected as obvious over the combination of Hossain in view of Wolkovitz, and further in view of Moshe as in claim 5.
Regarding Claim 18, the claim is directed towards a system which performs the same claim features as the system in claim 4. Therefore claim 18 is rejected as obvious over the combination of Hossain in view of Wolkovitz, and further in view of Moshe as in claim 4.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939), as applied to claim 1 above, and further in view of Poplack et al. USP (11,275,598).
Regarding Claim 6, Hossain discloses the system of claim 1, wherein outputs of the receiver circuits comprise the receiver clocks, (see Para’s [0026] i.e., error signals output from the receivers can be in the form of phase error signals of a local CDR for the specific lane & [0029] i.e., receivers indicate errors such as phase offsets, between a local sampling times and the data signals on the communication lines)
and wherein the system further comprises: first time-interleaving circuitry configured to time-interleave the receiver clocks output from the receiver circuits based on a channel select control; (see Figures 1 & 3 & Para’s [0026], [0029] i.e., local clock recovery circuits 51-54 include phase detectors (i.e., “first time-interleaving circuitry”) which output error signals & [0036] i.e., The local error signals produced in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit (i.e., a channel or communication line is selected for providing from each receiver each of the error signals suggests a channel selection at a particular time)).
While Hossain suggests transitions of the channel select control based on each receiver respectively providing the error signal to the global clock recovery circuit (see Figures 1 & 3 & Para’s [0026], [0029], & [0036] i.e., The local error signals produced in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit (i.e., a channel or communication line is selected for providing from each receiver each of the error signals suggests a transition of channel selection at particular times for providing the error signals)), the combination of Hossain in view of Wolkovitz does not disclose the claim feature of and clock domain crossing (CDC) circuitry configured to halt the receiver clocks output from the receiver circuits during transitions of the channel select control. However the claim feature would be rendered obvious in view of Poplack et al. USP (11,275,598).
Poplack discloses clock domain crossing (CDC) circuitry configured to halt the receiver lanes output from receiver circuits during providing output from a selected channel (see Fig. 3A i.e., selected channel 308 & Col. 5 lines 6-35 i.e., The RxFE circuit block 304 may receive incoming data from a corresponding data input lane 308…the macro receiver 310 may provide to the RXPCS 312, a receiver clock signal (i.e., “output”) & lines 35-50 i.e., the switching ASIC 300 may comprise a sequencer for each output lane…The sequence 324 may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes (which may include data input lane 308) corresponding to the data output lane 322 (i.e., halt other receiver lanes)).
(Poplack suggests the sequencer 324 may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes for resolving clock domain crossing issues and results in power savings based on receiving from a subset of the receiver lanes (see Fig. 3A & Col. 5 lines 35-50)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for a receiver which provides the error signal output during a transition of the channel selection control as disclosed in Hossain in view of Wolkovitz to halt the receiver clocks output from the other receiver lanes from providing output by using the clock domain crossing (CDC) circuitry configured to halt the other receiver lanes output during providing output from a selected channel from a receiver lane as disclosed in the teachings of Poplack, because the motivation lies in Poplack that the sequencer may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes for resolving clock domain crossing issues and results in power savings based on receiving from a subset of the receiver lanes.
Regarding Claim 13, the claim is directed towards a method which performs the same claim features as the system in claim 6. Therefore claim 13 is rejected as obvious over the combination of Hossain in view of Wolkovitz, and further in view of Poplack as in claim 6.
Claims 7 and 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939), and further in view of Poplack et al. USP (11,275,598) as applied to claim 6 above, and further in view of De et al. US (2017/0053051).
Regarding Claim 7, Hossain in view of Wolkovitz discloses the system of claim 6, further comprising: second time-interleaving circuitry configured to time-interleave data output from the receiver circuits based on the channel select control; (In light of the applicants specification in Para [0043], the “second time-interleaving circuitry “refers to the time-interleave de-skew circuitry 130 in Fig. 1 (Hossain, see Fig. 3, i.e., local phase adj. 71-74 i.e., “second time-interleaving circuitry” which provide the error signal output to the global clock recovery circuit & Para [0036] i.e., The local error signals produced in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit (i.e., a channel or communication line is selected for providing from each receiver each of the error signals suggests a transition of channel selection at particular times for providing the error signals)), but does not disclose the claim feature and glitch control circuitry configured to halt an output of the second time-interleaving circuitry during the transitions of the channel select control. However the claim feature would be rendered obvious in view of Poplack et al. USP (11,275,598).
In light of the applicants specification, glitch control circuitry configured to halt an output of the second time-interleaving circuitry refers to the clock domain processing crossing (CDC) circuitry 134 which disables the time-interleave de-skew circuitry 130 based on arising glitches (see applicants specification Para [0043]).
Poplack discloses clock domain crossing (CDC) circuitry configured to halt the receiver lanes output from receiver circuits during providing output from a selected channel (see Fig. 3A i.e., selected channel 308 & Col. 5 lines 6-35 i.e., The RxFE circuit block 304 may receive incoming data from a corresponding data input lane 308…the macro receiver 310 may provide to the RXPCS 312, a receiver clock signal (i.e., “output”) & lines 35-50 i.e., the switching ASIC 300 may comprise a sequencer for each output lane…The sequence 324 may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes (which may include data input lane 308) corresponding to the data output lane 322 (i.e., halt other receiver lanes)).
(Poplack suggests the sequencer 324 may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes for resolving clock domain crossing issues and results in power savings based on receiving from a subset of the receiver lanes (see Fig. 3A & Col. 5 lines 35-50)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for a receiver which provides the error signal output during a transition of the channel selection control as disclosed in Hossain in view of Wolkovitz to halt the other local phase adjusters (i.e., “second time-interleaving circuitry”) from the other receiver lanes from providing output by using the clock domain crossing (CDC) circuitry configured to halt the other receiver lanes output during providing output from a selected channel from a receiver lane as disclosed in the teachings of Poplack, because the motivation lies in Poplack that the sequencer may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes for resolving clock domain crossing issues and results in power savings based on receiving from a subset of the receiver lanes.
The combination of Hossain in view of Wolkovitz, and further in view of Poplack does not explicitly disclose glitch control circuitry. However the claim feature would be rendered obvious in view of De et al. US (2017/0053051).
De discloses glitch control circuitry can be a clock domain crossing (CDC) synchronization circuit for glitch detection, (see Para [0010], [0025], [0027], & [0035])
(De suggests the glitch control circuitry detects and prevents the glitch from propagating to the network (see Para’s [0010], [0025], [0027], & [0035])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the clock domain crossing (CDC) circuitry disclosed in Hossain in view of Wolkovitz, and further in view of Poplack to include the glitch control circuitry of the clock domain crossing (CDC) synchronization circuit disclosed in the teachings of De, because the motivation lies in De that the glitch control circuitry detects and prevents the glitch from propagating to the network.
Regarding Claim 14, the claim is directed towards a method which performs the same claim features as the system in claim 7. Therefore claim 14 is rejected as obvious over the combination of Hossain in view of Wolkovitz, further in view of Poplack, and further in view of De as in claim 7.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939) as applied to claim 15 above, and further in view of Kochavi et al. USP (11,909,850).
Regarding Claim 16, Hossain discloses the system of claim 15, including providing outputs to the CDR system and to the second IC device, (see Fig. 3 & Para’s [0035-0036]), the combination of Hossain in view of Wolkovitz does not disclose wherein the first IC device further comprises: multi-stage de-serializer circuitry configured to de-serialize data outputs of the receiver circuits in stages. However the claim feature would be rendered obvious in view of Kochavi et al. USP (11,909,850).
Kovachi discloses wherein a first IC device (see Fig. 2 i.e., 204) further comprises: multi-stage de-serializer circuitry (see Fig. 2 i.e., each receiver per lane includes a de-serializer circuit) configured to de-serialize data outputs of the receiver circuits in stages (see Fig. 2 & Col. 9 lines 55-60 i.e., Each receiver Rx may include an I/O interface to receive the serialized data on the respective lane from a respective transmitter Tx on the other die, and a de-serializer circuit to convert the serial data into parallel data (i.e., reception and de-serializing by converting the serialized data into parallel data for output may represent “stages”)).
(Kovachi suggests each receiver RX may include a de-serializer circuit to convert the serial data into parallel data for appropriately converting the serialized data for output (see Fig. 2 & Col. 9 lines 55-60)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for each of the per lane receivers which provide outputs to the CDR system and to the second IC device as disclosed in Hossain in view of Wolkovitz to each include the de-serializer circuitry of the per lane receivers configured to de-serialize data outputs of the receiver circuits in stages as disclosed in the teachings of Kovachi which results in multi-stage de-serializer circuitry providing de-serialized outputs to the CRD system and second IC device, because the motivation lies in Kovachi that each receiver RX may include a de-serializer circuit to convert the serial data into parallel data for appropriately converting the serialized data for output.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939), and further in view of Kochavi et al. USP (11,909,850) as applied to claim 16 above, and further in view of Kozaki et al. US (2010/0232798).
Regarding 17, the combination of Hossain in view of Wolkovitz, and further in view of Kochavi discloses the system of claim 16, wherein the first and second IC devices comprise respective first and second chip-to-chip interface circuitry configured to interface with one another over a link, (Hossain, see Fig. 3 i.e., line interface 68-69 between global clock recovery circuit (i.e., CDR) and remaining receiver circuits 61-64 of integrated circuit 60)
wherein the first and second chip-to-chip interface circuitry comprise respective parallel physical layer circuitry, (Hossain, see Fig. 3 Para’s [0035-0036] i.e., the second integrated circuit 60 includes a receiver on each one of the communication lines 11-14 & [0037-0039] i.e., global clock recovery circuit (upper portion 98)), but does not disclose the claim feature of the first and second chips configured to interface with one another over a fiber optic link. However the claim feature would be rendered obvious in view of Kozaki et al. US (2010/0232798).
Kozaki discloses a plurality of receivers as slave stations (see Fig. 1 i.e., ONU’s) and a clock recover circuit as a master station (see Fig. 1 i.e., CDR 12 of OLT 1) configured to interface with one another over a fiber optic link, (see Fig. 1 i.e., optical fiber link 3 & Para’s [0042-0043]).
(Kozaki suggests the master station communicates with the slave stations over fiber optic link for managing the slave stations and performing clock data recovery, (see Fig. 1 & Para’s [0042-0044])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the first and second chip-to-chip interface circuitry including the remaining receiver circuits which may be slave stations and the reference receiver circuit which may be a master station configured to interface with one another over a link as disclosed in Hossain in view of Wolkovitz, and further in view of Kochavi to be performed over a fiber optic link as disclosed in the teachings of Kozaki who discloses a plurality of receivers as slave stations and a clock recover circuit as a master station configured to interface with one another over a fiber optic link, because the motivation lies in Kozaki that the master station communicates with the slave stations over fiber optic link for managing the slave stations and performing clock data recovery.
Conclusion
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/ADNAN BAIG/Primary Examiner, Art Unit 2461