DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-8, 10-18, and 20 have been considered but are moot in view of the new ground(s) of rejection set forth.
Applicant's arguments filed June 19 2026 have been fully considered but they are not persuasive. In regards to the applicants arguments regarding amended claim 1, while a new ground(s) of rejection has been set forth, the examiner respectfully disagrees with certain arguments presented by the applicant. For example, the applicant the teachings of Hossain does not teach the claim feature of the de-multiplexer configured to de-multiplex multiple signals received from a transmitter. However a new ground(s) of rejection has been set forth for the claim feature. Therefore arguments presented with respect to the claim feature are considered moot.
In regards to the applicants arguments that Hossain does not teach or suggest selecting one of the multiple receivers as a reference receiver, the applicant is arguing the teachings of Hossain individually for not disclosing the claim feature. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
For example, based on the combined teachings of the references of Hossain (Of Record) in view of Wolkovitz (Of Record), the teachings of Wolkovitz was relied upon for selecting one of the multiple receivers as a reference receiver such as the clock data recovery circuit (CDR) in lane 3 (Wolkovitz, see Fig. 1 & Col. 4 line 39-57). As explained in the office action, it would be obvious to one of ordinary skill in the art for the global clock recovery circuit (i.e., “reference receiver circuit”) as disclosed in Hossain to be included in one of the receiver circuits as a reference receiver circuit based on the teachings of Wolkovitz who discloses a clock data recovery circuit (CDR) is included in a reference receiver circuit of a plurality of receiver circuits. Therefore the combined teachings of Hossain in view of Wolkovitz discloses selecting one of the multiple receivers as a reference receiver.
In regards to the applicants arguments that Hossain also does not teach or suggest a CDR circuit that controls a phase of a reference clock based on outputs of the reference receiver circuit, the examiner respectfully disagrees as the combined teachings of Hossain in view of Wolkovitz discloses the claim feature. For example Hossain discloses a CDR circuit (see Fig. 3 i.e., global clock recovery circuit including Frequency tracker 65 & Phase adjuster 72) that controls a phase of reference clock (Hossain, see Fig. 3 i.e., R-CK on line 69) based on outputs of the receiver circuits (& Para [0036] i.e., The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66).
As previously explained based on the combination of Hossain in view of Wolkovitz when the global clock recovery circuit of Hossain including Frequency tracker 65 & Phase adjuster 72 (Hossain, Fig. 3) which controls the phase adjuster 66 (i.e., controls a phase of a reference clock) which is based on outputs (i.e., local error signals) of all of the receiver circuits (Hossain, see Para [0036]), is included in one of the receiver circuits as a reference receiver circuit based on the combined teachings of Hossain in view of Wolkovitz, results in controlling the phase of the reference clock also based on an output of the reference receiver circuit since the receiver circuits include the reference receiver circuit. Therefore the combination of Hossain in view of Wolkovitz results in disclosing the claim feature of a CDR circuit that controls a phase of a reference clock based on outputs of the reference receiver circuit.
In regards to the applicants arguments that Hossain also does not teach or suggest time-multiplexed de-skew circuit configured to determine the phase offsets for the remaining ones of the receiver circuits based on time-multiplexed outputs of the respective remaining receiver circuits, the examiner respectfully disagrees. For example Hossain discloses a time-multiplexed de-skew circuit (see Fig. 3 i.e., local phase adjuster 71-74) configured to determine the phase offsets for the remaining ones of the receiver circuits (see Fig. 3 i.e., receivers 61-64) based on time-multiplexed outputs of the respective remaining receiver circuits, (see Fig. 3 & Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74 & [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66 & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators).
In regards to the applicants arguments that Hossain also does not teach or suggest that each receiver includes a de-skew circuit that generates a respective receiver clock (i.e., sampling clock) based on the reference clock and the respective phase offset, a new ground(s) of rejection has been set forth for the claim feature. Therefore arguments with respect to the claim feature are considered moot.
In regards to the applicants argument regarding the office action conceding that “Hossain does not disclose the global clock recovery circuit s included in a reference receiver circuit of the receiver circuits and the claim feature of wherein the receiver circuits comprise a reference receiver circuit” (i.e., Pg. 7 of the non-final office action, 2nd paragraph), in which the office action applied the teachings of Wolkovitz for disclosing “a clock data recovery circuit (CDR) is included in a reference receiver circuit of receiver circuits”, the applicant states that amended claim 1 does not recite that the reference receiver circuit includes a global clock recovery circuit, and Wolkovitz is thus immaterial to amended claim 1. However the examiner respectfully disagrees, as the global clock recovery circuit as disclosed in Hossain was interpreted in the non-final office action as a reference receiver circuit. However the claim requires that the reference receiver circuit is selected as or is part of one of the receiver circuits, in which such feature of including the global clock recovery circuit (i.e., “reference receiver circuit”) of Hossain in one of the receiver circuits would be rendered obvious in view of the teachings of Wolkovitz who discloses a clock data recovery circuit (CDR) is included as a reference receiver circuit in one of a plurality of receiver circuits (Wolkovitz, see Fig. 3 i.e., Clock-Data-Recovery circuit (CDR) 116 (i.e., “reference receiver circuit”) which samples data on lane 3 among remaining receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57). Therefore the combined teachings of Hossain in view of Wolkovitz results in the reference receiver circuit such as the global clock recovery circuit to be included in one of the receiver circuits based on the combination of Hossain in view of Wolkovitz. For the reasons explained the prior art references of Hossain in view of Wolkovitz is maintained for rejection of amended claim 1 although a new ground(s) of rejection has been set forth.
The same response to arguments for amended claim 1 also apply to amended independent claims 8 and 15 which recite features similar to claim 1. The dependent claims remain rejected over the prior art based on their dependence to the independent claims 1, 8, and 15.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8 and 10-14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the reference receiver circuit" in lines 4-5 of the claim. There is insufficient antecedent basis for this limitation in the claim. The dependent claims 10-14 are also rejected under 35 U.S.C. 112(b) based on their dependence to independent claim 8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939), further in view of Chiang et al. US (2009/0161247), and further in view of Hsueh US (2012/0063291).
Regarding Claim 1, Hossain discloses a system (see Fig. 3), comprising: multiple signals received from a transmitter (see Fig. 3 & Para [0035] i.e., The first integrated circuit 10 transmits respective data signals (“S1” to “S4”), each of which include a corresponding data stream D1 to D4 on the communication lines 11-14 to the second integrated circuit 60)
a clock source configured to provide a reference clock (see Fig. 3 i.e., R-CK & Para’s [0027-0029] i.e., reference clock, [0031], & [0036-0037] i.e., each local phase adjuster 71-74 receives the global recovered clock across line 69 from global clock recovery circuit)
a plurality of receiver circuits (see Fig. 3 i.e., receivers including samplers 61-64 on each communication line 11-14), each comprising a circuit (see Fig. 3 i.e., local phase adjusters 71-74) configured to generate a respective receiver clock based on the reference clock and a respective phase offset, (see Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74, [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine and apply “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69 (i.e., “reference clock”). The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66, [0038] i.e., digital phase interpolator, which produces the local recovered clock used for sampling data, & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments (i.e., “phase offsets”) using per lane, digital phase interpolators)
wherein each of the receivers is configured to configured to sample a respective one of the signals based on respective receiver clocks, (see Fig. 3 & Para’s [0025], [0035] i.e., while the per-lane, local clock recovery circuits, [0036] i.e., the second integrated circuit 60 includes a receiver on each one of the communication lines 11-14. These receivers include corresponding samplers 41-44, using local recovered clocks, and producing the corresponding data streams “D1” to “D4”. & [0038] i.e., digital phase interpolator, which produces the local recovered clock used for sampling data)
a reference receiver circuit (see Fig. 3 i.e., global clock recovery circuit including frequency tracker and phase adjuster & Para [0036])
wherein the reference receiver circuit is configured to use the reference clock as the respective receiver clock, (see Fig. 3 i.e., R-CK (i.e., “reference clock”) & Para’s [0025] i.e., A global clock recovery circuit 45 produces a global recovered clock R-CK (i.e., “reference clock”) shared by all lanes to produce a respective, local recovered clock to control local sampling times at the respective samplers 41-44, [0036] i.e., Each local phase adjuster 71-74 receives the global recovered clock (i.e., “reference clock”) across line 69, [0037] i.e., global recovered clock R-CK is provided to each of the local clock recovery circuits & [0040])
a clock and data recovery (CDR) circuit (see Fig. 3 i.e., global clock recovery circuit including Frequency tracker 65 & Phase adjuster 72) configured to control a phase of the reference clock based on outputs of the reference receiver circuit; (see Para [0036] i.e., The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66)
a time-multiplexed de-skew circuit (see Fig. 3 i.e., local phase adjuster 71-74) configured to compute the phase offsets for the remaining ones of the receiver circuits (see Fig. 3 i.e., receivers 61-64) based on time-multiplexed outputs of the respective remaining receiver circuits, (see Fig. 3 & Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74 & [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66 & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators)
While Hossain discloses a reference receiver circuit such as the global clock recovery circuit which includes the reference clock provided to the remaining receiver circuits for performing the phase-shift based on determined phase offsets (see Fig. 3 & Para’s [0035-0036] & [0040-0041]), Hossain does not disclose the global clock recovery circuit is included in one of the receiver circuits as the reference receiver circuit and the claim feature of reference channel selection circuitry configured to select one of the receiver circuits as the reference receiver circuit. However the claim features would be rendered obvious in view of Wolkovitz et al. USP (11,031,939).
Wolkovitz discloses a clock data recovery circuit (CDR) is included as a reference receiver circuit in one of a plurality of receiver circuits (see Fig. 3 i.e., Clock-Data-Recovery circuit (CDR) 116 (i.e., “reference receiver circuit”) which samples data on lane 3 among remaining receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57 i.e., Clock-Data-Recovery circuit (CDR) 116 that is coupled to lane 3, and samplers 118, which are coupled to lanes 1, 2, 4, and 5…the CDR is further configured to output phase correction signaling, which indicates phase corrections to the Receiver Clock that are needed to properly sample the data…the samplers receive phase correction signaling from the CDR, and sample data from the respective lanes)
wherein the receiver circuits comprise a reference receiver circuit (see Fig. 3 i.e., CDR 116 coupled to lane 3 may be a reference receiver circuit among the receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57)
reference channel selection circuitry configured to select one of the receiver circuits as the reference receiver circuit (see Fig. 1 i.e., one of the receiver circuits associated with each lane will be selected as a CDR (i.e., “reference receiver circuit”) & Col. 3 lines 49-56 i.e., the CDRs can be configured e.g., by software, strap-pin or mask-options (i.e., configuring the CDR by software includes execution of the software by hardware or a processor which may be “reference channel selection circuitry”), to function as samplers that receive phase correction signaling from neighboring CDRs and modify the sampling phase accordingly (and optionally, propagate the phase correction signaling to further neighboring CDRs that are configured to function as samplers, Col. 4 lines 39-66 i.e., a single CDR circuit is implemented on one of the lanes, Col. 7 lines 40-41 i.e., Configuring of the CDR may be done by software, Col. 8 lines 23-25 & Col. 9 lines 3-13)
(Wolkovitz suggests the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase, (see Col. 4 line 39-57)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the global clock recovery circuit (i.e., “reference receiver circuit”) which includes the reference clock that is provided to the remaining receiver circuits for performing the phase-shift based on the determined phase offsets as disclosed in Hossain to be included in one of the receiver circuits as a reference receiver circuit based on the teachings of Wolkovitz who discloses a clock data recovery circuit (CDR) is included in a reference receiver circuit of a plurality of receiver circuits, which results in controlling the phase of the reference clock based on outputs of the reference receiver circuit, because the motivation lies in Wolkovitz that the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase.
While Hossain discloses the data signals S1 to S4 received and sampled by the receivers of the second integrated circuit 60 based on their respective receiver clocks which is performed using multilane SERDES protocol (see Fig. 3 & Para’s [0024] i.e., SERDES channels, [0035-0036], [0038] i.e., local recovered clock used for sampling the data, & [0062] i.e., multi-lane SERDES application), the combination of Hossain in view of Wolkovitz does not disclose the claim features of a de-multiplexer configured to de-multiplex multiple signals received from a transmitter such and that the receivers sample a respective one of the de-multiplexed signals. However the claim feature would be rendered obvious in view of Chiang et al. US (2009/0161247).
Chiang discloses a de-multiplexer (see Fig. 1 i.e., demultiplexer 110) configured to de-multiplex multiple signals received from a transmitter according to SERDES protocol (see Para’s [0006] i.e., SERDES Framer Interface Level 5 “SFI-5” protocol & [0030-0033] i.e., demultiplexer that is complaint with the SFI-5 specification. The demultiplexer 110 comprises an input 115 on which a signal, such as a client signal, is received and a plurality of output channels om which the signal is distributed comprising channel (0) 120, channel (1) 125 through channel (N) 130…the plurality of output channels after they have been received at a receiving electrical component. This receiving component may be devices such as a framer…or other such devices within the relevant signal path).
(Chiang suggests the demultiplexer demultiplexes the received input signal for distributing the signal on a plurality of output channels in order for a respective receiver on a signal path to receive the signal and for effectively managing the skew on the output channels for properly processing the channels, (see Para’s [0030-0033], [0035], & [0039])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the multiple signals received by the receivers of the integrated circuit 60 over the communication channels or lanes according to the SERDES protocol as disclosed in Hossain in view of Wolkovitz to be received using a demultiplexer to demultiplex the multiple signals such as the demultiplexer disclosed in Chiang who discloses a de-multiplexer configured to de-multiplex multiple signals received from a transmitter according to SERDES protocol, which results in the receivers sampling a respective one of the de-multiplexed signals based on the receiver clocks, because the motivation lies in Chiang that the demultiplexer demultiplexes the received input signal for distributing the signal on a plurality of output channels in order for a respective receiver on a signal path to receive the signal and for effectively managing the skew on the output channels for properly processing the channels.
While Hossain discloses each of the plurality of receiver circuits each comprise a phase interpolator circuit configured to generate the respective receiver clock (Hossain, see Fig. 3 i.e., local phase adjusters 71-74 & Para’s [0035-0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74, such as digital phase interpolators), the combination of Hossain in view of Wolkovitz, and further in view of Chiang does not disclose the plurality of receiver circuits each comprise a de-skew circuit. However the claim feature would be rendered obvious in view of Hsueh US (2012/0063291).
Hsueh discloses a de-skew circuit of a receiver may be for example a phase interpolator (see Fig. 2 i.e., receiver circuitry 56 & Para [0036])
(Hsueh suggests the de-skew circuit such as the phase interpolator of the receiver circuit, may be required to optimize the sampling phase for the receiver circuitry 56 and data capture circuitry 58 (see Fig. 2 & Para [0036])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for each of the phase interpolators of each of the plurality of receiver circuits configured to generate the respective receiver clock as disclosed in Hossain in view of Wolkovitz, and further in view of Chiang to be implemented as a de-skew circuit based on the teachings of Hsueh who discloses a de-skew circuit of a receiver may be for example a phase interpolator, because the motivation lies in Hsueh that the de-skew circuit such as the phase interpolator of the receiver circuit, may be required to optimize the sampling phase for the receiver circuitry 56 and data capture circuitry 58.
Regarding Claim 3, Hossain discloses the system of claim 1, wherein the time-multiplexed de-skew circuitry (see Fig. 3 i.e., local phase adjuster 71-74) is further configured to determine the time-multiplexed phase offsets for enabled ones of the remaining receiver circuits, (see Fig. 3 i.e., receivers 61-64 which performs phase adjustment may be enabled ones of the remaining receiver circuits & Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74 & [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66 & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators)
Regarding Claim 15, Hossain discloses a system (see Fig. 3), comprising: a first integrated circuit (IC) device (see Fig. 3 i.e., integrated circuit 60 & Para [0036]) comprising:
multiple signals received from a transmitter (see Fig. 3 & Para [0035] i.e., The first integrated circuit 10 transmits respective data signals (“S1” to “S4”), each of which include a corresponding data stream D1 to D4 on the communication lines 11-14 to the second integrated circuit 60)
a clock source configured to provide a reference clock (see Fig. 3 i.e., R-CK & Para’s [0027-0029] i.e., reference clock, [0031], & [0036-0037] i.e., each local phase adjuster 71-74 receives the global recovered clock across line 69 from global clock recovery circuit)
a plurality of receiver circuits (see Fig. 3 i.e., receivers including samplers 61-64 on each communication line 11-14), each comprising a circuit (see Fig. 3 i.e., local phase adjusters 71-74) configured to generate a respective receiver clock based on the reference clock and a respective phase offset, (see Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74, [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine and apply “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69 (i.e., “reference clock”). The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66, [0038] i.e., digital phase interpolator, which produces the local recovered clock used for sampling data, & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments (i.e., “phase offsets”) using per lane, digital phase interpolators)
wherein each of the receivers is configured to configured to sample a respective one of the signals based on respective receiver clocks, (see Fig. 3 & Para’s [0025], [0035] i.e., while the per-lane, local clock recovery circuits, [0036] i.e., the second integrated circuit 60 includes a receiver on each one of the communication lines 11-14. These receivers include corresponding samplers 41-44, using local recovered clocks, and producing the corresponding data streams “D1” to “D4”. & [0038] i.e., digital phase interpolator, which produces the local recovered clock used for sampling data)
a reference receiver circuit (see Fig. 3 i.e., global clock recovery circuit including frequency tracker and phase adjuster & Para [0036])
wherein the reference receiver circuit is configured to use the reference clock as the respective receiver clock, (see Fig. 3 i.e., R-CK (i.e., “reference clock”) & Para’s [0025] i.e., A global clock recovery circuit 45 produces a global recovered clock R-CK (i.e., “reference clock”) shared by all lanes to produce a respective, local recovered clock to control local sampling times at the respective samplers 41-44, [0036] i.e., Each local phase adjuster 71-74 receives the global recovered clock (i.e., “reference clock”) across line 69, [0037] i.e., global recovered clock R-CK is provided to each of the local clock recovery circuits & [0040])
a clock and data recovery (CDR) circuit (see Fig. 3 i.e., global clock recovery circuit including Frequency tracker 65 & Phase adjuster 72) configured to control a phase of the reference clock based on outputs of the reference receiver circuit; (see Para [0036] i.e., The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66)
a time-multiplexed de-skew circuit (see Fig. 3 i.e., local phase adjuster 71-74) configured to compute the phase offsets for the remaining ones of the receiver circuits (see Fig. 3 i.e., receivers 61-64) based on time-multiplexed outputs of the respective remaining receiver circuits, (see Fig. 3 & Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74 & [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66 & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators)
and a second IC device configured to receive outputs of the receiver circuits, (see Fig. 3 i.e., global clock recovery circuit may be a second IC device (i.e., Fig. 4, 98) which receives error signal output from receivers 61-64 & Para’s [0037-0039] & [0042-0043])
While Hossain discloses a reference receiver circuit such as the global clock recovery circuit which includes the reference clock provided to the remaining receiver circuits for performing the phase-shift based on determined phase offsets (see Fig. 3 & Para’s [0035-0036] & [0040-0041]), Hossain does not disclose the global clock recovery circuit is included in one of the receiver circuits as the reference receiver circuit and the claim feature of reference channel selection circuitry configured to select one of the receiver circuits as the reference receiver circuit. However the claim features would be rendered obvious in view of Wolkovitz et al. USP (11,031,939).
Wolkovitz discloses a clock data recovery circuit (CDR) is included as a reference receiver circuit in one of a plurality of receiver circuits (see Fig. 3 i.e., Clock-Data-Recovery circuit (CDR) 116 (i.e., “reference receiver circuit”) which samples data on lane 3 among remaining receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57 i.e., Clock-Data-Recovery circuit (CDR) 116 that is coupled to lane 3, and samplers 118, which are coupled to lanes 1, 2, 4, and 5…the CDR is further configured to output phase correction signaling, which indicates phase corrections to the Receiver Clock that are needed to properly sample the data…the samplers receive phase correction signaling from the CDR, and sample data from the respective lanes)
wherein the receiver circuits comprise a reference receiver circuit (see Fig. 3 i.e., CDR 116 coupled to lane 3 may be a reference receiver circuit among the receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57)
reference channel selection circuitry configured to select one of the receiver circuits as the reference receiver circuit (see Fig. 1 i.e., one of the receiver circuits associated with each lane will be selected as a CDR (i.e., “reference receiver circuit”) & Col. 3 lines 49-56 i.e., the CDRs can be configured e.g., by software, strap-pin or mask-options (i.e., configuring the CDR by software includes execution of the software by hardware or a processor which may be “reference channel selection circuitry”), to function as samplers that receive phase correction signaling from neighboring CDRs and modify the sampling phase accordingly (and optionally, propagate the phase correction signaling to further neighboring CDRs that are configured to function as samplers, Col. 4 lines 39-66 i.e., a single CDR circuit is implemented on one of the lanes, Col. 7 lines 40-41 i.e., Configuring of the CDR may be done by software, Col. 8 lines 23-25 & Col. 9 lines 3-13)
(Wolkovitz suggests the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase, (see Col. 4 line 39-57)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the global clock recovery circuit (i.e., “reference receiver circuit”) which includes the reference clock that is provided to the remaining receiver circuits for performing the phase-shift based on the determined phase offsets as disclosed in Hossain to be included in one of the receiver circuits as a reference receiver circuit based on the teachings of Wolkovitz who discloses a clock data recovery circuit (CDR) is included in a reference receiver circuit of a plurality of receiver circuits, which results in controlling the phase of the reference clock based on outputs of the reference receiver circuit, because the motivation lies in Wolkovitz that the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase.
While Hossain discloses the data signals S1 to S4 received and sampled by the receivers of the second integrated circuit 60 based on their respective receiver clocks which is performed using multilane SERDES protocol (see Fig. 3 & Para’s [0024] i.e., SERDES channels, [0035-0036], [0038] i.e., local recovered clock used for sampling the data, & [0062] i.e., multi-lane SERDES application), the combination of Hossain in view of Wolkovitz does not disclose the claim features of a de-multiplexer configured to de-multiplex multiple signals received from a transmitter such and that the receivers sample a respective one of the de-multiplexed signals. However the claim feature would be rendered obvious in view of Chiang et al. US (2009/0161247).
Chiang discloses a de-multiplexer (see Fig. 1 i.e., demultiplexer 110) configured to de-multiplex multiple signals received from a transmitter according to SERDES protocol (see Para’s [0006] i.e., SERDES Framer Interface Level 5 “SFI-5” protocol & [0030-0033] i.e., demultiplexer that is complaint with the SFI-5 specification. The demultiplexer 110 comprises an input 115 on which a signal, such as a client signal, is received and a plurality of output channels om which the signal is distributed comprising channel (0) 120, channel (1) 125 through channel (N) 130…the plurality of output channels after they have been received at a receiving electrical component. This receiving component may be devices such as a framer…or other such devices within the relevant signal path).
(Chiang suggests the demultiplexer demultiplexes the received input signal for distributing the signal on a plurality of output channels in order for a respective receiver on a signal path to receive the signal and for effectively managing the skew on the output channels for properly processing the channels, (see Para’s [0030-0033], [0035], & [0039])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the multiple signals received by the receivers of the integrated circuit 60 over the communication channels or lanes according to the SERDES protocol as disclosed in Hossain in view of Wolkovitz to be received using a demultiplexer to demultiplex the multiple signals such as the demultiplexer disclosed in Chiang who discloses a de-multiplexer configured to de-multiplex multiple signals received from a transmitter according to SERDES protocol, which results in the receivers sampling a respective one of the de-multiplexed signals based on the receiver clocks, because the motivation lies in Chiang that the demultiplexer demultiplexes the received input signal for distributing the signal on a plurality of output channels in order for a respective receiver on a signal path to receive the signal and for effectively managing the skew on the output channels for properly processing the channels.
While Hossain discloses each of the plurality of receiver circuits each comprise a phase interpolator circuit configured to generate the respective receiver clock (Hossain, see Fig. 3 i.e., local phase adjusters 71-74 & Para’s [0035-0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74, such as digital phase interpolators), the combination of Hossain in view of Wolkovitz, and further in view of Chiang does not disclose the plurality of receiver circuits each comprise a de-skew circuit. However the claim feature would be rendered obvious in view of Hsueh US (2012/0063291).
Hsueh discloses a de-skew circuit of a receiver may be for example a phase interpolator (see Fig. 2 i.e., receiver circuitry 56 & Para [0036])
(Hsueh suggests the de-skew circuit such as the phase interpolator of the receiver circuit, may be required to optimize the sampling phase for the receiver circuitry 56 and data capture circuitry 58 (see Fig. 2 & Para [0036])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for each of the phase interpolators of each of the plurality of receiver circuits configured to generate the respective receiver clock as disclosed in Hossain in view of Wolkovitz, and further in view of Chiang to be implemented as a de-skew circuit based on the teachings of Hsueh who discloses a de-skew circuit of a receiver may be for example a phase interpolator, because the motivation lies in Hsueh that the de-skew circuit such as the phase interpolator of the receiver circuit, may be required to optimize the sampling phase for the receiver circuitry 56 and data capture circuitry 58.
Regarding Claim 20, the claim is directed towards a system which performs the same claim features as the system of claim 3. Therefore claim 20 is rejected as obvious over the combination of Hossain in view of Wolkovitz, further in view of Chiang, and further in view of Hsueh as in claim 3.
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939), and further in view of Chiang et al. US (2009/0161247).
Regarding Claim 8, Hossain discloses a method comprising: multiple signals received from a transmitter (see Fig. 3 & Para [0035] i.e., The first integrated circuit 10 transmits respective data signals (“S1” to “S4”), each of which include a corresponding data stream D1 to D4 on the communication lines 11-14 to the second integrated circuit 60)
multiple receivers (see Fig. 3 i.e., receivers including samplers 61-64 on each communication line 11-14 & Para [0036] i.e., receiver on each one of the communication lines 11-14)
A reference receiver circuit (see Fig. 3 i.e., global clock recovery circuit including frequency tracker and phase adjuster & Para [0036])
Controlling (see Fig. 3 i.e., global clock recovery circuit including Frequency tracker 65 & Phase adjuster 72) a frequency of a reference clock based on outputs of the reference receiver circuit (see Fig. 3 i.e., R-CK & Para’s [0025] i.e., A global clock recovery circuit 45 produces a global recovered clock R-CK (i.e., “reference clock”) shared by all lanes to produce a respective, local recovered clock to control local sampling times at the respective samplers 41-44, [0036] i.e., The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66, [0037] i.e., global recovered clock R-CK is provided to each of the local clock recovery circuits, & [0040])
computing (see Fig. 3 i.e., local phase adjuster 71-74) phase offsets for remaining ones of the receiver circuits (see Fig. 3 i.e., receivers 61-64) based on time-multiplexed outputs of the respective remaining receiver circuits, (see Fig. 3 & Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74 & [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66 & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators)
generating a receiver clock, by each of the remaining receiver circuits, based on the reference clock and the respective phase offsets, (see Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74, [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine and apply “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69 (i.e., “reference clock”). The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66, [0038] i.e., digital phase interpolator, which produces the local recovered clock used for sampling data, & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments (i.e., “phase offsets”) using per lane, digital phase interpolators)
sampling remaining ones of the signals by respective ones of the remaining receiver circuits, based on the respective receiver clocks, (see Fig. 3 & Para’s [0025] i.e., A global clock recovery circuit 45 produces a global recovered clock R-CK shared by all lanes to produce a respective, local recovered clock to control local sampling times at the respective samplers 41-44, [0035] i.e., while the per-lane, local clock recovery circuits, [0036] i.e., the second integrated circuit 60 includes a receiver on each one of the communication lines 11-14. These receivers include corresponding samplers 41-44, using local recovered clocks, and producing the corresponding data streams “D1” to “D4”. & [0038] i.e., digital phase interpolator, which produces the local recovered clock used for sampling data)
While Hossain discloses a reference receiver circuit such as the global clock recovery circuit which includes the reference clock provided to the remaining receiver circuits for performing the phase-shift based on determined phase offsets (see Fig. 3 & Para’s [0035-0036] & [0040-0041]), Hossain does not disclose the global clock recovery circuit is included in one of the receiver circuits as the reference receiver circuit and the claim features of selecting one of multiple receivers as a reference receiver and sampling a first one of the signals by the reference receiver circuit based on the reference clock. However the claim features would be rendered obvious in view of Wolkovitz et al. USP (11,031,939).
Wolkovitz discloses a clock data recovery circuit (CDR) is included as a reference receiver circuit in one of a plurality of receiver circuits (see Fig. 3 i.e., Clock-Data-Recovery circuit (CDR) 116 (i.e., “reference receiver circuit”) which samples data on lane 3 among remaining receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57 i.e., Clock-Data-Recovery circuit (CDR) 116 that is coupled to lane 3, and samplers 118, which are coupled to lanes 1, 2, 4, and 5…the CDR is further configured to output phase correction signaling, which indicates phase corrections to the Receiver Clock that are needed to properly sample the data…the samplers receive phase correction signaling from the CDR, and sample data from the respective lanes)
Selecting one of multiple receivers as a reference receiver (see Fig. 3 i.e., CDR 116 coupled to lane 3 may be a reference receiver circuit among the receiver circuits 118 on lanes 1-2 and 4-5 & Col. 4 line 39-57)
and sampling a first one of the signals by the reference receiver circuit based on the reference clock (see Fig. 3 i.e., CDR 116 coupled to lane 3 may sample signals & Col. 4 line 36-51 i.e., CDR 116 is configured to restore the embedded clock and to sample the data from lane 3)
(Wolkovitz suggests the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase, (see Col. 4 line 39-57)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the global clock recovery circuit (i.e., “reference receiver circuit”) which includes the reference clock that is provided to the remaining receiver circuits for performing the phase-shift based on the determined phase offsets as disclosed in Hossain to be included in one of the receiver circuits as a reference receiver circuit based on the teachings of Wolkovitz who discloses a clock data recovery circuit (CDR) is included in a reference receiver circuit of a plurality of receiver circuits, which results in controlling the phase of the reference clock based on outputs of the reference receiver circuit, because the motivation lies in Wolkovitz that the clock data recovery circuit (CDR) outputs phase correction signaling which indicates phase corrections to the remaining receiver circuits in order for the receivers to properly sample data from the respective lanes according to the corrected or adjusted phase.
While Hossain discloses the data signals S1 to S4 received and sampled by the receivers of the second integrated circuit 60 based on their respective receiver clocks which is performed using multilane SERDES protocol (see Fig. 3 & Para’s [0024] i.e., SERDES channels, [0035-0036], [0038] i.e., local recovered clock used for sampling the data, & [0062] i.e., multi-lane SERDES application), the combination of Hossain in view of Wolkovitz does not disclose the claim features of a de-multiplexer configured to de-multiplex multiple signals received from a transmitter such that the receivers sample a respective one of the de-multiplexed signals. However the claim feature would be rendered obvious in view of Chiang et al. US (2009/0161247).
Chiang discloses a de-multiplexer (see Fig. 1 i.e., demultiplexer 110) configured to de-multiplex multiple signals received from a transmitter according to SERDES protocol (see Para’s [0006] i.e., SERDES Framer Interface Level 5 “SFI-5” protocol & [0030-0033] i.e., demultiplexer that is complaint with the SFI-5 specification. The demultiplexer 110 comprises an input 115 on which a signal, such as a client signal, is received and a plurality of output channels om which the signal is distributed comprising channel (0) 120, channel (1) 125 through channel (N) 130…the plurality of output channels after they have been received at a receiving electrical component. This receiving component may be devices such as a framer…or other such devices within the relevant signal path).
(Chiang suggests the demultiplexer demultiplexes the received input signal for distributing the signal on a plurality of output channels in order for a respective receiver on a signal path to receive the signal and for effectively managing the skew on the output channels for properly processing the channels, (see Para’s [0030-0033], [0035], & [0039])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the multiple signals received by the receivers of the integrated circuit 60 over the communication channels or lanes according to the SERDES protocol as disclosed in Hossain in view of Wolkovitz to be received using a demultiplexer to demultiplex the multiple signals such as the demultiplexer disclosed in Chiang who discloses a de-multiplexer configured to de-multiplex multiple signals received from a transmitter according to SERDES protocol, which results in the receivers sampling a respective one of the de-multiplexed signals based on their respective receiver clocks, because the motivation lies in Chiang that the demultiplexer demultiplexes the received input signal for distributing the signal on a plurality of output channels in order for a respective receiver on a signal path to receive the signal and for effectively managing the skew on the output channels for properly processing the channels.
Regarding Claim 10, Hossain discloses the method of claim 8, wherein the computing the phase offsets comprises: computing the phase offsets for enabled ones of the remaining receiver circuits, (see Fig. 3 i.e., receivers 61-64 which performs phase adjustment may be enabled ones of the remaining receiver circuits & Para’s [0035] i.e., while the per-lane, local clock recovery circuits include local phase adjusters 71-74 & [0036] i.e., The local recovered clocks are produced by local phase adjusters 71-74 (i.e., phase adjusters 71-74 determine “phase offsets” based on received R-CK 69 as input in Fig. 3), such as digital phase interpolators…Each local phase adjuster 71-74 receives the global recovered clock across line 69. The global clock recovery circuity includes a combination of a frequency tracker 65 and a phase adjuster 66. The local error signals produced (i.e., “outputs of the remaining receiver circuits”) in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit, where they are combined and used to control both the frequency tracker 65 and the phase adjuster 66 & [0040-0041] i.e., In this example, the local recovered clock has a frequency that is controlled by the global recovered clock, and its phase is adjusted by the phase increments using per lane, digital phase interpolators)
Claims 4-5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939) further in view of Chiang et al. US (2009/0161247), and further in view of Hsueh US (2012/0063291) as applied to claim 1 above, further in view of Moshe et al. US (2024/0143518), and further in view of Doblar USP (7,822,110).
Regarding Claim 4, the combination of Hossain in view of Wolkovitz, further in view of Chiang, and further in view of Hsueh discloses the system of claim 1, but does not disclose the claim feature of further comprising: time-multiplexed calibration circuitry configured to compute parameters for each of the receiver circuits based on time-multiplexed outputs of the respective receiver circuits. However the claim feature would be rendered obvious in view of Moshe et al. US (2024/0143518).
Moshe discloses time-multiplexed calibration circuitry configured to determine parameters for each of the receiver circuits based on time-multiplexed outputs of the respective receiver circuits (see Para [0060] i.e., For example, each link, lane, and/or channel may include receive filters and transmitter filters with coefficients (i.e., “parameters”) that are configured to establish data signal integrity meeting the predefined BER threshold. These sets of coefficient values may be determined and verified by link state machine 532.1 (i.e., “calibration circuitry”)…For example, coefficient value logic 532.2 may check a register managed by configuration service 542 for previously used coefficient values(i.e., “parameters”) (i.e., previously used coefficient values for meeting the predetermined BER threshold is based on the receiver output of each lane)).
(Moshe suggests the coefficients are configured for each receiver lane for meeting the predefined BER threshold for establishing data signal integrity, (see Para [0060])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the receiver circuits in each of the lanes as disclosed in the system of Hossain in view of Wolkovitz, further in view of Chiang, and further in view of Hsueh to comprise the time-multiplexed calibration circuitry configured to determine the parameters for the receiver lanes based on time-multiplexed outputs of the respective receiver circuits as disclosed in Moshe, because the motivation lies in Moshe that the coefficients are configured for each receiver lane for meeting the predefined BER threshold for establishing data signal integrity.
The combination of Hossain in view of Wolkovitz, further in view of Chiang, further in view of Hsueh, and further in view of Moshe does not disclose the claim feature of including to perform one or more of: compute codes to control times at which the respective receiver circuits sample the respective signals. However the claim feature would be rendered obvious in view of Doblar USP (7,822,110).
Doblar discloses circuitry (see Fig. 1 i.e., service processor 140) configured to compute codes to control times at which the respective receiver circuits sample the respective signals (see Col. 2 lines 10-37 i.e., the service processor is configured to analyze the eye scan to determine various characteristics such as sample time (i.e., “codes”)…and convey the resulting sample time, high voltage threshold, and low voltage threshold to the receiver. The receiver is configured to sample the voltage of the selected lane at the sample time…The resulting sampled data can be used to determine a particular system assembly has sufficient operating electrical performance gain & Col. 5 line 45-Col. 6 lines 1-4).
(Doblar suggests the sample times may be conveyed to the deserializers 122 for sampling data at the sample time for determining that a particular system assembly has sufficient operating electrical performance margin, and to determine optimum phase offset and voltage thresholds to minimize the bit-error rate experienced on a lane under test, (see Col. 2 lines 24-26 & Col. 6 lines 1-4)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the respective receiver circuit sampling times as disclosed in Hossain in view of Wolkovitz, further in view of Chiang, further in view of Hsueh, and further in view of Moshe to control the times at which the receiver circuits sample the respective signals based on compute codes (i.e., “sample times”) configured for the receivers as disclosed in the teachings of Doblar who discloses circuitry configured to compute codes to control times at which respective receiver circuits sample the respective signals, because the motivation lies in Doblar that the sample times may be conveyed to the deserializers 122 for sampling data at the sample time for determining that a particular system assembly has sufficient operating electrical performance margin, and to determine optimum phase offset and voltage thresholds to minimize the bit-error rate experienced on a lane under test.
Regarding Claim 5, the combination of Hossain in view of Wolkovitz, further in view of Chiang, further in view of Hsueh, and further in view of Doblar discloses the system of claim 4, but does not disclose the claim feature of wherein the time-multiplexed calibration circuitry is further configured to compute the parameters for enabled ones of the receiver circuits. However the claim feature would be rendered obvious in view of Moshe et al. US (2024/0143518).
Moshe discloses wherein the time-multiplexed calibration circuitry is further configured to compute parameters for enabled ones of the receiver circuits (see Para [0060] i.e., For example, each link, lane, and/or channel (i.e., enabled receiver circuits on each lane) may include receive filters and transmitter filters with coefficients (i.e., “parameters”) that are configured to establish data signal integrity meeting the predefined BER threshold)
(Moshe suggests the coefficients are configured for each receiver lane for meeting the predefined BER threshold for establishing data signal integrity, (see Para [0060])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the receiver circuits in each of the lanes as disclosed in the system of Hossain in view of Wolkovitz, further in view of Chiang, further in view of Hsueh, and further in view of Doblar to comprise the time-multiplexed calibration circuitry configured to determine the parameters for enabled one of the receiver lanes of the receiver circuits as disclosed in Moshe, because the motivation lies in Moshe that the coefficients are configured for each receiver lane for meeting the predefined BER threshold for establishing data signal integrity.
Regarding Claim 18, the claim is directed towards a system which performs the same claim features as the system in claim 4. Therefore claim 18 is rejected as obvious over the combination of Hossain in view of Wolkovitz, further in view of Chiang, further in view of Hsueh, further in view of Moshe, and further in view of Doblar as in claim 4.
Claims 6 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939), further in view of Chiang et al. US (2009/0161247), and further in view of Hsueh US (2012/0063291) as applied to claim 1 above, and further in view of Poplack et al. USP (11,275,598).
Regarding Claim 6, Hossain discloses the system of claim 1, wherein outputs of the receiver circuits comprise the receiver clocks, (see Para’s [0026] i.e., error signals output from the receivers can be in the form of phase error signals of a local CDR for the specific lane & [0029] i.e., receivers indicate errors such as phase offsets, between a local sampling times and the data signals on the communication lines)
and wherein the system further comprises: first time-interleaving circuitry configured to time-interleave the receiver clocks output from the receiver circuits based on a channel select control; (see Figures 1 & 3 & Para’s [0026], [0029] i.e., local clock recovery circuits 51-54 include phase detectors (i.e., “first time-interleaving circuitry”) which output error signals & [0036] i.e., The local error signals produced in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit (i.e., a channel or communication line is selected for providing from each receiver each of the error signals suggests a channel selection at a particular time)).
While Hossain suggests transitions of the channel select control based on each receiver respectively providing the error signal to the global clock recovery circuit (see Figures 1 & 3 & Para’s [0026], [0029], & [0036] i.e., The local error signals produced in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit (i.e., a channel or communication line is selected for providing from each receiver each of the error signals suggests a transition of channel selection at particular times for providing the error signals)), the references combined does not disclose the claim feature of and clock domain crossing (CDC) circuitry configured to halt the receiver clocks output from the receiver circuits during transitions of the channel select control. However the claim feature would be rendered obvious in view of Poplack et al. USP (11,275,598).
Poplack discloses clock domain crossing (CDC) circuitry configured to halt the receiver lanes output from receiver circuits during providing output from a selected channel (see Fig. 3A i.e., selected channel 308 & Col. 5 lines 6-35 i.e., The RxFE circuit block 304 may receive incoming data from a corresponding data input lane 308…the macro receiver 310 may provide to the RXPCS 312, a receiver clock signal (i.e., “output”) & lines 35-50 i.e., the switching ASIC 300 may comprise a sequencer for each output lane…The sequence 324 may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes (which may include data input lane 308) corresponding to the data output lane 322 (i.e., halt other receiver lanes)).
(Poplack suggests the sequencer 324 may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes for resolving clock domain crossing issues and results in power savings based on receiving from a subset of the receiver lanes (see Fig. 3A & Col. 5 lines 35-50)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for a receiver which provides the error signal output during a transition of the channel selection control as disclosed in Hossain in view of Wolkovitz, further in view of Chiang, and further in view of Hsueh to halt the receiver clocks output from the other receiver lanes from providing output by using the clock domain crossing (CDC) circuitry configured to halt the other receiver lanes output during providing output from a selected channel from a receiver lane as disclosed in the teachings of Poplack, because the motivation lies in Poplack that the sequencer may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes for resolving clock domain crossing issues and results in power savings based on receiving from a subset of the receiver lanes.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939), further in view of Chiang et al. US (2009/0161247), further in view of Hsueh US (2012/0063291), and further in view of Poplack et al. USP (11,275,598) as applied to claim 6 above, and further in view of De et al. US (2017/0053051).
Regarding Claim 7, Hossain discloses the system of claim 6, further comprising: second time-interleaving circuitry configured to time-interleave data output from the receiver circuits based on the channel select control; (In light of the applicants specification in Para [0043], the “second time-interleaving circuitry “refers to the time-interleave de-skew circuitry 130 in Fig. 1 (Hossain, see Fig. 3, i.e., local phase adj. 71-74 i.e., “second time-interleaving circuitry” which provide the error signal output to the global clock recovery circuit & Para [0036] i.e., The local error signals produced in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit (i.e., a channel or communication line is selected for providing from each receiver each of the error signals suggests a transition of channel selection at particular times for providing the error signals)), but the references combined does not disclose the claim feature and glitch control circuitry configured to halt an output of the second time-interleaving circuitry during the transitions of the channel select control. However the claim feature would be rendered obvious in view of Poplack et al. USP (11,275,598).
In light of the applicants specification, glitch control circuitry configured to halt an output of the second time-interleaving circuitry refers to the clock domain processing crossing (CDC) circuitry 134 which disables the time-interleave de-skew circuitry 130 based on arising glitches (see applicants specification Para [0043]).
Poplack discloses clock domain crossing (CDC) circuitry configured to halt the receiver lanes output from receiver circuits during providing output from a selected channel (see Fig. 3A i.e., selected channel 308 & Col. 5 lines 6-35 i.e., The RxFE circuit block 304 may receive incoming data from a corresponding data input lane 308…the macro receiver 310 may provide to the RXPCS 312, a receiver clock signal (i.e., “output”) & lines 35-50 i.e., the switching ASIC 300 may comprise a sequencer for each output lane…The sequence 324 may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes (which may include data input lane 308) corresponding to the data output lane 322 (i.e., halt other receiver lanes)).
(Poplack suggests the sequencer 324 may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes for resolving clock domain crossing issues and results in power savings based on receiving from a subset of the receiver lanes (see Fig. 3A & Col. 5 lines 35-50)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for a receiver which provides the error signal output during a transition of the channel selection control as disclosed in Hossain in view of Wolkovitz, further in view of Chiang, and further in view of Hsueh to halt the other local phase adjusters (i.e., “second time-interleaving circuitry”) from the other receiver lanes from providing output by using the clock domain crossing (CDC) circuitry configured to halt the other receiver lanes output during providing output from a selected channel from a receiver lane as disclosed in the teachings of Poplack, because the motivation lies in Poplack that the sequencer may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes for resolving clock domain crossing issues and results in power savings based on receiving from a subset of the receiver lanes.
The combination of Hossain in view of Wolkovitz, and further in view of Poplack, further in view of Chiang, and further in view of Hsueh does not explicitly disclose glitch control circuitry. However the claim feature would be rendered obvious in view of De et al. US (2017/0053051).
De discloses glitch control circuitry can be a clock domain crossing (CDC) synchronization circuit for glitch detection, (see Para [0010], [0025], [0027], & [0035])
(De suggests the glitch control circuitry detects and prevents the glitch from propagating to the network (see Para’s [0010], [0025], [0027], & [0035])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the clock domain crossing (CDC) circuitry disclosed in Hossain in view of Wolkovitz, further in view of Chiang, further in view of Hsueh, and further in view of Poplack to include the glitch control circuitry of the clock domain crossing (CDC) synchronization circuit disclosed in the teachings of De, because the motivation lies in De that the glitch control circuitry detects and prevents the glitch from propagating to the network.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939) and further in view of Chiang et al. US (2009/0161247) as applied to claim 8 above, further in view of Moshe et al. US (2024/0143518), and further in view of Doblar USP (7,822,110).
Regarding Claim 11, the combination of Hossain in view of Wolkovitz, and further in view of Chiang discloses the system of claim 1, but does not disclose the claim feature of further comprising: computing parameters for each of the receiver circuits based on time-multiplexed outputs of the respective receiver circuits. However the claim feature would be rendered obvious in view of Moshe et al. US (2024/0143518).
Moshe discloses computing parameters for each of the receiver circuits based on time-multiplexed outputs of the respective receiver circuits (see Para [0060] i.e., For example, each link, lane, and/or channel may include receive filters and transmitter filters with coefficients (i.e., “parameters”) that are configured to establish data signal integrity meeting the predefined BER threshold. These sets of coefficient values may be determined and verified by link state machine 532.1 (i.e., “calibration circuitry”)…For example, coefficient value logic 532.2 may check a register managed by configuration service 542 for previously used coefficient values(i.e., “parameters”) (i.e., previously used coefficient values for meeting the predetermined BER threshold is based on the receiver output of each lane)).
(Moshe suggests the coefficients are configured for each receiver lane for meeting the predefined BER threshold for establishing data signal integrity, (see Para [0060])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the receiver circuits in each of the lanes as disclosed in the system of Hossain in view of Wolkovitz, and further in view of Chiang to comprise computing parameters for the receiver lanes based on time-multiplexed outputs of the respective receiver circuits as disclosed in Moshe, because the motivation lies in Moshe that the coefficients are configured for each receiver lane for meeting the predefined BER threshold for establishing data signal integrity.
The combination of Hossain in view of Wolkovitz, further in view of Chiang, and further in view of Moshe does not disclose the claim feature of including to perform one or more of: compute codes to control times at which the respective receiver circuits sample the respective signals. However the claim feature would be rendered obvious in view of Doblar USP (7,822,110).
Doblar discloses circuitry (see Fig. 1 i.e., service processor 140) configured to compute codes to control times at which the respective receiver circuits sample the respective signals (see Col. 2 lines 10-37 i.e., the service processor is configured to analyze the eye scan to determine various characteristics such as sample time (i.e., “codes”)…and convey the resulting sample time, high voltage threshold, and low voltage threshold to the receiver. The receiver is configured to sample the voltage of the selected lane at the sample time…The resulting sampled data can be used to determine a particular system assembly has sufficient operating electrical performance gain & Col. 5 line 45-Col. 6 lines 1-4).
(Doblar suggests the sample times may be conveyed to the deserializers 122 for sampling data at the sample time for determining that a particular system assembly has sufficient operating electrical performance margin, and to determine optimum phase offset and voltage thresholds to minimize the bit-error rate experienced on a lane under test, (see Col. 2 lines 24-26 & Col. 6 lines 1-4)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the respective receiver circuit sampling times as disclosed in Hossain in view of Wolkovitz, further in view of Chiang, and further in view of Moshe to control the times at which the receiver circuits sample the respective signals based on compute codes (i.e., “sample times”) configured for the receivers as disclosed in the teachings of Doblar who discloses circuitry configured to compute codes to control times at which respective receiver circuits sample the respective signals, because the motivation lies in Doblar that the sample times may be conveyed to the deserializers 122 for sampling data at the sample time for determining that a particular system assembly has sufficient operating electrical performance margin, and to determine optimum phase offset and voltage thresholds to minimize the bit-error rate experienced on a lane under test.
Regarding Claim 12, the combination of Hossain in view of Wolkovitz, further in view of Chiang discloses the system of claim 11, but does not disclose the claim feature of wherein the computing the parameters further comprises: computing the parameters for enabled ones of the receiver circuits. However the claim feature would be rendered obvious in view of Moshe et al. US (2024/0143518).
Moshe discloses wherein the time-multiplexed calibration circuitry is further configured to compute parameters for enabled ones of the receiver circuits (see Para [0060] i.e., For example, each link, lane, and/or channel (i.e., enabled receiver circuits on each lane) may include receive filters and transmitter filters with coefficients (i.e., “parameters”) that are configured to establish data signal integrity meeting the predefined BER threshold)
(Moshe suggests the coefficients are configured for each receiver lane for meeting the predefined BER threshold for establishing data signal integrity, (see Para [0060])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the receiver circuits in each of the lanes as disclosed in the system of Hossain in view of Wolkovitz, and further in view of Chiang to compute the parameters for enabled one of the receiver lanes of the receiver circuits as disclosed in Moshe, because the motivation lies in Moshe that the coefficients are configured for each receiver lane for meeting the predefined BER threshold for establishing data signal integrity.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939), further in view of Chiang et al. US (2009/0161247), and further in view of Hsueh US (2012/0063291) as applied to claim 15 above, and further in view of Kochavi et al. USP (11,909,850).
Regarding Claim 16, Hossain discloses the system of claim 15, including providing outputs to the CDR system and to the second IC device, (see Fig. 3 & Para’s [0035-0036]), but the references combined does not disclose wherein the first IC device further comprises: multi-stage de-serializer circuitry configured to de-serialize data outputs of the receiver circuits in stages. However the claim feature would be rendered obvious in view of Kochavi et al. USP (11,909,850).
Kovachi discloses wherein a first IC device (see Fig. 2 i.e., 204) further comprises: multi-stage de-serializer circuitry (see Fig. 2 i.e., each receiver per lane includes a de-serializer circuit) configured to de-serialize data outputs of the receiver circuits in stages (see Fig. 2 & Col. 9 lines 55-60 i.e., Each receiver Rx may include an I/O interface to receive the serialized data on the respective lane from a respective transmitter Tx on the other die, and a de-serializer circuit to convert the serial data into parallel data (i.e., reception and de-serializing by converting the serialized data into parallel data for output may represent “stages”)).
(Kovachi suggests each receiver RX may include a de-serializer circuit to convert the serial data into parallel data for appropriately converting the serialized data for output (see Fig. 2 & Col. 9 lines 55-60)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for each of the per lane receivers which provide outputs to the CDR system and to the second IC device as disclosed in Hossain in view of Wolkovitz, further in view of Chiang, and further in view of Hsueh to each include the de-serializer circuitry of the per lane receivers configured to de-serialize data outputs of the receiver circuits in stages as disclosed in the teachings of Kovachi which results in multi-stage de-serializer circuitry providing de-serialized outputs to the CRD system and second IC device, because the motivation lies in Kovachi that each receiver RX may include a de-serializer circuit to convert the serial data into parallel data for appropriately converting the serialized data for output.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939), further in view of Chiang et al. US (2009/0161247), and further in view of Hsueh US (2012/0063291), and further in view of Kochavi et al. USP (11,909,850) as applied to claim 16 above, and further in view of Kozaki et al. US (2010/0232798).
Regarding 17, Hossein discloses the system of claim 16, wherein the first and second IC devices comprise respective first and second chip-to-chip interface circuitry configured to interface with one another over a link, (Hossain, see Fig. 3 i.e., line interface 68-69 between global clock recovery circuit (i.e., CDR) and remaining receiver circuits 61-64 of integrated circuit 60)
wherein the first and second chip-to-chip interface circuitry comprise respective parallel physical layer circuitry, (Hossain, see Fig. 3 Para’s [0035-0036] i.e., the second integrated circuit 60 includes a receiver on each one of the communication lines 11-14 & [0037-0039] i.e., global clock recovery circuit (upper portion 98)), but the references combined does not disclose the claim feature of the first and second chips configured to interface with one another over a fiber optic link. However the claim feature would be rendered obvious in view of Kozaki et al. US (2010/0232798).
Kozaki discloses a plurality of receivers as slave stations (see Fig. 1 i.e., ONU’s) and a clock recover circuit as a master station (see Fig. 1 i.e., CDR 12 of OLT 1) configured to interface with one another over a fiber optic link, (see Fig. 1 i.e., optical fiber link 3 & Para’s [0042-0043]).
(Kozaki suggests the master station communicates with the slave stations over fiber optic link for managing the slave stations and performing clock data recovery, (see Fig. 1 & Para’s [0042-0044])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the first and second chip-to-chip interface circuitry including the remaining receiver circuits which may be slave stations and the reference receiver circuit which may be a master station configured to interface with one another over a link as disclosed in Hossain in view of Wolkovitz, further in view of Chiang, further in view of Hsueh, and further in view of Kochavi to be performed over a fiber optic link as disclosed in the teachings of Kozaki who discloses a plurality of receivers as slave stations and a clock recover circuit as a master station configured to interface with one another over a fiber optic link, because the motivation lies in Kozaki that the master station communicates with the slave stations over fiber optic link for managing the slave stations and performing clock data recovery.
Claims 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939), and further in view of Chiang et al. US (2009/0161247) as applied to claim 8 above, and further in view of Poplack et al. USP (11,275,598).
Regarding Claim 13, Hossain discloses the system of claim 8, wherein outputs of the receiver circuits comprise the receiver clocks, (see Para’s [0026] i.e., error signals output from the receivers can be in the form of phase error signals of a local CDR for the specific lane & [0029] i.e., receivers indicate errors such as phase offsets, between a local sampling times and the data signals on the communication lines)
and wherein the system further comprises: first time-interleaving circuitry configured to time-interleave the receiver clocks output from the receiver circuits based on a channel select control; (see Figures 1 & 3 & Para’s [0026], [0029] i.e., local clock recovery circuits 51-54 include phase detectors (i.e., “first time-interleaving circuitry”) which output error signals & [0036] i.e., The local error signals produced in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit (i.e., a channel or communication line is selected for providing from each receiver each of the error signals suggests a channel selection at a particular time)).
While Hossain suggests transitions of the channel select control based on each receiver respectively providing the error signal to the global clock recovery circuit (see Figures 1 & 3 & Para’s [0026], [0029], & [0036] i.e., The local error signals produced in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit (i.e., a channel or communication line is selected for providing from each receiver each of the error signals suggests a transition of channel selection at particular times for providing the error signals)), the combination of Hossain in view of Wolkovitz, and further in view of Chiang does not disclose the claim feature of and clock domain crossing (CDC) circuitry configured to halt the receiver clocks output from the receiver circuits during transitions of the channel select control. However the claim feature would be rendered obvious in view of Poplack et al. USP (11,275,598).
Poplack discloses clock domain crossing (CDC) circuitry configured to halt the receiver lanes output from receiver circuits during providing output from a selected channel (see Fig. 3A i.e., selected channel 308 & Col. 5 lines 6-35 i.e., The RxFE circuit block 304 may receive incoming data from a corresponding data input lane 308…the macro receiver 310 may provide to the RXPCS 312, a receiver clock signal (i.e., “output”) & lines 35-50 i.e., the switching ASIC 300 may comprise a sequencer for each output lane…The sequence 324 may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes (which may include data input lane 308) corresponding to the data output lane 322 (i.e., halt other receiver lanes)).
(Poplack suggests the sequencer 324 may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes for resolving clock domain crossing issues and results in power savings based on receiving from a subset of the receiver lanes (see Fig. 3A & Col. 5 lines 35-50)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for a receiver which provides the error signal output during a transition of the channel selection control as disclosed in Hossain in view of Wolkovitz, and further in view of Chiang to halt the receiver clocks output from the other receiver lanes from providing output by using the clock domain crossing (CDC) circuitry configured to halt the other receiver lanes output during providing output from a selected channel from a receiver lane as disclosed in the teachings of Poplack, because the motivation lies in Poplack that the sequencer may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes for resolving clock domain crossing issues and results in power savings based on receiving from a subset of the receiver lanes.
Claims 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. US (2015/0078495) in view of Wolkovitz et al. USP (11,031,939), and further in view of Chiang et al. US (2009/0161247) as applied to claim 8 above, further in view of Poplack et al. USP (11,275,598), and further in view of De et al. US (2017/0053051).
Regarding Claim 14, Hossain discloses the system of claim 13, further comprising: second time-interleaving circuitry configured to time-interleave data output from the receiver circuits based on the channel select control; (In light of the applicants specification in Para [0043], the “second time-interleaving circuitry “refers to the time-interleave de-skew circuitry 130 in Fig. 1 (Hossain, see Fig. 3, i.e., local phase adj. 71-74 i.e., “second time-interleaving circuitry” which provide the error signal output to the global clock recovery circuit & Para [0036] i.e., The local error signals produced in each of the lanes corresponding with communication lines 11-14 are delivered on line 68 to the global clock recovery circuit (i.e., a channel or communication line is selected for providing from each receiver each of the error signals suggests a transition of channel selection at particular times for providing the error signals)), but the references combined does not disclose the claim feature and glitch control circuitry configured to halt an output of the second time-interleaving circuitry during the transitions of the channel select control. However the claim feature would be rendered obvious in view of Poplack et al. USP (11,275,598).
In light of the applicants specification, glitch control circuitry configured to halt an output of the second time-interleaving circuitry refers to the clock domain processing crossing (CDC) circuitry 134 which disables the time-interleave de-skew circuitry 130 based on arising glitches (see applicants specification Para [0043]).
Poplack discloses clock domain crossing (CDC) circuitry configured to halt the receiver lanes output from receiver circuits during providing output from a selected channel (see Fig. 3A i.e., selected channel 308 & Col. 5 lines 6-35 i.e., The RxFE circuit block 304 may receive incoming data from a corresponding data input lane 308…the macro receiver 310 may provide to the RXPCS 312, a receiver clock signal (i.e., “output”) & lines 35-50 i.e., the switching ASIC 300 may comprise a sequencer for each output lane…The sequence 324 may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes (which may include data input lane 308) corresponding to the data output lane 322 (i.e., halt other receiver lanes)).
(Poplack suggests the sequencer 324 may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes for resolving clock domain crossing issues and results in power savings based on receiving from a subset of the receiver lanes (see Fig. 3A & Col. 5 lines 35-50)).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for a receiver which provides the error signal output during a transition of the channel selection control as disclosed in Hossain in view of Wolkovitz, and further in view of Chiang to halt the other local phase adjusters (i.e., “second time-interleaving circuitry”) from the other receiver lanes from providing output by using the clock domain crossing (CDC) circuitry configured to halt the other receiver lanes output during providing output from a selected channel from a receiver lane as disclosed in the teachings of Poplack, because the motivation lies in Poplack that the sequencer may be triggered by a clock domain-crossing micro-architecture (not shown) with a configurable logic such that the UMUX 302 receives bits from the subset of the receiver lanes for resolving clock domain crossing issues and results in power savings based on receiving from a subset of the receiver lanes.
The combination of Hossain in view of Wolkovitz, further in view of Chiang, and further in view of Poplack does not explicitly disclose glitch control circuitry. However the claim feature would be rendered obvious in view of De et al. US (2017/0053051).
De discloses glitch control circuitry can be a clock domain crossing (CDC) synchronization circuit for glitch detection, (see Para [0010], [0025], [0027], & [0035])
(De suggests the glitch control circuitry detects and prevents the glitch from propagating to the network (see Para’s [0010], [0025], [0027], & [0035])).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date for the clock domain crossing (CDC) circuitry disclosed in Hossain in view of Wolkovitz, further in view of Chiang, and further in view of Poplack to include the glitch control circuitry of the clock domain crossing (CDC) synchronization circuit disclosed in the teachings of De, because the motivation lies in De that the glitch control circuitry detects and prevents the glitch from propagating to the network.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ADNAN BAIG/Primary Examiner, Art Unit 2461
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