DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-13, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cowperthwaite et al. (U.S. Patent Application Publication Number 2023/0297421), Hendin et al. (U.S. Patent Application Publication Number 2009/0204834), and Kegel et al. (U.S. Patent Application Publication Number 2019/0235940).
Regarding Claim 1, Cowperthwaite discloses a system on a chip (SoC) (Figure 13, item 1300, paragraph 0233) comprising:
at least one central processing unit (CPU) (Figure 13, item 1308, paragraphs 0233 and 0260);
at least one graphics processing unit (GPU) (Figure 13, item 1306, paragraph 0054);
a hardware accelerator (Figure 13, item 1304, paragraph 0234; i.e., vision processor 1304 can be used to accelerate compute vision operations and is therefore a “hardware accelerator”) comprising data processing engines (DPEs) (Figure 16C, items 1640, paragraph 0280; i.e., the teachings of the hardware accelerator 1630 can apply to hardware accelerator 1304 as well) and other circuitry (Figure 16C, item 1642, paragraph 0281) that excludes DPEs, wherein the DPEs are in a first power or clock domain, wherein the hardware accelerator excludes the at least one GPU (Figure 13; i.e., hardware accelerator 1304 is separate from GPU 1306); and
an interface communicatively coupling the CPU to the hardware accelerator (Figure 16C, item 1628, paragraph 0280).
Cowperthwaite does not expressly disclose the other circuitry is in a second power or clock domain, wherein the SoC is configured to turn off the first power or clock domain to disable the DPEs while the second power or clock domain remains turned on; and
wherein the CPU is in a third power or clock domain that is separate from the first and second power or clock domains.
In the same field of endeavor (e.g., SoC configuration techniques), Hendin teaches wherein the other circuitry (Figure 1, item 110) is in a second power or clock domain (paragraph 0023; i.e., the always on module 110 and rest of SoC 102 may be connected to different voltage rails), wherein the SoC is configured to turn off the first power or clock domain to disable the DPEs (Figure 1, item 118, paragraph 0020; i.e., Cowperthwaite discloses multiple DPEs as discussed above) while the second power or clock domain remains turned on (paragraphs 0024 and 0029; i.e., always on module 110 is a power partition which remains powered while other portions of SoC 102 are put into a sleep state where their power is gated or disabled; an always on power rail allows substantial portions of SOC 216 to enter a sleep state while still powering a minimal portion [e.g., always on module 110] of SOC 216 in order to allow SOC 216 to be responsive to inputs and exit sleep mode in time to be responsive to inputs).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Hendin’s teachings of SoC configuration techniques with the teachings of Cowperthwaite, for the purpose of saving power in the SoC while still retaining use of certain important components.
Also in the same field of endeavor (e.g., integrated circuit configuration techniques), Kegel teaches wherein the CPU is in a third power or clock domain that is separate from the first and second power or clock domains (paragraph 0015; i.e., the CPU is in a different voltage/power and clock domain than the domain(s) in which the accelerator is operating).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Kegel’s teachings of integrated circuit configuration techniques with the teachings of Cowperthwaite, for the purpose of further reducing the power consumption of the SoC (i.e., because the processor could be placed in an off state while the accelerator circuitry could continue to run).
Regarding Claims 2, 12, and 18, Cowperthwaite discloses wherein the other circuitry in the second power or clock domain comprises:
a controller (Figure 3C, item 367, paragraph 0102);
a network on chip (NoC) (paragraph 0278); and
an Input-Output Memory Management Unit (IOMMU) (Figure 3C, item 364) comprising circuitry configured to perform a physical to virtual address translation (paragraphs 0104 and 0136), wherein the IOMMU is coupled to the DPEs via the NoC (paragraph 0278; i.e., there is a fabric that connects the IOMMU 364 with the DPEs 370; Cowperthwaite discloses that an NoC can be used to replace fabrics; Cowperthwaite also states that different embodiments of the invention can be combined [paragraph 0498]).
Regarding Claims 3 and 13, Cowperthwaite discloses wherein the IOMMU is configured to translate virtual addresses used by the hardware accelerator to physical addresses used by the CPU (Figure 3C, item 361) before transmitting data from the hardware accelerator to the interface (paragraphs 0104 and 0136).
Regarding Claim 4, Cowperthwaite discloses wherein the controller communicates with the DPEs through the NoC (paragraph 0278; i.e., there is a fabric that connects the memory controller 367 with the DPEs 370; Cowperthwaite discloses that an NoC can be used to replace fabrics; Cowperthwaite also states that different embodiments of the invention can be combined [paragraph 0498]).
Regarding Claim 5, Cowperthwaite discloses wherein the controller communicates with the CPU only through the interface (Figure 4B, item 440), wherein the interface is a second NoC (i.e., Cowperthwaite discloses that an NoC can be used to replace fabrics; Cowperthwaite also states that different embodiments of the invention can be combined [paragraph 0498]), wherein the second NoC is larger than the NoC in the hardware accelerator (paragraph 0131; i.e., the second NoC is larger because it must connect between two separate chips whereas the first NoC connects only within a single chip).
Regarding Claim 8, Hendin and Kegel teach wherein the SoC is configured to turn off the first power or clock domain when the DPEs are idle (Kegel, paragraph 0024), wherein the SoC is configured to turn on the first power or clock domain in response to the CPU assigning a task to the hardware accelerator (Hendin, paragraphs 0027 and 0031; i.e., given the fact that the CPU and GPU may be powered independently, it is possible that the wake event could come from the CPU that is already awake and wishes to assign a task to the GPU).
Regarding Claims 9 and 20, Cowperthwaite discloses wherein the DPEs are arranged in an array (Figure 16B, items 1610), wherein each of the DPEs comprises a core (Figure 17, item 1714), a memory module (Figure 16B, items 1626), and an interconnect, wherein the interconnects in the DPEs are interconnected so that the DPEs are able to transmit data between each other (Figure 16B, items 1623, paragraph 0277).
Regarding Claims 10 and 16, Cowperthwaite discloses wherein the hardware accelerator is at least one of an artificial intelligence (AI) accelerator (paragraph 0283), a cryptography accelerator, or a compression accelerator.
Regarding Claim 11, Cowperthwaite discloses a method comprising:
a hardware accelerator (Figure 13, item 1304, paragraph 0234; i.e., vision processor 1304 can be used to accelerate compute vision operations and is therefore a “hardware accelerator”) comprising data processing engines (DPEs) (Figure 16C, items 1640, paragraph 0280; i.e., the teachings of the hardware accelerator 1630 can apply to hardware accelerator 1304 as well) and other circuitry (Figure 16C, item 1642, paragraph 0281) that excludes DPEs, wherein the DPEs are in a first power or clock domain;
wherein the hardware accelerator is located on a system on a chip (SoC) (Figure 13, item 1300, paragraph 0233) which further comprises:
at least one central processing unit (CPU) (Figure 13, item 1308, paragraphs 0233 and 0260); and
at least one graphics processing unit (GPU) (Figure 13, item 1306, paragraph 0054), wherein the hardware accelerator excludes the at least one GPU (Figure 13; i.e., hardware accelerator 1304 is separate from GPU 1306).
Cowperthwaite does not expressly disclose determining that DPEs in a hardware accelerator are idle, wherein other circuitry, that excludes DPEs, in the hardware accelerator are in a second power or clock domain;
turning off the first power or clock domain but not the second power or clock domain so that the DPEs are disabled but the other circuitry remains operational;
determining, after turning off the first power or clock domain, that the DPEs have work;
turning on the first power or clock domain so the DPEs are operational to perform the work; and
wherein the CPU is in a third power or clock domain that is separate from the first and second power or clock domains.
In the same field of endeavor, Hendin teaches wherein other circuitry (Figure 1, item 110), that excludes the DPE, in the hardware accelerator are in a second power or clock domain (paragraph 0023; i.e., the always on module 110 and rest of SoC 102 may be connected to different voltage rails);
turning off the first power or clock domain but not the second power or clock domain so that the DPE is disabled but the other circuitry remains operational (paragraphs 0024 and 0029; i.e., always on module 110 is a power partition which remains powered while other portions of SoC 102 are put into a sleep state where their power is gated or disabled; an always on power rail allows substantial portions of SOC 216 to enter a sleep state while still powering a minimal portion [e.g., always on module 110] of SOC 216 in order to allow SOC 216 to be responsive to inputs and exit sleep mode in time to be responsive to inputs);
determining, after turning off the first power or clock domain, that the DPE has work (paragraphs 0026-0027, 0029, and 0031; i.e., a wake signal can be sent to the SoC when work needs to be performed); and
turning on the first power or clock domain so the DPEs is operational to perform the work (paragraphs 0026-0027 and 0031; i.e., any needed component of the SoC [e.g., the video processor 118 - see paragraph 0029] can be awoken to perform the work).
Also in the same field of endeavor, Kegel teaches determining that DPEs (paragraph 0015; i.e., Cowperthwaite discloses multiple DPEs as discussed above) in a hardware accelerator (Figure 1, item 101, paragraph 0015) are idle (paragraphs 0024); and
wherein the CPU is in a third power or clock domain that is separate from the first and second power or clock domains (paragraph 0015; i.e., the CPU is in a different voltage/power and clock domain than the domain(s) in which the accelerator is operating).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 11.
Regarding Claim 17, Cowperthwaite discloses a system comprising:
an IC (Figure 13, item 1300, paragraph 0233) comprising:
at least one central processing unit (CPU) (Figure 13, item 1308, paragraphs 0233 and 0260);
at least one graphics processing unit (GPU) (Figure 13, item 1306, paragraph 0054);
a hardware accelerator (Figure 13, item 1304, paragraph 0234; i.e., vision processor 1304 can be used to accelerate compute vision operations and is therefore a “hardware accelerator”) comprising DPEs (Figure 16C, items 1640, paragraph 0280; i.e., the teachings of the hardware accelerator 1630 can apply to hardware accelerator 1304 as well) in a first power or clock domain and other circuitry (Figure 16C, item 1642, paragraph 0281), that excludes DPEs, wherein the hardware accelerator excludes the at least one GPU (Figure 13; i.e., hardware accelerator 1304 is separate from GPU 1306).
Cowperthwaite does not expressly disclose a memory controller; and
at least one memory coupled to the memory controller in the IC;
wherein the other circuitry is in a second power or clock domain, wherein the IC is configured to turn off the first power or clock domain to disable the DPEs while the other circuitry in the second power or clock domain remains operational;
wherein the CPU is in a third power or clock domain that is separate from the first and second power or clock domains.
In the same field of endeavor, Hendin teaches a memory controller (paragraph 0021); and
at least one memory (Figure 1, item 108) coupled to the memory controller in the IC (paragraph 0021);
wherein the other circuitry (Figure 1, item 110) is in a second power or clock domain (paragraph 0023; i.e., the always on module 110 and rest of SoC 102 may be connected to different voltage rails), wherein the IC is configured to turn off the first power or clock domain to disable the DPEs (Figure 1, item 118, paragraph 0020; i.e., Cowperthwaite discloses multiple DPEs as discussed above) while the other circuitry in the second power or clock domain remains operational (paragraphs 0024 and 0029; i.e., always on module 110 is a power partition which remains powered while other portions of SoC 102 are put into a sleep state where their power is gated or disabled; an always on power rail allows substantial portions of SOC 216 to enter a sleep state while still powering a minimal portion [e.g., always on module 110] of SOC 216 in order to allow SOC 216 to be responsive to inputs and exit sleep mode in time to be responsive to inputs).
Also in the same field of endeavor, Kegel teaches wherein the CPU is in a third power or clock domain that is separate from the first and second power or clock domains (paragraph 0015; i.e., the CPU is in a different voltage/power and clock domain than the domain(s) in which the accelerator is operating).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 17.
Regarding Claim 19, Cowperthwaite discloses wherein the IC comprises a CPU and an interconnect, wherein the interconnect couples the CPU (Figure 3C, item 361) to the controller (Figure 3C, item 367) and the IOMMU (Figure 3C, item 364) in the hardware accelerator (paragraphs 0103-0105).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a system for having separate power and clock domains for hardware accelerators.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN, ESQ. whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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