DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s arguments with respect to claims 1 – 10 have been considered, but they are not persuasive. In the response to the Office Action dated October 2, 2025, Applicant argues that Ecton does not disclose “a first circuit layer formed on the first insulating layer and electrically connected to the conductive via” and a “second circuit layer formed on the second insulating layer and electrically connected to the first circuit layer’ as recited in independent claims 1 and 6 of the instant application. Applicant contends that as illustrated in FIG. 1A of Ecton, the conductive vias 122 are formed in the solder resist 116 without any circuit layer being formed thereon. Furthermore, the conductive traces 114 are embedded within the dielectric 112, rather than being formed on an upper surface thereof. Applicant is reminded that the claim recites that a first circuit layer is formed on the first insulating layer. Examiner has cited conductive vias 122 as the first circuit layer and solder resist 116 as the insulating layer. In Figure 1A of Ecton, conductive vias 122 are formed within and on side surfaces of the solder resist 116. The claims do not recite that the first circuit layer is formed directly on the first insulating layer or that the first circuit layer is formed on an upper surface of the first insulating layer. Likewise, conductive traces 114 (cited “second circuit layer”) are formed within and on the bottom surface of dielectric 112 (cited “second insulating layer”). The claims do not recite that the second circuit layer is formed directly on the second insulating layer or that the second circuit layer is formed on an upper surface of the second insulating layer.
Further, Applicant argues that Ecton’s solder resist 116 and conductive vias 122 are not directly disposed on opposing sides of a core 108, as stated in the claims. Applicant is reminded that claims 1 and 6 do not recite that the first circuit structure is disposed directly on the first side of the core board body or that the second circuit structure is disposed directly on the first circuit structure.
Even if Examiner were to agree with Applicant’s above arguments, Ecton still discloses the claimed structure of claims 1 and 6 as further detailed in the rejection(s) below.
Thus, Applicant’s traversal of the instant rejection on these grounds is deemed unsuccessful.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ecton et al. (U.S. Patent Publication No. 2023/0078099).
Regarding claim 1, in Figure 1A, Ecton discloses a package substrate, comprising: a core board body (108) having a first side, a second side opposing the first side, and at least one conductive via (110) connecting the first side and the second side; a first circuit structure (116, 122; comprising solder resist 116 and vias 122 OR 106, substrate 106) disposed on the first side of the core board body, and comprising at least one first insulating layer (116 OR 132) formed on the core board body and a first circuit layer (122 OR 144, conductive traces 144) formed on the first insulating layer and electrically connected to the conductive via (through conductive traces 114 OR through vias 134, interconnects 126, and conductive traces 114); and a second circuit structure (112, 114; comprising dielectric 112 and conductive traces 114 OR 112, 114, 124; comprising dielectric 112, conductive traces 114, and interconnects 124) disposed on the first circuit structure (disposed on bottom surface of solder resist 116 OR disposed on the bottom surface of substrate 106), and comprising at least one second insulating layer (112) formed on the first insulating layer (formed on the bottom surface thereof) and a second circuit layer (114 OR 124) formed on the second insulating layer and electrically connected to the first circuit layer (Figure 1A), wherein a material forming the second insulating layer is an Ajinomoto build-up film (paragraph [0083]) that is different from a material forming the first insulating layer (in some embodiments, solder resist 116 may comprise a different material from dielectric 112; end of paragraph [0083] OR mold compound 132 is formed of epoxy resin, paragraph [0086]).
Regarding claim 2, Ecton discloses wherein the first circuit structure further comprises a plurality of first conductive blind vias formed in the first insulating layer and electrically connected to the first circuit layer (Figure 1A).
Regarding claim 3, Ecton discloses wherein the conductive via extends into the first circuit structure and is electrically connected to the first circuit layer (Figure 1A).
Regarding claim 4, Ecton discloses wherein the first circuit structure is further formed on the second side of the core board body (Figure 1A).
Regarding claim 5, Ecton discloses wherein the second circuit structure is further formed on the first circuit structure on the second side of the core board body (Figure 1A).
Regarding claim 6, in Figure 1A, Ecton discloses a method of manufacturing a package substrate, comprising: providing a core board body (108) having a first side and a second side opposing the first side; forming a first circuit structure (116, 122; comprising solder resist 116 and vias 122) on the first side of the core board body, wherein the first circuit structure comprises at least one first insulating layer (116) formed on the core board body and a first circuit layer (122) formed on the first insulating layer, wherein the core board body has at least one conductive via (110) connecting the first side and the second side to electrically connect the first circuit layer; and forming a second circuit structure (112, 114; comprising dielectric 112 and conductive traces 114) on the first circuit structure (disposed on bottom surface of solder resist 116), wherein the second circuit structure comprises at least one second insulating layer (112) formed on the first insulating layer and a second circuit layer (114) formed on the second insulating layer and electrically connected to the first circuit layer (Figure 1A), wherein a material forming the second insulating layer is an Ajinomoto build- up film (paragraph [0083]) that is different from a material forming the first insulating layer (in some embodiments, solder resist 116 may comprised a different material from dielectric 112; end of paragraph [0083].
Regarding claim 7, Ecton discloses wherein the first circuit structure further comprises a plurality of first conductive blind vias formed in the first insulating layer and electrically connected to the first circuit layer (Figure 1A).
Regarding claim 8, Ecton discloses wherein the conductive via extends into the first circuit structure and is electrically connected to the first circuit layer (Figure 1A).
Regarding claim 9, Ecton discloses wherein the first circuit structure is further formed on the second side of the core board body (Figure 1A).
Regarding claim 10, Ecton discloses wherein the second circuit structure is further formed on the first circuit structure on the second side of the core board body (Figure 1A).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847