DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 25, 2026 has been entered.
Response to Amendment
Applicant's arguments with respect to claims 1 – 10 have been considered but they are not persuasive in view of the different interpretation of the prior art based on the amendment(s) made. Please find the ground(s) of rejection below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ecton et al. (U.S. Patent Publication No. 2023/0078099).
(116, 122; comprising solder resist 116 and vias 122 OR 106, substrate 106)
Regarding claim 1, in Figure 1A, Ecton discloses a package substrate, comprising: a core board body (108) having a first side, a second side opposing the first side, and at least one conductive via (110) connecting the first side and the second side; a first circuit structure (112, 114; comprising lower dielectric 112 and lower conductive traces 114) disposed directly on the first side (bottom side of core 108) of the core board body, and comprising at least one first insulating layer (112; dielectric 112 may comprise benzocyclobutene (BCB), cyclotene, polyimide, epoxy/phenol, acrylic, and/or polybenzoxazole (PBO), Ajinomoto Buildup Film (ABF), bismaleimide-triazine (BT) resin, organic dielectrics with inorganic fillers or low-k and ultralow-k dielectric, paragraph [0083]) formed on the core board body and a first circuit layer (114) formed on the first insulating layer and electrically connected to the conductive via (Figure 1A); and a second circuit structure (116, 122; comprising solder resist 116 and vias 122) disposed on the first circuit structure, and comprising at least one second insulating layer (116) formed on the first insulating layer and a second circuit layer (122) formed on the second insulating layer and electrically connected to the first circuit layer (Figure 1A), wherein a material forming the second insulating layer is an Ajinomoto build-up film (paragraph [0083]) that is different from a material forming the first insulating layer (solder resist 116 may comprise same material as dielectric 112, and dielectric 112 may be formed of Ajinomoto Buildup Film (ABF); end of paragraph [0083]).
Regarding claim 2, Ecton discloses wherein the first circuit structure further comprises a plurality of first conductive blind vias formed in the first insulating layer and electrically connected to the first circuit layer (Figure 1A).
Regarding claim 3, Ecton discloses wherein the conductive via extends into the first circuit structure and is electrically connected to the first circuit layer (Figure 1A).
Regarding claim 4, Ecton discloses wherein the first circuit structure is further formed on the second side of the core board body (Figure 1A).
Regarding claim 5, Ecton discloses wherein the second circuit structure is further formed on the first circuit structure on the second side of the core board body (Figure 1A).
Regarding claim 6, in Figure 1A, Ecton discloses a method of manufacturing a package substrate, comprising: providing a core board body (108) having a first side and a second side opposing the first side; forming a first circuit structure (112, 114; comprising lower dielectric 112 and lower conductive traces 114) directly on the first side (bottom side of core 108) of the core board body, wherein the first circuit structure comprises at least one first insulating layer (112; dielectric 112 may comprise benzocyclobutene (BCB), cyclotene, polyimide, epoxy/phenol, acrylic, and/or polybenzoxazole (PBO), Ajinomoto Buildup Film (ABF), bismaleimide-triazine (BT) resin, organic dielectrics with inorganic fillers or low-k and ultralow-k dielectric, paragraph [0083]) formed on the core board body and a first circuit layer (114) formed on the first insulating layer, wherein the core board body has at least one conductive via (110) connecting the first side and the second side to electrically connect the first circuit layer; and forming a second circuit structure (116, 122; comprising solder resist 116 and vias 122) on the first circuit structure, wherein the second circuit structure comprises at least one second insulating layer (116) formed on the first insulating layer and a second circuit layer (122) formed on the second insulating layer and electrically connected to the first circuit layer (Figure 1A), wherein a material forming the second insulating layer is an Ajinomoto build- up film (paragraph [0083]) that is different from a material forming the first insulating layer (solder resist 116 may comprise same material as dielectric 112, and dielectric 112 may be formed of Ajinomoto Buildup Film (ABF); end of paragraph [0083]).
Regarding claim 7, Ecton discloses wherein the first circuit structure further comprises a plurality of first conductive blind vias formed in the first insulating layer and electrically connected to the first circuit layer (Figure 1A).
Regarding claim 8, Ecton discloses wherein the conductive via extends into the first circuit structure and is electrically connected to the first circuit layer (Figure 1A).
Regarding claim 9, Ecton discloses wherein the first circuit structure is further formed on the second side of the core board body (Figure 1A).
Regarding claim 10, Ecton discloses wherein the second circuit structure is further formed on the first circuit structure on the second side of the core board body (Figure 1A).
Conclusion
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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