Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 22, 2023 is in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated. The examiner notes that the references JP 5015065 B2, JP 2013004648, and JP 2015032697 have not been considered because the applicant did not provide copies of these references. The examiner further notes that the documents submitted for JP 5015065 B2, JP 2013004648, and JP 2015032697 do not contain the actual text of JP 5015065 B2, JP 2013004648, and JP 2015032697 and instead contain numerous non-text symbols such as chess pieces, dice, and music notes.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation “the passive element includes a first side surface facing a side surface of the semiconductor chip and a second side surface perpendicular to the side surface of the semiconductor chip when viewed in a plan view,” on page 3 lines 7-9. This limitation renders the claim indefinite because this limitation makes the structure of the passive element conditional based on the view. Therefore, it is unclear whether the passive element includes a first side surface facing a side surface of the semiconductor chip and a second side surface perpendicular to the side surface of the semiconductor chip when not viewed in a plan view. For examination purposes, this limitation will be interpreted as the passive element includes a first side surface facing a side surface of the semiconductor chip and a second side surface perpendicular to the side surface of the semiconductor chip.
Claims 13-16 are also rejected for containing the same limitation because claims 13-16 depend from claim 12.
Claim 16 recites the limitation “wherein the insulating pattern extends in a direction parallel to the first side surface when viewed in a plan view,” on page 4 lines 1-2. This limitation renders the claim indefinite because this limitation makes the structure of the insulating pattern conditional based on the view. Therefore, it is unclear whether the insulating pattern extends in a direction parallel to the first side surface when not viewed in a plan view. For examination purposes, this limitation will be interpreted as wherein the insulating pattern extends in a direction parallel to the first side surface.
Claim 17 recites the limitation “the passive element overlaps the recessed portion vertically and includes a first side surface facing a side surface of the semiconductor chip and a second side surface perpendicular to the side surface of the semiconductor chip when viewed in a plan view,” on page 4 lines 14-16. This limitation renders the claim indefinite because this limitation makes the structure of the passive element conditional based on the view. Therefore, it is unclear whether the passive element includes a first side surface facing a side surface of the semiconductor chip and a second side surface perpendicular to the side surface of the semiconductor chip when not viewed in a plan view. For examination purposes, this limitation will be interpreted as the passive element includes a first side surface facing a side surface of the semiconductor chip and a second side surface perpendicular to the side surface of the semiconductor chip.
Claims 18-20 are also rejected for containing the same limitation because claims 18-20 depend from claim 17.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura et al. (US 2011/0304016).
Regarding Claim 12:
Nakamura discloses a semiconductor package, comprising:
a substrate (wiring board, See fig. 4, ref. no. 10, paragraph 41 and 52);
a semiconductor chip (semiconductor chip, See fig. 4, ref. no. 41 and paragraph 52) on the substrate; and
a passive element (left chip capacitor, See fig. 4, ref. no. 31 and paragraph 52) apart from the semiconductor chip in a first direction parallel to an upper surface of the substrate (horizontal direction along figure 4),
wherein the substrate includes a recessed portion (recessed portion in upper side surface, See figs. 1-4, ref. no. DP and paragraphs 48-51) at an upper portion thereof,
the passive element is vertically apart from the substrate with the recess portion therebetween (the chip capacitor vertically above the recessed portion, See figs. 2-4, ref. nos. DP, 31),
the passive element includes a first side surface (right side surface of the cubic capacitor body of the chip capacitor, See figs. 3B, 4, ref. no. 31 and paragraph 50) facing a side surface of the semiconductor chip (left side surface of the semiconductor chip See fig. 4, ref. no. 41) and a second side surface (top surface of the cubic capacitor body of the chip capacitor, See figs. 3B, 4, ref. no. 31 and paragraph 50) perpendicular to the side surface of the semiconductor chip when viewed in a plan view,
the first side surface and the second side surface have a first width (the vertical dimension of right side surface of the cubic capacitor body shown, See fig. 4, ref. no. 31) and a second width (the horizontal dimension of the top surface of the cubic capacitor body, See fig. 4, ref. no. 31), respectively, and
the first width is narrower than the second width (the vertical dimension of the right side surface of the cubic capacitor body is less than the horizontal dimension of the top surface of the cubic capacitor body, See fig. 4, ref. no. 31 and paragraph 50).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-10, 13-14, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US 2011/0304016) in view of Choi et al. (US 2013/0063917).
Regarding Claim 1:
Nakamura discloses a semiconductor package, comprising:
a substrate (wiring board, See fig. 4, ref. no. 10, paragraph 41 and 52) including a first surface (upper side surface, See fig. 4, ref. no. 10 and paragraph 44) and a second surface (lower side surface, See fig. 4, ref. no. 10 and paragraph 44) facing each other;
a semiconductor chip (semiconductor chip, See fig. 4, ref. no. 41 and paragraph 52) on the substrate;
a passive element (left chip capacitor, See fig. 4, ref. no. 31 and paragraph 52) apart from the semiconductor chip in a first direction parallel to the first surface of the substrate (horizontal direction along figure 4); and
wherein the substrate has a recessed portion (recessed portion, See figs. 1-4, ref. no. DP and paragraphs 48-51) on the first surface,
the passive element vertically overlaps the recessed portion (the chip capacitor vertically over laps the recessed portion, See figs. 2-4, ref. nos. DP, 31).
Nakamura does not disclose a first insulating pattern on an edge region of the first surface and the first insulating pattern protrudes in a second direction perpendicular to the first surface of the substrate.
Choi discloses a first insulating pattern on an edge region of the first surface (an under-fill dam formed along the outer edge of a substrate, See fig. 2, ref. no. 6, paragraphs 12 and 101-103) and the first insulating pattern protrudes in a second direction perpendicular to the first surface of the substrate (the under-fill dam extends in a vertical direction from the substrate, See fig. 2, ref. no. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Nakamura to include a first insulating pattern on an edge region of the first surface and the first insulating pattern protrudes in a second direction perpendicular to the first surface of the substrate as taught by Choi to prevent the molding resin from leaking out. (See Choi paragraph 4.)
Regarding Claim 2:
Nakamura discloses a molding layer (Molding Resin, See fig. 4, ref. no. 44 and paragraph 53-54) on the substrate, wherein the molding layer fills the recessed portion and space between the recessed portion and the passive element (the molding resin fill the recessed portion and the space between the recessed portion and the chip capacitor, See fig. 4, ref. no. DP, 31, 44).
Regarding Claim 4:
Nakamura discloses at least one connection terminal (solders, See figs. 2-4, ref. no. 33 and paragraphs 48-49) between the passive element and the first surface of the substrate.
Regarding Claim 5:
Nakamura discloses wherein a length of the recess portion in the second direction is 10 μm or more (depth of recess portion is approximately 10 to 100 µm, See paragraph 50).
Regarding Claim 6:
Choi discloses the under-fill dam may have a height equal to the distance between the substrate and the semiconductor chip (See paragraph 16). Nakamura discloses the semiconductor chip is connected to the wiring board through the solder bumps with the height of the solder bumps corresponding to the distance between the wiring board and the semiconductor chip (See fig. 4, ref. nos. 10, 41, 42 and paragraph 52) The examiner notes that Choi teaches the height of the under-fill dam decreases as the distance between the substrate and the semiconductor chip decreases because Choi teaches the relationship of the height of the under-fill dam and the distance between the substrate and the semiconductor chip as being equal. The examiner now points out that Nakamura is silent with respect to the height of the solder bumps, however, it would have been obvious to one of ordinary skill in the art before the effective filing date to have a length of the first insulating pattern in the second direction is 10 µm to 18 µm since it has been held that changes in dimensions are an obvious expedient and not a patentable distinction where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device. Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding Claim 7:
The combination of Nakamura and Choi discloses a length of the first insulating pattern in the first direction is 50 µm or more (Nakamura discloses the length and the width of wiring board are greater than the length and the width of the chip capacitor. See Nakamura figs. 3B, ref. no. 31, fig. 4, ref. no. 10, 31, and paragraph 49. Nakamura also discloses the length of the chip capacitor is 1.0 mm and the width is 0.5 mm. See Nakamura paragraph 50. Therefore, the length and the width of wiring board are greater than 1.0 mm and 0.5 mm. Choi discloses the under-fill dam is formed along outer edge of a substrate (See Choi paragraph 12). Thus, the under-fill dam will have dimensions that correspond with the outer edge of the wiring board and the outer edge of the wiring board has a length greater than 50 µm.).
Regarding Claim 8:
The combination of Nakamura and Choi discloses an upper surface of the passive element is above an upper surface of the first insulating pattern (Nakamura discloses the top surface of the chip capacitor is above the bottom surface the semiconductor chip. See Nakamura, fig. 4 ref. nos. 10, 31, 41. The examiner notes that the surface referred to as the top surface of the chip capacitor is the top surface of the cubic capacitor body. The examiner also notes that the distance between the upper side surface of the wiring board and the bottom surface of the semiconductor chip is the distance between the wiring board and the semiconductor chip. Choi discloses the under-fill dam may have a height that is equal the distance between the substrate and the semiconductor chip. See Choi paragraph 16. Thus, the chip capacitor will have an upper surface above an upper surface of the under-fill dam.).
The examiner also notes that an upper surface of the passive element is above an upper surface of the first insulating pattern would have been obvious to one of ordinary skill in the art before the effective filing date since it has been held that changes in dimensions are an obvious expedient and not a patentable distinction where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device. Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding Claim 9:
The combination of Nakamura and Choi discloses an upper surface of the first insulating pattern is above a lower surface of the passive element (Nakamura discloses the top surface of the semiconductor chip is above the bottom surface of chip capacitor. See Nakamura, fig. 4 ref. nos. 31, 41. The examiner notes that the surface referred to as the bottom surface of the chip capacitor is the bottom surface of the cubic capacitor body. Choi discloses the under-fill dam may have a height that is the same height as the outermost side of the semiconductor chip. See Choi paragraph 16. Thus, the under-fill dam will have an upper surface above a lower surface of the passive element.)
The examiner also notes that an upper surface of the first insulating pattern is above a lower surface of the passive element would have been obvious to one of ordinary skill in the art before the effective filing date since it has been held that changes in dimensions are an obvious expedient and not a patentable distinction where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device. Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding Claim 10:
The combination of Nakamura and Choi discloses an upper surface of the first insulating pattern is above an upper surface of the connection terminal (Nakamura discloses the top surface of the semiconductor chip is above the solders connected to the chip capacitor. See Nakamura, fig. 4 ref. nos. 31, 33, 41. Choi discloses the under-fill dam may have a height that is the same height as the outermost side of the semiconductor chip. See Choi paragraph 16. Thus, the under-fill dam will have an upper surface above an upper surface of the connection terminal.)
The examiner also notes that an upper surface of the first insulating pattern is above an upper surface of the connection terminal would have been obvious to one of ordinary skill in the art before the effective filing date since it has been held that changes in dimensions are an obvious expedient and not a patentable distinction where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device. Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding Claim 13:
Nakamura discloses the above stated semiconductor package.
Nakamura does not disclose an insulating pattern on an edge region of the substrate, wherein the insulating pattern protrudes in a second direction perpendicular to the upper surface of the substrate.
Choi discloses an insulating pattern on an edge region of the substrate (an under-fill dam formed along the outer edge of a substrate, See fig. 2, ref. no. 6, paragraphs 12 and 101-103), wherein the insulating pattern protrudes in a second direction perpendicular to the upper surface of the substrate (the under-fill dam extends in a vertical direction from the substrate, See fig. 2, ref. no. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Nakamura to include an insulating pattern on an edge region of the substrate, wherein the insulating pattern protrudes in a second direction perpendicular to the upper surface of the substrate as taught by Choi to prevent the molding resin from leaking out. (See Choi paragraph 4.)
Regarding Claim 14:
The combination of Nakamura and Choi discloses a lower surface of the passive element is below an upper surface of the insulating pattern (Nakamura discloses the bottom surface of chip capacitor is below the top surface of the semiconductor chip. See Nakamura, fig. 4 ref. nos. 31, 41. The examiner notes that the surface referred to as the bottom surface of the chip capacitor is the bottom surface of the cubic capacitor body. Choi discloses the under-fill dam may have a height that is the same height as the outermost side of the semiconductor chip. See Choi paragraph 16. Thus, the passive element will have a lower surface below an upper surface of the under-fill dam.)
The examiner also notes that a lower surface of the passive element is below an upper surface of the insulating pattern would have been obvious to one of ordinary skill in the art before the effective filing date since it has been held that changes in dimensions are an obvious expedient and not a patentable distinction where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device. Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding Claim 16:
The above stated combination of Nakamura and Choi discloses the above stated semiconductor package. Choi further discloses wherein the insulating pattern extends in a direction parallel to the first side surface when viewed in plan view (an under-fill dam formed along the outer edge of a substrate, See Choi fig. 2, ref. no. 6, paragraphs 12 and 101-103.)
The above stated combination of Nakamura and Choi is silent as to the outer edge of the wiring board extends in a direction parallel to the first side surface when viewed in a plan view.
Nakamura discloses a wiring board having a rectangular shape (See fig. 16A, ref. no. 5 and paragraph 33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Nakamura and Choi to include the wiring board having a rectangular shape as taught by Nakamura for ease of semiconductor package manufacturing through the use of wiring boards known shapes.
Regarding Claim 17:
Nakamura discloses a semiconductor package, comprising:
a substrate (wiring board, See fig. 4, ref. no. 10, paragraph 41 and 52) including a first surface (upper side surface, See fig. 4, ref. no. 10 and paragraph 44) and a second surface (lower side surface, See fig. 4, ref. no. 10 and paragraph 44) facing each other;
a semiconductor chip (semiconductor chip, See fig. 4, ref. no. 41 and paragraph 52) on the substrate;
a passive element (left chip capacitor, See fig. 4, ref. no. 31 and paragraph 52) apart from the semiconductor chip in a first direction parallel to the first surface of the substrate (horizontal direction along figure 4);
a molding layer (Molding Resin, See fig. 4, ref. no. 44 and paragraph 53-54) on the substrate;
and connection terminals (solder bumps, See fig. 4, ref. no. 42 and paragraph 52) between the semiconductor chip and the first surface of the substrate,
wherein the substrate has a recessed portion (recessed portion, See figs. 1-4, ref. no. DP and paragraphs 48-51) on the first surface,
the passive element overlaps the recessed portion vertically (the chip capacitor vertically over laps the recessed portion, See figs. 2-4, ref. nos. DP, 31) and includes a first side surface (right side surface of the cubic capacitor body of the chip capacitor, See figs. 3B, 4, ref. no. 31 and paragraph 50) facing a side surface of the semiconductor chip (left side surface of the semiconductor chip, See fig. 4, ref. no. 41. The examiner notes the semiconductor chip has a rectangular shape because the semiconductor chip occupies a rectangular shaped chip mounting area, See figs. 4, 16A, ref. no. CM and paragraph 43) and a second side surface (top surface of the cubic capacitor body of the chip capacitor, See figs. 3B, 4, ref. no. 31 and paragraph 50) perpendicular to the side surface of the semiconductor chip when viewed in a plan view,
the first side surface and the second side surface have a first width (the vertical dimension of right side surface of the cubic capacitor body shown, See fig. 4, ref. no. 31) and a second width (the horizontal dimension of the top surface of the cubic capacitor body, See fig. 4, ref. no. 31), respectively,
the first width is narrower than the second width (the vertical dimension of the right side surface of the cubic capacitor body is less than the horizontal dimension of the top surface of the cubic capacitor body, See fig. 4, ref. no. 31 and paragraph 50), and
the molding layer fills the recessed portion (the molding resin fill the recessed portion and the space between the recessed portion and the chip capacitor, See fig. 4, ref. no. DP, 31, 44) and surrounds side surfaces of the connection terminals (the molding resin surrounds the solder bumps, See fig. 4, ref. no. 42, 44).
Nakamura does not disclose an insulating pattern on an edge region of the first surface; the insulating pattern protrudes by 10 μm to 18 μm in a second direction perpendicular to the first surface of the substrate.
Choi discloses an insulating pattern on an edge region of the first surface (an under-fill dam formed along the outer edge of a substrate, See fig. 2, ref. no. 6, paragraphs 12 and 101-103) and the first insulating pattern protrudes in a second direction perpendicular to the first surface of the substrate (the under-fill dam extends in a vertical direction from the substrate, See fig. 2, ref. no. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Nakamura to include a first insulating pattern on an edge region of the first surface and the first insulating pattern protrudes in a second direction perpendicular to the first surface of the substrate as taught by Choi to prevent the molding resin from leaking out. (See Choi paragraph 4.)
The examiner notes that Choi discloses the under-fill dam may have a height equal to the distance between the substrate and the semiconductor chip (See paragraph 16). The examiner next notes that Nakamura discloses the semiconductor chip is connected to the wiring board through the solder bumps with the height of the solder bumps corresponding to the distance between the wiring board and the semiconductor chip (See fig. 4, ref. nos. 10, 41, 42 and paragraph 52) The examiners further notes that Choi teaches the height of the under-fill dam decreases as the distance between the substrate and the semiconductor chip decreases because Choi teaches the relationship of the height of the under-fill dam and the distance between the substrate and the semiconductor chip as being equal. The examiner now points out that Nakamura is silent with respect to the height of the solder bumps, however, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the insulating pattern protrude by 10 μm to 18 μm in a second direction perpendicular to the first surface of the substrate since it has been held that changes in dimensions are an obvious expedient and not a patentable distinction where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device. Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding Claim 18:
The combination of Nakamura and Choi discloses an upper surface of the insulating pattern is above a lower surface of the passive element (Nakamura discloses the top surface of the semiconductor chip is above the bottom surface of chip capacitor. See Nakamura, fig. 4 ref. nos. 31, 41. The examiner notes that the surface referred to as the bottom surface of the chip capacitor is the bottom surface the cubic capacitor body. Choi discloses the under-fill dam may have a height that is the same height as the outermost side of the semiconductor chip. See Choi paragraph 16. Thus, the under-fill dam will have an upper surface above a lower surface of the passive element.)
The examiner also notes that an upper surface of the insulating pattern is above a lower surface of the passive element would have been obvious to one of ordinary skill in the art before the effective filing date since it has been held that changes in dimensions are an obvious expedient and not a patentable distinction where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device. Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding Claim 19:
Nakamura discloses wherein the passive element includes at least one of a capacitor (chip capacitor, See fig. 4, ref. no. 31), an inductor, and a resistor.
Regarding Claim 20:
The combination of Nakamura and Choi discloses a length of the insulating pattern in the first direction is 50 µm or more (Nakamura discloses the length and the width of wiring board are greater than the length and the width of the chip capacitor. See Nakamura figs. 3B, ref. no. 31, fig. 4, ref. no. 10, 31, and paragraph 49. Nakamura also discloses the length of the chip capacitor is 1.0 mm and the width is 0.5 mm. See Nakamura paragraph 50. Therefore, the length and the width of wiring board are greater than 1.0 mm and 0.5 mm. Choi discloses the under-fill dam is formed along outer edge of a substrate (See Choi paragraph 12). Thus, the under-fill dam will have dimensions that correspond with the outer edge of the wiring board and the outer edge of the wiring board has a length greater than 50 µm.).
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US2011/0304016) in view of Choi et al. (US 2013/0063917) further in view Lin (US 5,436,203).
Regarding Claim 3:
The above stated combination of Nakamura and Choi disclose the above stated semiconductor package.
The above stated combination of Nakamura and Choi does not disclose the semiconductor chip includes a logic chip.
Lin discloses a microprocessor (See fig. 3, ref. no. 32 and col. 4 lines 20-32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Nakamura and Choi to include a microprocessor as taught by Lin so that semiconductor chip can execute programs. (See Choi paragraph 4.)
Regarding Claim 11:
The above stated combination of Nakamura and Choi disclose the above stated semiconductor package. Choi further discloses the first insulating pattern includes a solder resist (the under-fill dam includes a dry film solder resist, See Choi paragraph 12).
The above stated combination of Nakamura and Choi does not disclose a second insulating pattern between the first surface of the substrate and the first insulating pattern.
Lin discloses a second insulating pattern (solder resist on top surface of substrate and below dam structure, See fig. 4, ref. nos. 13, 26, 44 and col. 5 lines 35-46) between the first surface of the substrate and the first insulating pattern.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Nakamura and Choi to include a second insulating pattern between the first surface of the substrate and the first insulating pattern as taught by Lin in order to protect against short-circuits and corrosion.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US2011/0304016)
Regarding Claim 15:
Nakamura discloses wherein the recessed portion has a third width in the first direction (the horizontal dimension of the recessed portion, See figs. 3A-4, ref. no. DP). Nakamura also discloses the recess portion has a third width less than a length of the chip capacitor in the first direction (See figs. 3A-4, ref. nos. DP, 31). Nakamura does not disclose the third width is 70% to 90% of a length of the passive element in the first direction, however, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the third width is 70% to 90% of a length of the passive element in the first direction since it has been held that changes in dimensions are an obvious expedient and not a patentable distinction where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device. Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US2011/0304016) in view of Choi et al. (US 2013/0063917) further in view of Kwamoto et al. (US 2005/0013082).
Regarding Claim 19:
The above stated combination of Nakamura and Choi discloses the above state semiconductor package.
The above stated combination of Nakamura and Choi does not disclose wherein the passive element includes at least one of an inductor and a resistor.
Kwamoto discloses wherein the passive element include a resistor (resistance, See figs. 13A, 14A, ref. no. 1004 and paragraph 70).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Nakamura and Choi to include a resistance as taught by Kwamoto in order to reduce a power supply voltage to an operating voltage for a semiconductor chip.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899