DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 06/01/2026 amendments of claims 1, 11 and 16 have been noted and entered.
The 06/01/2026 cancellation of claim 18 is noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 7-10, filed 06/01/2026, with respect to the rejection(s) of claim(s) 1-5, 7-16 and 19-20 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. However, upon further consideration, a new ground(s) of rejection is made in view of Han, US 20220299887 A1 (Han).
Additionally, the indication of allowable subject matter of claims 6 and 17-18 detailed in the Non-Final Rejection of 03/26/2026 has been withdrawn in light of the new grounds of rejection disclosed below.
New Grounds of Rejection
New grounds of rejection, prior art reference Han, US 20220299887 A1 (Han) appears below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han, US 20220299887 A1 (Han).
Regarding claim 1; Lee teaches a semiconductor device, comprising:
a substrate (Han: Fig (5): 110) having a key region therein (OLR);
a device isolation layer (LS) on the key region (OLR);
first key patterns (First Version of Annotated Fig (4) shared in this OA: 122y and 132y within OLP1 and OLP2) on the device isolation layer ( Fig (5): LS); and
a dummy key pattern (First Version of Annotated Fig (4) shared in this OA: 128 = 128X + 128Y) extending between the first key patterns (122y within OLP1), which are adjacent to each other;
wherein the first key patterns (122y and 132y within OLP1 and OLP2) include a plurality of first sub-key patterns (122y and 132y);
wherein the dummy key pattern (126, 128 = 128X + 128Y, 136, 138 = 138X + 138Y) includes a separation structure (Fig (5): the body structure of 128X and 128Y), which extends into the device isolation layer (LS); and
wherein a first pitch (First Version of Annotated Fig (4) shared in this OA: First Pitch) between the plurality of first sub-key patterns (122y) is substantially the same as a second pitch (Second Pitch) between the separation structure (Annotated Fig (4) shared in this OA and Fig (5): the body structure of 128X and 128Y) and one of the plurality of first sub-key patterns (122y) adjacent thereto.
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Regarding claim 2; Han teaches all the limitations of the semiconductor device of Claim 1.
Han teaches further comprising: a second key pattern (Han: First Version of Annotated Fig (4) shared in this OA: 124x) extending between adjacent ones of the first key patterns (122y and 132y) and wherein the first key patterns (Fig (5): 122y and 132y) and the dummy key pattern (128) are positioned at a first level (the level at which the 122y, 132y and 128 are positioned vertically), and the second key pattern (124x) is positioned at a second level (the level at which 124x is positioned vertically) higher than the first level.
Regarding claim 3; Han teaches all the limitations of the semiconductor device of Claim 2
Further, Han teaches wherein a first interval (First Version of Annotated Fig (4) shared in this OA: First Interval) between one of the first key patterns (122y) adjacent to each other and the second key pattern (124x) is different from a second interval (Second Interval) between the second key pattern (124x) and another one of the first key patterns (132y) adjacent to each other.
Regarding claim 4; Han teaches all the limitations of the semiconductor device of claim 3.
Han teaches wherein the second key pattern (Han: First Version of Annotated Fig (4) shared in this OA: 124x) includes a plurality of second sub-key patterns (124x), and wherein each of the plurality of second sub-key patterns (124x) includes a conductive pattern and a barrier pattern surrounding the corresponding conductive pattern ([0051]: “[0051] The first overlay pattern group OPG1 (that is, the first lower sub-patterns 122x, the second lower sub-patterns 122y, the first upper sub-patterns 124x, and the second upper sub-patterns 124y) may each include tungsten (W),…. In some embodiments, the first overlay pattern group OPG1 may include a metal layer and a conductive barrier layer covering at least a portion of the metal layer.”).
Regarding claim 5; Han teaches all the limitations of the semiconductor device of claim 4.
Han teaches wherein a third pitch (Han: First Version of Annotated Fig (4) shared in this OA: Third Pitch) between the plurality of second sub-key patterns (124x) is substantially the same as the first pitch (First Pitch).
Regarding claim 6; Han teaches all the limitations of the semiconductor device of claim 1.
Han teaches wherein the dummy key pattern (Han: First Version of Annotated Fig (4) shared in this OA: 126, 128 = 128X + 128Y, 136, 138 = 138X + 138Y) includes a pair of separation structures (Fig (5): the bodies of 126 and 136) adjacent to each other; and wherein a third pitch (First Version of Annotated Fig (4) shared in this OA: Third Pitch – 2) between the pair of separation structures (the bodies of 126 and 136) is substantially the same as the first pitch (First Version of Annotated Fig (4) shared in this OA: First Pitch).
Regarding claim 7; Han teaches all the limitations of the semiconductor device of claim 1.
Han teaches wherein a bottom of the separation structure (Han: Fig (5): bottom of the bodies of 126, 128, 136 and 138) is higher than a front surface of the substrate (110).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 10 are rejected under 35 U.S.C. 103 as being unpatentable over Han, US 20220299887 A1 (Han) in view of Kim et al, KR 20220168241 A (Kim).
Regarding claim 10; Han teaches all the limitations of the semiconductor device of claim 1.
However, Han does not teach wherein the first key patterns further include a plurality of capping patterns respectively provided on the plurality of first sub- key patterns; and wherein upper surfaces of the plurality of capping patterns are coplanar with an upper surface of the separation structure.
Kim teaches wherein the first key patterns (Kim: Fig (12b): GE1, GE2 and GE3) further include a plurality of capping patterns (GP) respectively provided on the plurality of first sub- key patterns (GE1, GE2 and GE3); and wherein upper surfaces of the plurality of capping patterns (GP) are coplanar with an upper surface of the separation structure (110).
Han and Kim are considered analogous art. Thus, it would have been obvious, prior to the effective filing date, to a person having ordinary skill in the art, to modify to modify Han by using a capping layer on the sub-key patterns as disclosed in Kim to improve the insulation of the gate electrodes which leads to a better performing device.
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Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Han, US 20220299887 A1 (Han) in view of Chern et al, US 20160086949 A1 (Chern) in further view of Kim et al, KR 20220168241 A (Kim).
Regarding claim 11; A semiconductor device, comprising:
a substrate (Han: Fig (5): 110) including a key region (OLR);
a device isolation layer (LS) on the key region (OLR);
first key patterns (Second Version of Annotated Fig (4) shared in this OA: 122y and 132y within OLP1 and OLP2) on the device isolation layer (Fig (5): LS);
a dummy key pattern (Second Version of Annotated Fig (4) shared in this OA: 126, 128 = 128X + 128 Y, 136 and 138 = 138X + 138Y) extending between the first key patterns (122y and 132y within OLP1 and OLP2) which are adjacent to each other; and
a second key pattern (124x) extending between the adjacent first key patterns (122y and 132y within OLP1 and OLP2);
wherein the first key patterns (122y and 132y within OLP1 and OLP2) are spaced apart from each other by the dummy key pattern (126, 128 = 128X + 128 Y, 136 and 138 = 138X + 138Y);
wherein each of the first key patterns (122y and 132y within OLP1 and OLP2) includes a first sub-key pattern (122y and 132y), a first spacer on a sidewall of the first sub-key pattern, and a capping pattern on the first sub-key pattern (122y and 132y in OLP1 and OLP2);
wherein the dummy key pattern (126, 128 = 128X + 128 Y, 136 and 138 = 138X + 138Y) includes a separation structure (the body structure of the dummy key pattern) and a second spacer on a sidewall of the separation structure;
wherein an upper surface of the capping pattern is substantially coplanar with an upper surface of the separation structure;
wherein a first pitch (Second Version of Annotated Fig (4) shared in this OA: First Pitch) between the adjacent first sub-key pattern (122y) and the second key pattern (124x) is different from a second pitch (Second Pitch) between the second key pattern (124x) and the separation structure (128Y); and
wherein a third pitch (Third Pitch) between first sub-key patterns (122y) of the first key patterns (122y and 132y) is substantially the same as a fourth pitch (Fourth Pitch) between the separation structure (126) and one of the first sub-key patterns (122y).
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Han does not teach a first spacer on a sidewall of the first sub-key pattern; a second spacer on a sidewall of the separation structure; and wherein an upper surface of the capping pattern is substantially coplanar with an upper surface of the separation structure.
Chern teaches a first spacer (Chern: Annotated Fig (5) shared in this OA: 256) on a sidewall of the first sub-key pattern (300A, 300B, 300C), a second spacer (240) on a sidewall of the separation structure (245).
Han and Chern are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Han by using the spacers on the sidewalls of the first sub-key pattern and separation structure as disclosed in Chern to enhance the insulation of these conductive structures thus leading to a more reliable device.
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Han in view of Chern does not teach a capping pattern on the first sub- key pattern; and wherein an upper surface of the capping pattern is substantially coplanar with an upper surface of the separation structure.
Kim teaches a capping pattern (Kim: Fig (12b): GP) on the first sub- key pattern (GE1, GE2 and GE3); and wherein an upper surface of the capping pattern (GP) is substantially coplanar with an upper surface of the separation structure (110).
Han in view of Chern and Kim are considered analogous art. Thus, it would have been obvious, prior to the effective filing date, to a person having ordinary skill in the art, to modify to modify Han in view of Chern by using a capping layer on the sub-key patterns as disclosed in Kim to improve the insulation of the gate electrodes which leads to a better performing device.
Regarding claim 12; Han in view of Chern in further view of Kim teaches all the limitations of the semiconductor device of Claim 11
Han further comprising: a second key pattern (Han: Second Version of Annotated Fig (4) shared in this OA: 124x) extending between the adjacent first key patterns (122y and 132y within OLP1 and OLP2); wherein the first key patterns (122y) and the dummy key pattern (126) are positioned at a first level (Fig (5): vertical level at which 122y and 126 are positioned); and wherein the second key pattern (124x) is positioned at a second level (vertical level at which 124x is positioned) higher than the first level.
Regarding claim 13; Han in view of Chern in further view of Kim teaches all the limitations of the semiconductor device of Claim 12
Han teaches wherein a first interval (Han: First Version of Annotated Fig (4) shared in this OA: First Interval) between one of the first key patterns (122y) adjacent to each other and the second key pattern (124x) is different from a second interval (Second Interval) between the second key pattern (124x) and another one of the first key patterns (132y) adjacent to each other.
Regarding claim 14; Han teaches all the limitations of the semiconductor device of claim 12.
Han teaches wherein the second key pattern (Han: First or Second Version of Annotated Fig (4) shared in this OA: 124x) includes a plurality of second sub-key patterns (124x); and wherein each of the plurality of second sub-key patterns (124x) includes a conductive pattern and a barrier pattern surrounding the corresponding conductive pattern ([0051]: “[0051] The first overlay pattern group OPG1 (that is, the first lower sub-patterns 122x, the second lower sub-patterns 122y, the first upper sub-patterns 124x, and the second upper sub-patterns 124y) may each include tungsten (W),…. In some embodiments, the first overlay pattern group OPG1 may include a metal layer and a conductive barrier layer covering at least a portion of the metal layer.”).
Regarding claim 15; Han in view of Chern in further view of Kim teaches all the limitations of the semiconductor device of Claim 11
Han teaches wherein the first sub-key pattern (Han: First Version of Annotated Fig (4) shared in this OA: 122y) includes a plurality of first sub-key patterns (122y); wherein the separation structure (126, 128 = 128X + 128Y, 136, 138 = 138X + 138Y) includes a plurality of separation structures (126, 128 = 128X + 128Y, 136, 138 = 138X + 138Y); and wherein a pitch (First Pitch) between the plurality of first sub-key patterns (122y) is substantially the same as a pitch (Third Pitch -2) between the separation structures (126 and 136).
Allowable Subject Matter
Claims 8-9, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8; Han alone or in combination with other available art does not teach further comprising: an active pattern on a logic cell region of the substrate; a channel pattern on the active pattern; a source/drain pattern electrically connected to the channel pattern; and a gate electrode on the channel pattern; wherein the gate electrode includes a plurality of gate electrodes; and wherein a third pitch between the plurality of gate electrodes is smaller than the first pitch. More precisely there is no available art that compares the first pitch between two adjacent first key patterns to a third pitch between the gate electrodes in a manner that facilitates the comparison in a reasonable manner in combination with the limitations above.
Claim 9 is objected for its dependence on claim 8.
Claims 16-17 and 19-20 are allowable over prior art. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 16; Park alone or in combination with other art teaches A semiconductor device, comprising: a substrate including a key region; a device isolation layer on the key region; a first single diffusion break and a second single diffusion break on the device isolation layer; a plurality of first sub-key patterns arranged between the first and second single diffusion breaks; and a second sub-key pattern extending between the second single diffusion break and one of the plurality of first sub-key patterns that is adjacent to the second single diffusion break.
However, Park alone or in combination with other available art does not teach wherein a first pitch between the adjacent first sub-key pattern and the second sub-key pattern is different from a second pitch between the second sub-key pattern and the second single diffusion break wherein the first sub-key patterns and the first and second single diffusion breaks are positioned at a first level, and wherein the second sub-key pattern is positioned at a second level higher than the first level. In other words the combination of the first and second pitches comparison along with the positioning of the sub-key patterns and the diffusion break region positions is not taught in any available art in a manner that can be reasonably combined with the above recited limitations.
Claims 17 and 19-20 are allowable for their dependence on an allowable claim.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Park et al, US 20160268414 A1 (Park); discloses gate structures along with diffusion break regions.
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/M.K./Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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