DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The instant application claim of the priority date of 03/15/2023 of the foreign application KR 10-2023-0034197 is noted and entered. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/22/2023 was filed after the mailing date of the application on 12/22/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al, KR 20160102788 A (Park)
Regarding claim 16; Park teaches a semiconductor device, comprising: a substrate (10) including a key region (Key Region – see annotated Fig (8) of Park shared in this OA); a device isolation layer (70) on the key region (Key Region – see annotated Fig (8) of Park shared in this OA); a first single diffusion brake (IG11) (see the specification of Park: “On the other hand, the insulating gate IG11 can be used for a single diffusion break…”) and a second single diffusion brake (IG12) (see the specification of Park: “The insulating gate IG12 may also be used for a single diffusion brake application…”) on the device isolation layer (70); a plurality of first sub-key patterns (First Sub-Key Pattern – see annotated Fig (8) of Park shared in this OA) arranged between the first (IG11) and second single diffusion brakes (IG12); and a second sub key pattern patterns (Second Sub-Key Pattern – see annotated Fig (8) of Park shared in this OA) extending between the second single diffusion break (IG12) and one of the plurality of first sub-key patterns (First Sub-Key Pattern – see annotated Fig (8) of Park shared in this OA) that is adjacent to the second single diffusion break (IG12); and wherein a first pitch (First Pitch – see annotated Fig (8) of Park shared in this OA) between the adjacent first sub-key pattern (First Sub-Key Pattern – see annotated Fig (8) of Park shared in this OA) and the second sub-key pattern (Second Sub-Key Pattern – see annotated Fig (8) of Park shared in this OA) is different from a second pitch (Second Pitch – see annotated Fig (8) of Park shared in this OA) between the second sub-key pattern (Second Sub-Key Pattern – see annotated Fig (8) of Park shared in this OA) and the second single diffusion (IG12) break.
PNG
media_image1.png
971
828
media_image1.png
Greyscale
PNG
media_image2.png
600
1010
media_image2.png
Greyscale
Regarding claim 19; Park teaches further comprising: a first spacer (MG1) on a sidewall of each of the plurality of first sub-key patterns (First Sub-Key Pattern – see annotated Fig (8) of Park shared in this OA); and a second spacer (50) on a sidewall of each of the first (IG11) and second (IG12) single diffusion brakes.
Regarding claim 20; Park teaches wherein the second sub-key pattern (Second Sub-Key Pattern – see annotated Fig (8) of Park shared in this OA) includes a conductive pattern (MG2) and a barrier pattern (MG1) surrounding the conductive pattern (MG2) (see the specification of Park: “The first metal layer MG1 may include at least one of TiN, TaN, TiC, TiAlC, and TaC, for example. The second metal layer MG2 may include, for example, W or Al. However, the present invention is not limited thereto, and the configurations of the first metal layer MG1 and the second metal layer MG2 may be modified in different ways.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20190206867 A1 (Lee) in view of Chern et al, US 20160086949 A1 (Chern).
Regarding claim 1; Lee teaches a semiconductor device, comprising: a substrate (100) having a key region therein (R1); a device isolation layer (103) on the key region; first key patterns (101) on the device isolation layer (103); wherein the first key patterns (101) include a plurality of first sub-key patterns (101).
PNG
media_image3.png
860
767
media_image3.png
Greyscale
PNG
media_image4.png
885
717
media_image4.png
Greyscale
Lee does not teach a dummy key pattern extending between the first key patterns, which are adjacent to each other; wherein the dummy key pattern includes a separation structure, which extends into the device isolation layer and through at least one of the plurality of first sub-key patterns; and wherein a first pitch between the plurality of first sub-key patterns is substantially the same as a second pitch between the separation structure and one of the plurality of first sub-key patterns adjacent thereto.
Chern teaches a dummy key pattern ((300D1), (300D2), (300D3) and (300D4)) extending between the first key patterns ((300A), (300B) and (300C)), which are adjacent to each other; wherein the dummy key pattern ((300D1), (300D2), (300D3) and (300D4)) includes a separation structure (245), which extends into the device isolation layer (240) and through at least one of the plurality of first sub-key patterns ((300A), (300B) and (300C)); and wherein a first pitch (First Pitch – see annotated Fig (5) of Chern shared in this OA) between the plurality of first sub-key patterns ((300A), (300B) and (300C)), is substantially the same as a second pitch (Second Pitch – see annotated Fig (5) of Chern shared in this OA) between the separation structure (245) and one of the plurality of first sub-key patterns ((300A), (300B) and (300C)), adjacent thereto.
Lee and Chern are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee by using the dummy key pattern disclosed in Chern to avoid the dishing phenomenon that happens when constructing gate electrodes and thus leading to a more reliable device.
PNG
media_image5.png
618
850
media_image5.png
Greyscale
Regarding claim 7; Lee does not teach wherein a bottom of the separation structure is higher than a front surface of the substrate.
Chern teaches wherein a bottom of the separation structure (245) is higher than a front surface of the substrate (202) (see Fig (5) of Chern shared in this OA).
Lee and Chern are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee by making the bottom of the separation structure higher than a front surface fo the substrate to improve the outcome of the etching processes against the dishing phenomenon for the device gates as disclosed in Chern leading to a more reliable device.
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20190206867 A1 (Lee) in view of Chern et al, US 20160086949 A1 (Chern) in further view of Han, US 20220299887 A1 (Han).
Regarding claim 2; Lee does not teach further comprising: a second key pattern extending between adjacent ones of the first key patterns; and wherein the first key patterns and the dummy key pattern are positioned at a first level, and the second key pattern is positioned at a second level higher than the first level.
Chern teaches further comprising: a second key pattern (Second Key Pattern – see annotated Fig (4C) of Chern shared in this OA) extending between adjacent ones of the first key patterns (First Key Pattern – see annotated Fig (4C) in this OA).
Lee and Chern are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee by adding a second key pattern between adjacent first key patterns to help increase the density of components in the device leading to a better performing device.
PNG
media_image6.png
760
1130
media_image6.png
Greyscale
Lee in view of Chern does not teach wherein the first key patterns and the dummy key pattern patterns are positioned at a first level, and the second key pattern is positioned at a second level higher than the first level.
Han teaches wherein the first key patterns and the dummy key pattern patterns (238) are positioned at a first level, and the second key (132y) pattern is positioned at a second level higher than the first level.
Lee in view of Chern and Han are considered analogous art. Thus, it would have been obvious to a person having ordinary skill in the art, to modify Lee in view of Chern by constructing the second key pattern at a higher level than the dummy key pattern to improve the outcomes of etching process by protecting the key patterns from the dishing phenomenon known to destroy gate electrodes thus leading to a better performing device.
PNG
media_image7.png
807
1141
media_image7.png
Greyscale
PNG
media_image8.png
794
1121
media_image8.png
Greyscale
Regarding claim 3; Lee does not teach wherein a first interval between one of the first key patterns adjacent to each other and the second key pattern is different from a second interval between the second key pattern and another one of the first key patterns adjacent to each other.
Chern teaches wherein a first interval (First Interval – see annotated Fig (4C) of Chern shared in this OA) between one of the first key patterns (First Key Pattern – see annotated Fig (4C) of Chern shared in this OA) adjacent to each other and the second key pattern (Second Key Pattern – see annotated Fig (4C) of Chern shared in this OA) is different from a second interval (Second Interval – see annotated Fig (4C) of Chern shared in this OA) between the second key pattern (Second Key Pattern – see annotated Fig (4C) of Chern shared in this OA) and another one of the first key patterns (First Key Pattern – see annotated Fig (4C) of Chern shared in this OA) adjacent to each other.
Lee and Chern are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee by using different intervals between the first and second key patterns to increase the density of components in the device leading to a better performing device.
Regarding claim 4; Lee in view of Chern does not teach wherein the second key pattern includes a plurality of second sub-key patterns, and wherein each of the plurality of second sub-key patterns includes a conductive pattern and a barrier pattern surrounding the corresponding conductive pattern.
Han teaches wherein the second key pattern (132y) includes a plurality of second sub-key patterns (132y), and wherein each of the plurality of second sub-key patterns (132y) includes a conductive pattern and a barrier pattern surrounding the corresponding conductive pattern. (see paragraph [0062] of the specification of Han: “[0062] The second overlay pattern group OPG2 (that is, the third lower sub-patterns 132x, the fourth lower sub-patterns 132y, the third upper sub-patterns 134x and the fourth upper sub-patterns 134y) may each include W, WN, Au, Ag, Cu, Al, TiAlN, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, ITO, an alloy thereof, or a combination thereof. In some embodiments, the second overlay pattern group OPG2 may include a metal layer and a conductive barrier layer covering at least a portion of the metal layer. The barrier layer may include, for example, Ti, TiN, Ta, TaN, or a combination thereof.”)
Lee in view of Chern are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee in view of Chern by including a conductive layer and a barrier pattern in the second key patterns as disclosed in Han to improve the conductivity of the structure leading to a better performing device.
Regarding claim 5; Lee teaches wherein a third pitch (Third Pitch – see annotated Fig (2A) of Lee shared in this OA) between the plurality of second sub-key patterns is substantially the same as the first pitch (First Pitch – see annotated Fig (2A) of Lee shared in this OA).
PNG
media_image9.png
885
719
media_image9.png
Greyscale
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20190206867 A1 (Lee) in view of Chern et al, US 20160086949 A1 (Chern) in further view of Xu et al, US 10985161 B2 (Xu).
Regarding claim 8; Lee in view of Chern does not teach further comprising: an active pattern on a logic cell region of the substrate; a channel pattern on the active pattern; a source/drain pattern electrically connected to the channel pattern; and a gate electrode on the channel pattern; wherein the gate electrode includes a plurality of gate electrodes; and wherein a third pitch between the plurality of gate electrodes is smaller than the first pitch.
Xu teaches further comprising: an active pattern (Active Region R1 – see annotated Fig (1B) of Xu shared in this OA) on a logic cell region of the substrate (100); a channel pattern ((112), (114) and ((116)) on the active pattern; a source/drain pattern (S/D) electrically connected to the channel pattern ((112), (114) and ((116)); and a gate electrode (124) on the channel pattern ((112), (114) and ((116)); wherein the gate electrode (124) includes a plurality of gate electrodes (124); and wherein a third pitch (Third Pitch – see annotated Fig (1B) of Xu shared in this OA) between the plurality of gate electrodes (124) is smaller than the first pitch (First Pitch – see annotated Fig (1B) of Xu shared in this OA).
Lee in view of Chern and Xu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee in view of Chern by constructing the gate structures and channels as disclosed in Xu to improve the functionality of the device.
PNG
media_image10.png
726
920
media_image10.png
Greyscale
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20190206867 A1 (Lee) in view of Chern et al, US 20160086949 A1 (Chern) in further view of Xu et al, US 10985161 B2 (Xu) in further view of Wong et al, On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node, Nanomaterials 2022, 12(10), 1739; https://doi.org/10.3390/nano12101739.
Regarding claim 9; Lee in view of Chern does not teach wherein the channel pattern includes a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other.
Xu teaches wherein the channel pattern ((112), (114) and ((116)) includes a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other (see annotated Fig (1B) of Xu shared in this OA).
Lee in view of Chern and Xu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to modify Lee in view of Chern by using the plurality of semiconductor patterns vertically stacked and spaced apart as disclosed in Xu to improve the performance of the device.
Lee in view of Chern in further view of Xu does not teach wherein the gate electrode surrounds a top surface, a bottom surface, and both sidewalls of each of the plurality of semiconductor patterns.
Wong teaches wherein the gate electrode (Gate Electrode – see annotated Fig (1)-(b) of Wong shared in this OA) surrounds a top surface, a bottom surface, and both sidewalls of each of the plurality of semiconductor patterns (Semiconductor Patterns – see annotated Fig (1)-(b) of Wong shared in this OA).
Lee in view of Chern in further view of Xu and Wong are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art, to modify Lee in view of Chern in further view of Xu by using the gate-all-around transistor design disclosed in Wong to improve the control of the currents through the transistor and improve its efficiency.
PNG
media_image11.png
904
1030
media_image11.png
Greyscale
Claims 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20190206867 A1 (Lee) in view of Chern et al, US 20160086949 A1 (Chern) in further view of Kim et al, KR 20220168241 A (Kim).
Regarding claim 10; Lee in view of Chern does not disclose wherein the first key patterns further include a plurality of capping patterns respectively provided on the plurality of first sub- key patterns; and wherein upper surfaces of the plurality of capping patterns are coplanar with an upper surface of the separation structure.
Kim teaches wherein the first key patterns ((GE1), (GE2) and (GE3) – see Fig (12b) of Kim shared in this OA)) further include a plurality of capping patterns ((GP) – see Fig (12b) of Kim shared in this OA) respectively provided on the plurality of first sub- key patterns ((GE1), (GE2) and (GE3) – see Fig (12b) of Kim shared in this OA)); and wherein upper surfaces of the plurality of capping patterns (GP) are coplanar with an upper surface of the separation structure (110).
Lee in view of Chern and Kim are considered analogous art. Thus, it would have been obvious, prior to the effective filing date, to a person having ordinary skill in the art, to modify to modify Lee in view of Chern by using a capping layer on the sub-key patterns as disclosed in Kim to improve the insulation of the gate electrodes which leads to a better performing device.
PNG
media_image12.png
697
871
media_image12.png
Greyscale
Regarding claim 11; Lee teaches a semiconductor device, comprising: a substrate including a key region (R1); a device isolation layer (103) on the key region (R1); first key patterns (101) on the device isolation layer (103); wherein each of the first key patterns (101) includes a first sub-key pattern (101), a first spacer (102) on a sidewall of the first sub-key pattern (101).
Lee does not teach a dummy key pattern extending between the first key patterns, which are adjacent to each other; wherein the first key patterns are spaced apart from each other by the dummy key pattern; wherein the dummy key pattern includes a separation structure and a second spacer on a sidewall of the separation structure; and wherein an upper surface of the capping pattern is substantially coplanar with an upper surface of the separation structure.
Chern teaches a dummy key pattern ((300D1), (300D2), (300D3) and (300D4)) extending between the first key patterns ((300A), (300B) and (300C)), which are adjacent to each other; wherein the first key patterns ((300A), (300B) and (300C)) are spaced apart from each other by the dummy key pattern ((300D1), (300D2), (300D3) and (300D4)); wherein the dummy key pattern ((300D1), (300D2), (300D3) and (300D4)) includes a separation structure (245) and a second spacer (240) on a sidewall of the separation structure (245).
Lee and Chern are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee by using the dummy key pattern disclosed in Chern to avoid the dishing phenomenon that happens when constructing gate electrodes and thus leading to a more reliable device.
Lee in view of Chern does not teach a capping pattern on the first sub- key pattern; and wherein an upper surface of the capping pattern is substantially coplanar with an upper surface of the separation structure.
Kim teaches a capping pattern ((GP) – see Fig (12b) of Kim shared in this OA)) on the first sub- key pattern ((GE1), (GE2) and (GE3) – see Fig (12b) of Kim shared in this OA)); and wherein an upper surface of the capping pattern ((GP) – see Fig (12b) of Kim shared in this OA))is substantially coplanar with an upper surface of the separation structure (110).
Lee in view of Chern and Kim are considered analogous art. Thus, it would have been obvious, prior to the effective filing date, to a person having ordinary skill in the art, to modify to modify Lee in view of Chern by using a capping layer on the sub-key patterns as disclosed in Kim to improve the insulation of the gate electrodes which leads to a better performing device.
Regarding claim 12; Lee does not teach further comprising: a second key pattern extending between the adjacent first key patterns; wherein the first key patterns and the dummy key pattern are positioned at a first level, and wherein the second key pattern is positioned at a second level higher than the first level.
Chern teaches further comprising: a second key pattern (Second Key Pattern – see annotated Fig (4C) of Chern shared in this OA) extending between the adjacent first key patterns (First Key Pattern – see annotated Fig (4C) in this OA).
Lee and Chern are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee by adding a second key pattern between adjacent first key patterns to help increase the density of components in the device leading to a better performing device.
Lee in view of Chern does not teach wherein the first key patterns and the dummy key pattern patterns are positioned at a first level, and wherein the second key pattern is positioned at a second level higher than the first level.
Han teaches wherein the first key patterns and the dummy key pattern patterns (238) are positioned at a first level, and wherein the second key (132y) pattern is positioned at a second level higher than the first level.
Lee in view of Chern and Han are considered analogous art. Thus, it would have been obvious to a person having ordinary skill in the art, to modify Lee in view of Chern by constructing the second key pattern at a higher level than the dummy key pattern to to improve the outcomes of etching process by protecting the key patterns from the dishing phenomenon known to destroy gate electrodes thus leading to a better performing device.
Regarding claim 13; Lee does not teach wherein a first interval between one of the first key patterns adjacent to each other and the second key pattern is different from a second interval between the second key pattern and another one of the first key patterns adjacent to each other.
Chern teaches wherein a first interval (First Interval – see annotated Fig (4C) of Chern shared in this OA) between one of the first key patterns (First Key Pattern – see annotated Fig (4C) of Chern shared in this OA) adjacent to each other and the second key pattern (Second Key Pattern – see annotated Fig (4C) of Chern shared in this OA) is different from a second interval (Second Interval – see annotated Fig (4C) of Chern shared in this OA) between the second key pattern (Second Key Pattern – see annotated Fig (4C) of Chern shared in this OA) and another one of the first key patterns (First Key Pattern – see annotated Fig (4C) of Chern shared in this OA) adjacent to each other.
Lee and Chern are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee by using different intervals between the first and second key patterns to increase the density of components in the device leading to a better performing device.
Regarding claim 14; Lee in view of Chern does not teach wherein the second key pattern includes a plurality of second sub-key patterns, and wherein each of the plurality of second sub-key patterns includes a conductive pattern and a barrier pattern surrounding the corresponding conductive pattern.
Han teaches wherein the second key pattern (132y) includes a plurality of second sub-key patterns (132y), and wherein each of the plurality of second sub-key patterns (132y) includes a conductive pattern and a barrier pattern surrounding the corresponding conductive pattern. (see paragraph [0062] of the specification of Han: “[0062] The second overlay pattern group OPG2 (that is, the third lower sub-patterns 132x, the fourth lower sub-patterns 132y, the third upper sub-patterns 134x and the fourth upper sub-patterns 134y) may each include W, WN, Au, Ag, Cu, Al, TiAlN, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, ITO, an alloy thereof, or a combination thereof. In some embodiments, the second overlay pattern group OPG2 may include a metal layer and a conductive barrier layer covering at least a portion of the metal layer. The barrier layer may include, for example, Ti, TiN, Ta, TaN, or a combination thereof.”)
Lee in view of Chern are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee in view of Chern by including a conductive layer and a barrier pattern in the second key patterns as disclosed in Han to improve the conductivity of the structure leading to a better performing device.
Regarding claim 15; Lee does not teach wherein the first sub-key pattern includes a plurality of first sub-key patterns; wherein the separation structure includes a plurality of separation structures; and wherein a pitch between the plurality of first sub- key patterns is substantially the same as a pitch between the separation structures.
Chern teaches wherein the first sub-key pattern ((300A), (300B) and (300C)) includes a plurality of first sub-key patterns ((300A), (300B) and (300C)); wherein the separation structure (245) includes a plurality of separation structures (245); and wherein a pitch (First Pitch – see annotated Fig (5) of Chern shared in this OA) between the plurality of first sub- key patterns ((300A), (300B) and (300C)) is substantially the same as a pitch (second Pitch – see annotated Fig (5) of Chern shared in this OA) between the separation structures (245).
Lee and Chern are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee by using the separation structures at the pitches disclosed in Chern to improve the device’s resistance towards the dishing phenomenon during etching processes leading to a more reliable device.
Allowable Subject Matter
Claims 6, and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6; The art made of record alone or along with other available art does not teach wherein the dummy key pattern includes a pair of separation structures adjacent to each other; and wherein a third pitch between the pair of separation structures is substantially the same as the first pitch.
Regarding claim 17; The art made of record alone or in combination with other available art does not teach wherein a third pitch between the plurality of first sub-key patterns is substantially the same as a fourth pitch between the second single diffusion break and the one of the plurality of first sub-key patterns.
Regarding claim 18; The art made of record alone or in combination with other available art does not teach wherein the first sub-key patterns and the first and second single diffusion breaks are positioned at a first level, and the second sub-key pattern is positioned at a second level higher than the first level.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.K./Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815