DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2 corresponding to claims 9-20 and described by Fig (5) of the instant application in the reply filed on 03/20/2026 is acknowledged.
Claims 1-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/20/2026.
Additionally, claims 14-15 have been withdrawn from further consideration for containing limitations which are mutually exclusive with the elected Species 2 descried by Fig (5):
Regarding claim 14; claim 14 contains the limitations: “… wherein a height from a bottom face of the element isolation film to a bottom face of the sub-element isolation film in the third direction is less than a height from the bottom face of the sub-element isolation film to an upper face of the sub-element isolation film.” (emphasis added). Comparing this limitation to Fig (5) of the instant application shows that such a limitation is contradictory to what is shown in the figure where H1 is visibly larger than H2. The relationship between the two heights H1 and H2 is captured correctly in the language of claim 13.
Regarding claim 15; claim 15 contains the limitations: “…wherein a height from a bottom face of the element isolation film to a bottom face of the sub-element isolation film in the third direction is the same as a height from the bottom face of the sub-element isolation film to an upper face of the sub-element isolation film.” (emphasis added). Comparing this limitation to Fig (5) of the instant application shows that such a limitation is contradictory to what is shown in the figure where H1 is visibly larger than H2.
Thus, claims 14-15 have been withdrawn from further consideration. The relationship between the two heights H1 and H2 is captured correctly in the language of claim 13.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/22/2023 was filed after the mailing date of the application on 12/22/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 9-10 and 12-13 are rejected under 35 U.S.C. 102(a)1 as being anticipated by Chang et al, US 20160343706 A1 (Chang).
Regarding claim 9; Chang teaches a semiconductor memory device (Chang: [0002]) comprising:
a substrate (Annotated Fig (1H) shared in this OA: 102+114+126+128) that includes an active region (Active Region) including a plurality of sub-regions (Sub-Region-A, Sub-Region-B);
an element isolation film (114+126+128) which is disposed in the substrate (102+114+126+128) and defines the active region (Active Region); and
a plurality of sub-element isolation films (126, 128) which are disposed in the substrate (102+114+126+128), extend in a first direction (X-direction), are spaced apart from each other in a second direction (Y-direction), and defines the plurality of sub-regions (Sub-Region-A, Sub-Region-B), wherein a height of each of the plurality of sub-element isolation films (126, 128) in a third direction (Z-direction) is less than a height of the element isolation film (114+126+128) in the third direction (Z-direction), and wherein widths of the plurality of sub-element isolation films (126, 128) in the second direction (Y-direction) are less than widths of the plurality of sub-
PNG
media_image1.png
864
1049
media_image1.png
Greyscale
regions (Sub-Region-A, Sub-Region-B) in the second direction (Y-direction).
Regarding claim 10; Chang teaches all the limitations of the semiconductor memory device of claim 9.
Chang teaches further comprising: a gate structure (Chang: Annotated Fig (1H) shared in this OA: 134’b+136’b+138’b) which is disposed on the substrate (102+114+126+128) and extends in the second direction (Y-direction), wherein the gate structure (134’b+136’b+138’b) includes a gate insulating film (134’b), a gate stack pattern (136’b+138’b), and a gate capping pattern (158b) which are sequentially stacked (see annotated Fig (1H) shared in this OA) in the third direction (Z-direction), wherein the gate insulating film (134’b) includes a first portion (First Portion) that overlaps an upper face of the active region (Active Region), and a second portion (Second Portion) that overlaps an upper face of the element isolation film (114+126+128), and wherein a thickness of the first portion (First Portion) in the third direction (Z-direction) is the same as a thickness of the second portion (Second Portion) in the third direction (Z-direction).
Regarding claim 12; Chang teaches all the limitations of the semiconductor memory device of claim 9.
Further, Chang teaches wherein widths of each of the plurality of the sub-element isolation films (Chang: Annotated Fig (1H): 126+128) in the second direction (Y-direction) are less than widths of each of the plurality of the sub-regions (Sub-Region-A, Sub-Region-B) in the second direction (Y-direction).
Regarding claim 13; Chang teaches all the limitations of the semiconductor memory device of claim 9.
Further, Chang teaches wherein a height from a bottom face of the element isolation film (Chang: Annotated Fig (1H): 114+126+128) to a bottom face of the sub-element isolation film (126) in the third direction (Z-direction) is greater than a height from the bottom face of the sub-element isolation film (126) to an upper face of the sub-element isolation film (126).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al, US 20160343706 A1 (Chang) in view of Takeuchi et al, US 20090194807 A1 (Takeuchi).
Regarding claim 11; Chang teaches all the limitations of the semiconductor memory device of claim 10.
However, Chang does not teach wherein the gate insulating film further comprises a third portion that overlaps an upper face of the sub-element isolation film, and wherein a thickness of the third portion in the third direction is the same as thicknesses of the first portion and the second portion in the third direction.
Takeuchi teaches wherein the gate insulating film (Takeuchi: Annotated Fig (3) shared in this OA: 34) further comprises a third portion (Third Portion) that overlaps an upper face of the sub-element isolation film (50), and wherein a thickness of the third portion (Third Portion) in the third direction (Z-direction) is the same as thicknesses of the first portion (First Portion) and the second portion (Second Portion) in the third direction (Z-direction).
Chang and Takeuchi are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to modify Chang by constructing the gate insulating film as disclosed in Takeuchi to improve the insulation of the gate and thus lead to a more reliable device.
PNG
media_image2.png
880
813
media_image2.png
Greyscale
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al, US 20160343706 A1 (Chang) in view of Tsai, US 20240098978 A1 (Tsai) in further view of Takeuchi et al, US 20090194807 A1 (Takeuchi).
Regarding claim 16; Chang teaches a semiconductor memory device (Chang: [0002]) comprising:
a substrate (Annotated Fig (1H) shared in this OA: 102+114+126+128) including a cell array region (Active Region) and a peripheral region (Peripheral Region);
a plurality of memory cells which are disposed in the cell array region (Active Region), and each include a word line, a bit line, and a capacitor;
a peripheral element isolation film (114+126+128) which is disposed in the peripheral region (Peripheral Region) of the substrate (102+114+126+128) and defines a peripheral active region;
at least one or more recesses (recess in which 126+128 films are deposited) disposed in the peripheral active region (Peripheral Region);
a peripheral sub-element isolation film (126) disposed in the recess (recess in which 126+128 films are deposited); and
a plurality of transistors which are disposed on the substrate (102+114+126+128) of the peripheral region (Peripheral Region), and control operations of the plurality of memory cells, wherein a height from an upper face of the substrate (102+114+126+128) to a bottom face of the peripheral element isolation film (114+126+128) is greater than a height from an upper face of the substrate (102+114+126+128) to a bottom face of the peripheral sub-element isolation film (126).
While Chang teaches a plurality of memory cell structures it fails to disclose that each include a word line, a bit line, and a capacitor.
Tsai teaches each include a word line (Tsai: Fig (3): 12e2;[0070]), a bit line (32), and a capacitor (34; [0104]: “The memory element 34 may be a capacitor”).
Chang and Tsai are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chang by constructing the word line and bit line disclosed in Tsai to make establishing electrical connections with the memory device easier thus leading to a more reliable device production process.
PNG
media_image3.png
700
935
media_image3.png
Greyscale
Chang in view of Tsai does not teach a plurality of transistors which control the operations of the memory cells.
However, Takeuchi teaches a plurality of transistors (Takeuchi: Figs (1)-(3): CG1…CGn) which control the operations of the memory cells ([0046]).
Chang in view of Tsai and Takeuchi are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chang in view of Tsai by using the transistors that control the memory cells as disclosed by Takeuchi to improve the device’s ability to control the memory structures leading to a more reliable device.
Regarding claim 17; Chang in view of Tsai in further view of Takeuchi teach all the limitations of the semiconductor memory device of claim 16.
Chang in view of Tsai does not teach wherein each of the plurality of transistors comprise a gate structure which includes a gate insulating film, a gate stack pattern, and a gate capping pattern sequentially stacked, wherein the gate insulating film includes a first portion extending along an upper face of the peripheral active region, and a second portion extending along an upper face of the peripheral element isolation film, and wherein a thickness of the first portion is the same as a thickness of the second portion.
However, Takeuchi wherein each of the plurality of transistors (Takeuchi: Fig (1): CG1…CGn) comprise a gate structure (Annotated Fig(3) shared in this OA: 34+36+42) which includes a gate insulating film (34), a gate stack pattern (36), and a gate capping pattern (42) sequentially stacked, wherein the gate insulating film (34) includes a first portion (First Portion) extending along an upper face of the peripheral active region (Peripheral Region), and a second portion (Second Portion) extending along an upper face of the peripheral element isolation film (32), and wherein a thickness of the first portion (First Portion) is the same as a thickness of the second portion (Second Portion).
Chang in view of Tsai and Takeuchi are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chang in view of Tsai by introducing the structure of the transistors disclosed in Takeuchi to improve the control of the memory cells leading to a more reliable device.
Regarding claim 18; Chang in view of Tsai in further view of Takeuchi teaches all the limitations of the semiconductor memory device of claim 17.
Chang in view of Tsai does not teach wherein the gate insulating film includes a third portion extending along an upper face of the peripheral sub-element isolation film, and wherein a thickness of the third portion is the same as a thicknesses of the first and second portions.
However, Takeuchi teaches wherein the gate insulating film (Takeuchi: Annotated Fig (3) shared in this OA: 32) includes a third portion (third Portion) extending along an upper face of the peripheral sub-element isolation film (50), and wherein a thickness of the third portion (Third Portion) is the same as a thicknesses of the first (First Portion) and second (Second Portion) portions.
Chang in view of Tsai and Takeuchi are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to modify Chang in view of Tsai by constructing the gate insulating film as disclosed in Takeuchi to improve the insulation of the gate and thus lead to a more reliable device.
Regarding claim 19; Chang in view of Tsai in further view of Takeuchi teaches all the limitations of the semiconductor memory device of claim 16.
Further, Chang teaches wherein an upper face of the peripheral element isolation film (Chang: Annotated Fig (1H) shared in this OA: 128) and an upper face of the peripheral sub-element isolation film (126) are placed on the same plane.
Regarding claim 20; Chang in view of Tsai in further view of Takeuchi teaches all the limitations of the semiconductor memory device of claim 16.
However, Chang in view of Tsai does not teach wherein the word line is disposed inside the substrate of the cell array region, and wherein the bit lines intersect the word line, on the substrate of the cell array region.
Takeuchi teaches wherein the word line (Takeuchi: Fig (2): WL) is disposed inside the substrate (Fig (3): S) of the cell array region, and wherein the bit lines (Fig (2) BL) intersect the word line (WL), on the substrate (Fig (3): S) of the cell array region.
Chang in view of Tsai and Takeuchi are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chang in view of Tsai by using the structure of the word lines and bit lines as disclosed by Takeuchi to make establishing electrical connection within the device easier which makes the device more reliable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.K./Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
Prosecution Insights