Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 3-5, 8-10, 14, 19, 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-13, 15-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Beak et al. (US 20200135971 A1) hereafter referred to as Beak
In regard to claim 11 Beak teaches a display device [see Fig. 2 shows one pixel, see plurality of pixels in a display] comprising:
signal lines [“A gate line GL may be formed on the same layer as the gate electrode 121. The gate line GL may be made of the same material as the gate electrode 121. The data line DL may also be formed in a similar manner as the gate line GL”, see that “The LED 130 and the thin-film transistor 120 may be connected to drivers such as a gate control circuit and a data control circuit through lines such as a gate line GL for a data line DL”];
auxiliary electrodes [see in each pixel, “source electrode 123” above 121, see paragraph 0052 see also “drain-electrode 124” see extending left-right, see on the right “The common line CL may be made of the same material as the source electrode 123 and the drain-electrode 124”] extending in a first direction on the signal lines;
alignment electrodes [“first connection electrode 141 may be in contact with the source electrode 123 of the thin-film transistor 120 through a contact hole formed through first planarization layer 116, the second planarization layer 117, the interlayer dielectric layer 114” “first connection electrode 141 may be in contact with the drain-electrode 124 of the thin-film transistor 120 depending on the type of the thin-film transistor 120” “second connection electrode 142 connects the common line CL with the n-electrode 135 of the LED 130”] including a first area [see the via part is overlapping and touching 123 along the left-right direction] overlapping the auxiliary electrodes and extending [see touching 123 along the left-right direction] in the first direction and a second area [see portion of the via extending up-down in the vertical direction] extending in a second direction crossing the first direction; and
light emitting elements [“LED 130”] between the alignment electrodes,
wherein the second area of the alignment electrodes contacts [see Fig. 2 both 141 and 142 are in the contact hole as via] the auxiliary electrodes through a contact hole, and wherein the auxiliary electrodes and the alignment electrodes are insulated [see Fig. 2 see “gate insulating layer 113 for insulating the active layer 121 from the gate electrode 121 is disposed between the gate electrode 121 and the active layer 122”] from the signal lines.
In regard to claim 12 Beak teaches further comprising: an emission area [i.e. the LED area], the light emitting elements being located in the emission area; a non-emission area [i.e. around the LEDs] surrounding the emission area; and a bank in the non-emission area [“the first planarization layer 116 and the second planarization layer 117 may be formed after the LED 130 is disposed and may be in tight contact with the LED 130”] and including an opening exposing [i.e. LED is exposed] the emission area.
In regard to claim 13 Beak teaches wherein the auxiliary electrodes [see Fig. 2 see 116 is over 123 and CL i.e. vertical overlap] overlap the bank.
In regard to claim 15 Beak teaches wherein the second area [see portion of the via extending up-down in the vertical direction] of the alignment electrodes is in the non-emission area.
In regard to claim 16 Beak teaches further comprising: bank patterns [“the first planarization layer 116 and the second planarization layer 117 may be formed after the LED 130 is disposed and may be in tight contact with the LED 130”, see 141 and 142 are in the contact hole as via and extend over 116, 117] located between the auxiliary electrodes and the alignment electrodes.
In regard to claim 17 Beak teaches wherein the bank patterns extend [see Fig. 2 wherein 116, 117 extend left-right] in the first direction.
In regard to claim 18 Beak teaches wherein the contact hole [see 141 and 142 are in the contact hole as via] is formed in the bank patterns.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 6, 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Beak et al. (US 20200135971 A1) hereafter referred to as Beak in view of Cho et al. (US 20180019369 A1) hereafter referred to as Cho
In regard to claim 1 Beak teaches a display device [see Fig. 2 shows one pixel, see plurality of pixels in a display] comprising:
signal lines [“A gate line GL may be formed on the same layer as the gate electrode 121. The gate line GL may be made of the same material as the gate electrode 121. The data line DL may also be formed in a similar manner as the gate line GL”, see that “The LED 130 and the thin-film transistor 120 may be connected to drivers such as a gate control circuit and a data control circuit through lines such as a gate line GL for a data line DL”];
auxiliary electrodes [see in each pixel, “source electrode 123” above 121, see paragraph 0052 see also “drain-electrode 124” see on the right “The common line CL may be made of the same material as the source electrode 123 and the drain-electrode 124”] on the signal lines;
bank patterns [“first planarization layer 116 and the second planarization layer 117 may be formed via a single process or two different processes”] on the auxiliary electrodes;
alignment electrodes [“first connection electrode 141 may be in contact with the source electrode 123 of the thin-film transistor 120 through a contact hole formed through first planarization layer 116, the second planarization layer 117, the interlayer dielectric layer 114” “first connection electrode 141 may be in contact with the drain-electrode 124 of the thin-film transistor 120 depending on the type of the thin-film transistor 120” “second connection electrode 142 connects the common line CL with the n-electrode 135 of the LED 130”] on the bank patterns and spaced [see that the first connection electrode 141 are formed for each LED location] from each other; and
light emitting elements [“the first planarization layer 116 and the second planarization layer 117 may be formed after the LED 130 is disposed and may be in tight contact with the LED 130”] between the bank patterns,
wherein the alignment electrodes are electrically connected to the auxiliary electrodes through a contact hole [“first connection electrode 141 may be in contact with the source electrode 123 of the thin-film transistor 120 through a contact hole formed through first planarization layer 116, the second planarization layer 117, the interlayer dielectric layer 114” “second connection electrode 142 is in contact with the common line CL through a contact hole formed through first planarization layer 116, the second planarization layer 117, the interlayer dielectric layer 114”] passing through the bank patterns, respectively, and wherein the auxiliary electrodes and the alignment electrodes are insulated [see Fig. 2 see “gate insulating layer 113 for insulating the active layer 121 from the gate electrode 121 is disposed between the gate electrode 121 and the active layer 122”] from the signal lines
but does not show that the bank patterns are spaced from each other,
however, see that in Fig. 2 see there is a hole in 116, 117 which is occupied by the “LED 130” so the left side and right side are “spaced” from each other by the LED 130 at each LED location, see that the claim does not state that the bank patterns are islands that do not touch, however in Fig. 10 of the instant Application the WL are shown as islands.
See that in Beak Fig. 2 “the first planarization layer 116 and the second planarization layer 117 may be formed after the LED 130 is disposed”.
See Cho teaches a different method see “FIGS. 8A to 8K are schematic cross-sectional views of a process of manufacturing a display apparatus” see in Fig. 8G “the light-emitting devices 40 may be transferred onto the first electrode 21 and the second electrode 22 by putting a solvent 90, such as ink or paste including a plurality of light-emitting devices 40, into the light-emitting portion 70” so in Cho the LED is disposed on the electrode pattern 21 and 22 which in the form of stripes inside the pixel, see Fig. 2.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Beak so that 116, 117 form stripes inside the pixel with the 141, 142 vias to receive the LEDs i.e. to modify Beak to include that the bank patterns are spaced from each other.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is ease of manufacture to dispose the LEDs onto the electrodes 141, 142 using a solvent.
In regard to claim 2 Beak and Cho as combined teaches further comprising: a first insulating layer [“an interlayer dielectric layer 114 is disposed on the source electrode 123 and the drain-electrode 124”] between the auxiliary electrodes and the bank patterns.
In regard to claim 6 Beak and Cho as combined teaches further comprising: an emission area [see combination, this is the LED region], the light emitting elements being located in the emission area; a non-emission area [this is the area around the LEDs] surrounding the emission area; and a bank in the non-emission area [see combination Cho the opening is to allow disposing LEDs using solvent] and including an opening exposing the emission area.
In regard to claim 7 Beak and Cho as combined teaches wherein the auxiliary electrodes overlap [see combination they are underneath the bank i.e. vertically overlap] the bank.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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