DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 14, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2021/0082802 Huang et al.
1. Referring to claim 1, Huang et al. teaches an interconnect structure, comprising: a transistor, (Figure 1M #104), on a substrate, (Figure 1M #102); a first dielectric layer, (Figure 1M #138’ & 140’), over the transistor, (Figure 1M #104); a first metal line, (Figure 1M #1351), through the first dielectric layer, (Figure 1M #138’ & 140’); a second dielectric layer, (Figure 1M #156), over the first dielectric layer, (Figure 1M #138’ & 140’); and a via, (Figure 1M #158 & 161), through the second dielectric layer, (Figure 1M #156), and on the first metal line, (Figure 1M #1351), wherein a first side surface of the first dielectric layer includes a first portion facing, (Figure 1M section of #138’ & 140’ that faces the metal line #1351), the first metal line, (Figure 1M #1351), and a second portion, (Figure 1M section of #138’ & 140’ that faces the via #158 & 161), facing the via, (Figure 1M #158 & 161), and the first portion of the first side surface of the first dielectric layer, (Figure 1M section of #138’ & 140’ that faces the metal line #1351), is aligned with the second portion of the first side surface of the first dielectric layer, (Figure 1M section of #138’ & 140’ that faces the via #158 & 161).
2. Referring to claim 2, Huang et al. teaches an interconnect structure as claimed in claim 1, wherein the via, (Figure 1M #158 & 161), lands on a top surface of the first dielectric layer, (Figure 1M #138’ & 140’).
3. Referring to claim 5, Huang et al. teaches an interconnect structure as claimed in claim 1, wherein the first metal line, (Figure 1M #1351), is electrically connected to a source/drain region of the transistor, (Figure 1M #108).
4. Referring to claim 14, Huang et al. teaches a method for forming an interconnect structure, comprising: forming a first dielectric layer, (Figures 1L-1M #138’ & 140’), over a transistor, (Figures 1L-1M #104); forming a metal line in the first dielectric layer, (Figures 1L-1M #1351); recessing the metal line, (Figures 1L- 1M #1351 after the removal of #141), to expose an upper portion of a side surface of the first dielectric layer, (Figures 1L-1M #138’ & 140’), wherein a lower portion of the side surface of the first dielectric layer, (Figures 1L-1M #138’ & 140’), is facing the metal line, (Figures 1L-1M #1351), and aligned with the upper portion of the side surface of the first dielectric layer, (Figures 1L-1M #138’ & 140’); forming a second dielectric layer, (Figures 1L-1M #156), over the metal line, (Figures 1L-1M #1351), and the first dielectric layer, (Figures 1L-1M #138’ & 140’); and forming a first via, (Figures 1L-1M #158 & 160), in the second dielectric layer, (Figures 1L-1M #156), and on the metal line, (Figures 1L-1M #1351).
5. Referring to claim 19, Huang et al. teaches a method for forming the interconnect structure as claimed in claim 14, further comprising: forming a contact plug, (Figure 1M #118), on a source/drain region of the transistor, (Figure 1M #108); and forming a second via, (Figure 1M area of #120), on the contact plug, (Figure 1M #118), wherein the metal line, (Figures 1L-1M #1351), is formed on the second via, (Figure 1M area of #120).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
6. Claims 3, 4, 6, 15-18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
7. The prior art teaches the claimed matter in the rejections above, but is silent with respect to the above teachings in combination with the interconnect structure as claimed in claim 1, further comprising: a contact etching stop layer between the first dielectric layer and the second dielectric layer, wherein a second side surface of the first dielectric layer is opposite to the first side surface of the first dielectric layer and includes a first portion facing the first metal line and a second portion facing the contact etching stop layer; the interconnect structure as claimed in claim 1, further comprising: a second metal line on the via, wherein the first metal line extends in a first horizontal direction, and the second metal line extends in a second horizontal direction that is perpendicular to the first horizontal direction; the method for forming the interconnect structure as claimed in claim 14, further comprising: forming a contact etching stop layer along a top surface of the first dielectric layer, the upper portion of the side surface of the first dielectric layer and a top surface of the metal line, wherein the second dielectric layer is formed over the contact etching stop layer; and/or the method for forming the interconnect structure as claimed in claim 14, wherein forming the transistor comprises: forming a plurality of nanostructures; and forming a gate stack to surround the plurality of nanostructures.
8. The prior art teaches an interconnect structure, comprising: a first intermetal dielectric layer over a substrate; a metal line surrounded by the first intermetal dielectric layer; a second intermetal dielectric layer over the first intermetal dielectric layer; a via in the second intermetal dielectric layer and on the metal line; and a contact etching stop layer between the first intermetal dielectric layer and the second intermetal dielectric layer, wherein a first side surface of the first intermetal dielectric layer includes a first portion facing the metal line, but is silent to the above teachings in combination with a second portion facing the contact etching stop layer, and the first portion of the first side surface of the first intermetal dielectric layer is aligned with the second portion of the first side surface of the first intermetal dielectric layer.
9. These combinations have been found to not be anticipated or render obvious over the prior art, hence claims 7-13 are allowed.
Conclusion
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/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 2/18/26
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