DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
As of August 17, 2026 no information disclosure statement has been made of record.
Drawing Objections
Examiner withdraws the drawing objection based upon Applicant’s submission of replacement figure 3.
Response to Arguments
Applicant's arguments filed July 22, 2026, have been fully considered but they are not persuasive.
Applicant asserts that that the prior art does not teach “a metallization structure disposed between the pad architecture and the plurality of active components”. This argument is not persuasive. The Applicant of this application is Advanced Micro Devices (“AMD”). According to an Applied Materials news release dated July 10, 1998, AMD was using metal interconnects as early as 1998.1 Further, Lapedus in figure 1 shows a drawing the interconnects where the interconnects are metal. This figure is reproduced below2. Therefore, any argument regarding the interconnects not being metal disingenuous at best seeing that Lapedus taught it, and the fact that Applicant uses metal interconnects. AMD is free to submit evidence that their own engineers did not know that their employer AMD uses metal interconnects in device (FEOL) and BEOL processes.
PNG
media_image1.png
737
500
media_image1.png
Greyscale
Applicant next asserts that Lapedus does not teach the metallization structure is disposed between the pad architecture and the plurality of active components. Applicant is correct. The pad architecture is taught by Hsu and the metallization structure is taught by Lapedus, and the combination teaches this limitation. To clearly show this limitation with the combination of references Examiner has put the two references together in Examiner figure 1 below.
PNG
media_image2.png
700
1244
media_image2.png
Greyscale
In Examiner figure 1 one can clearly see that metallization structure is between the pad of Hsu and the plurality of active devices of Lapedus. Therefore, this argument is unpersuasive as Applicant has failed to consider the combination of references together as a whole. This is because, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant’s arguments that there is no reason to combine to the references is equally unpersuasive. Hsu clearly teaches that the substrates in figure 9 contain devices and BOEL features. Figure 1 of Lapedus shows the devices (FEOL) and BOEL features. Applicant, and their engineers should, as one of the largest CPU and GPU manufactures on the planet, know that when Hsu speaks of devices (FEOL) and BOEL they are talking about the features shown Lapedus. Therefore, it would have been obvious to one of ordinary skill in the art that when Hsu speaks about devices (FEOL) and BOEL that it is referring obviously to the features shown in Lapedus. One would be motivated to combine these references as this is the ordinary and customary way one of ordinary skill in the art does this as evidenced by the references.3
For all the above reasons, Applicant’s arguments are not persuasive.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11, and 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2011/0031633 A1) (“Hsu”), view of Lapedus, Mark, "New BEOL/MOL Breakthroughs?", https://semiengineering.com/new-beolmol-breakthroughs/, June 15, 2017 (“Lapedus”).
Regarding claim 1, Hsu teaches at least in figures 9 and 12, and Examiner figure 1:
PNG
media_image2.png
700
1244
media_image2.png
Greyscale
a pad architecture comprising (detailed below; hereinafter A)
first conductive pads (504) of a first substrate (top part of figure 9) each bonded to respective second conductive pads (801) of a second substrate (bottom part of figure 9),
the first (504) and second conductive pads (801) arrayed at an inter-pad spacing (they are so spaced);
a plurality of active components (806 contains active devices) located in the second substrate (bottom part of figure 9).
Hsu does not explicitly teach:
a plurality of active components (Hsu 806 contains active devices) located in the second substrate (Hsu bottom part of figure 9) and arrayed at an inter-component spacing;
a metallization structure disposed between the pad architecture and the plurality of active components,
wherein the metallization structure is configured to decrease the inter-component spacing relative to the inter-pad spacing.
Lapedus teaches at least in figure 2 below:
PNG
media_image3.png
258
672
media_image3.png
Greyscale
a plurality of active components (Hsu 806 contains active devices; Lapedus transistor) located in the second substrate (Hsu bottom part of figure 9; substrate of Lapedus) and arrayed at an inter-component spacing (as can be seen in figure above each of the transistors are so spaced);
It would have been obvious to one of ordinary skill in the art that Hsu’s device and BEOL would include the transistor and interconnect structure of Hsu. This is because this is the customary and ordinary way that devices in semiconductors are made. One of ordinary skill in the art reading Hsu would have known this. This is why Hsu does not explicitly teach this. Under MPEP 2161, specifications “‘a specification need not disclose what is well known in the art.’” Id. (quoting Genentech, Inc.v. Novo Nordisk A/S, 108 F.3d 1361, 1366, 42 USPQ2d 1001, 1005 (Fed. Cir. 1997)); see also AK Steel Corp. v. Sollac & Ugine, 344 F.3d 1234, 1244, 68 USPQ2d 1280, 1287 (Fed. Cir. 2003). Lapedus shows/teaches what is well known in the art.
The combination of references teach:
a metallization structure (Lapedus contact and interconnect) disposed between the pad architecture (Hsu A) and the plurality of active components (Lapedus transistor; Hsu Device+BEOL),
wherein the metallization structure (Lapedus contact and interconnect) is configured to decrease the inter-component spacing relative to the inter-pad spacing (as one can see in figure 2 of Lapedus above the device/transistors are closer together and the interconnect spacing fans out).
Regarding claim 2, the prior art teaches:
wherein the metallization structure (Lapedus contact and interconnect) comprises at least one conductive line extending laterally by an amount effective to decrease the inter-component spacing relative to the inter-pad spacing (this is obvious, routine, and customary in the semiconductor arts. How one chooses to route the connections between devices and the output pins is routine in the art. It is a basic job function performed by an engineer, and depends upon the design requirements. Some of these requirements are the size of the die, the amount of current in the transistors, the type of device one is designing (analog, digital, mixed signal, etc.), what the line is going to be used for (power, ground, clock, signal, etc.). Therefore, this limitation would have been obvious to one of ordinary skill in the art.
Regarding claim 3, the prior art teaches:
wherein the metallization structure electrically connects a selected one of the active components with a selected one of the first conductive pads such that the selected active component is laterally offset from the selected first conductive pad (This limitation is obvious for the same reason as claim 2 above. One of ordinary skill in the art using ordinary skill in the art would use the metallization structure (also known as metal layers) to direct and redirect the electrical connection between the devices and the pads).
Regarding claim 4, the prior art teaches:
wherein the inter-component spacing is at least approximately 10% less than the inter-pad spacing (this is an obvious optimization based upon the analysis contained in claims 2-3. One of ordinary skill in the art using routine skill in the art would have optimized the placement of the transistors in the device level of Lapedus and the TSV’s 304 in Hsu in order to minimize the die size, and to optimize the device placement for the circuits being designed for).
Regarding claim 5, Lapedus teaches:
wherein the inter-pad spacing is greater than approximately 10 micrometers and the inter-component spacing is less than approximately 8 micrometers (pg. 5 bottom of the page where the component contact spacing can be 7nm or so; pg. 8 where the m1 pitch is 42nm. Based upon figures 1-2, it would have been obvious that as one increases in height along the metal layers from the device layer to the top of the BEOL that the spacing would increase. This is because one would eventually need to accommodate solder balls or other external connection components.).
Regarding claim 6, Hsu teaches at least in figures 9 and 12:
wherein the active components comprise driver or receiver logic elements (Hsu does not limit what the device can be. It would have been obvious to one of ordinary skill in the art that the device layer of Hsu could include driver or receiver logic elements as these are standard elements included in semiconductor devices).
Regarding claim 7, Hsu teaches at least in figures 9 and 12:
wherein the first (504) and second conductive pads (801) comprise bond pad metal structures (¶ 0039, where 504 can be copper; ¶ 0042, where 801 can be copper).
Regarding claim 8, Hsu teaches at least in figures 9 and 12:
wherein the first and second conductive pads comprise copper (¶ 0039, where 504 can be copper; ¶ 0042, where 801 can be copper).
Regarding claim 9, Hsu teaches at least in figures 9 and 12:
wherein the first substrate (top of figure 9) comprises conductive vias (304; ¶ 0034, where 304 can be copper plated) extending entirely through the first substrate (figure 12 where 304 so extends all the way through) and each aligned with a respective one of the first conductive pads (Based upon the teachings of Hsu and Lapedus it would have been obvious that there would be multiple 304 extending through the top part of Hsu figure 9 which would interconnected with the Device+BEOL of Hsu. This would have been obvious because a semiconductor device circuit will obviously require more than the connections shown in Hsu.).
Regarding claim 10,
Claim 10 contains the same and/or similar subject matter as claims 1, 3, 5, and/or 9. Therefore, claim 10 is rejected for the same reasons as claims 1, 3, 5, and/or 9.
Regarding claim 11,
Claim 11 is obvious for the same reasons/rational as claims 3-5. This is because how one of ordinary skill in the art chooses to arrange and interconnect the devices in Hsu/Lapedus is a matter of ordinary skill in the art based upon the aforementioned design requirements as previously stated.).
Regarding claim 14,
Claim 14 is rejected for the same reasons as claim 6 above.
Regarding claim 15,
Claim 15 is rejected for the same reasons as claim 4 above.
Regarding claims 16-17,
Claim 16-17 are rejected for the same reasons as claim 5 above.
Regarding claim 18,
Claim 18 is rejected for the same reasons as claim 1 above.
Regarding claim 19,
Claim 19 is rejected for the same reasons as claim 2 and/or 3 above.
Claim(s) 12-13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, view of Lapedus, in view of Chen et al., "Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding", 2010 International Electron Devices Meeting, Date of Conference: 06-08 December 2010, Date Added to IEEE Xplore: 28 January 2011, DOI: 10.1109/IEDM.2010.5703283 (“Chen”)
Regarding claim 12, Hsu teaches at least in figures 9 and 12:
The two parts of figure 9 are bonded together as shown in figure 10 by having the metal 504 and 801 being bonded together (¶ 0045-51).
Hsu does not use the term hybrid bonding.
Chen teaches:
That hybrid bonding is metal to metal and oxide to oxide bonding. Chen teaches that the style of bonding shown in Hsu is called lock-n-key. Figure 1. It would have been obvious to one of ordinary skill in the art to use Chen’s hybrid bonding as Chen teaches this hybrid bonding performs better than previous methods of wafer bonding. Introduction.
Regarding claim 13, the prior art teaches:
wherein the first and second die (the two parts shown in figure 9) are bonded with a face-to-back hybrid bond (the two wafers of Hsu are so bonded together as taught by Chen).
Regarding claim 20, Chen teaches:
wherein the bonding comprises forming a first bond between the insulating material of the first die and the insulating material of the second die, and forming a second bond between the plurality of conductive pads of the first die and the plurality of conductive pads of the second die (this is the hybrid bonding as taught by Chen).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VINCENT WALL/ Primary Examiner, Art Unit 2898
1 Applied Materials new release, “AMD Selects Applied Materials' Copper Technology; Electra IMP TaN and Copper Seed Layer Processes Will Be Used for Copper Interconnect Structures”, July 10, 1998, https://ir.appliedmaterials.com/news-releases/news-release-details/amd-selects-applied-materials-copper-technology-electra-imp-tan
2 https://en.wikipedia.org/wiki/Interconnect_(integrated_circuits)#/media/File:Cmos-chip_structure_in_2000s_(en).svg Cited by Lapedus.
3 Examiner asserts that these processes are so well known in the art that a YouTube by the name of nanolearning posted five videos on the FEOL and BEOL process at https://www.youtube.com/playlist?list=PLSHXXkQ-R9aQuo228YdPa7hH6Ai4dtDZd
Prosecution Insights