DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
As of February 19, 2026 no information disclosure statement has been made of record.
Drawing Objections
The drawings are objected to because:
In figure 3 there are two dashed boxes with no labels associated with them.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11, and 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2011/0031633 A1) (“Hsu”), view of Lapedus, Mark, "New BEOL/MOL Breakthroughs?", https://semiengineering.com/new-beolmol-breakthroughs/, June 15, 2017 (“Lapedus”).
Regarding claim 1, Hsu teaches at least in figures 9 and 12:
a pad architecture comprising (detailed below; hereinafter A)
first conductive pads (504) of a first substrate (top part of figure 9) each bonded to respective second conductive pads (801) of a second substrate (bottom part of figure 9),
the first (504) and second conductive pads (801) arrayed at an inter-pad spacing (they are so spaced);
a plurality of active components (806 contains active devices) located in the second substrate (bottom part of figure 9).
Hsu does not explicitly teach:
a plurality of active components (Hsu 806 contains active devices) located in the second substrate (Hsu bottom part of figure 9) and arrayed at an inter-component spacing;
a metallization structure disposed between the pad architecture and the plurality of active components,
wherein the metallization structure is configured to decrease the inter-component spacing relative to the inter-pad spacing.
Lapedus teaches at least in figure 2 below:
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a plurality of active components (Hsu 806 contains active devices; Lapedus transistor) located in the second substrate (Hsu bottom part of figure 9; substrate of Lapedus) and arrayed at an inter-component spacing (as can be seen in figure above each of the transistors are so spaced);
It would have been obvious to one of ordinary skill in the art that Hsu’s device and BEOL would include the transistor and interconnect structure of Hsu. This is because this is the customary and ordinary way that devices in semiconductors are mad. One of ordinary skill in the art reading Hsu would have known this. This is why Hsu does not explicitly teach this. Under MPEP 2161, specifications “‘a specification need not disclose what is well known in the art.’” Id. (quoting Genentech, Inc.v. Novo Nordisk A/S, 108 F.3d 1361, 1366, 42 USPQ2d 1001, 1005 (Fed. Cir. 1997)); see also AK Steel Corp. v. Sollac & Ugine, 344 F.3d 1234, 1244, 68 USPQ2d 1280, 1287 (Fed. Cir. 2003). Lapedus shows/teaches what is well known in the art.
The combination of references teach:
a metallization structure (Lapedus contact and interconnect) disposed between the pad architecture (Hsu A) and the plurality of active components (Lapedus transistor; Hsu Device+BEOL),
wherein the metallization structure (Lapedus contact and interconnect) is configured to decrease the inter-component spacing relative to the inter-pad spacing (as one can see in figure 2 of Lapedus above the device/transistors are closer together and the interconnect spacing fans out).
Regarding claim 2, the prior art teaches:
wherein the metallization structure (Lapedus contact and interconnect) comprises at least one conductive line extending laterally by an amount effective to decrease the inter-component spacing relative to the inter-pad spacing (this is obvious, routine, and customary in the semiconductor arts. How one chooses to route the connections between devices and the output pins is routine in the art. It is a basic job function performed by an engineer, and depends upon the design requirements. Some of these requirements are the size of the die, the amount of current in the transistors, the type of device one is designing (analog, digital, mixed signal, etc.), what the line is going to be used for (power, ground, clock, signal, etc.). Therefore, this limitation would have been obvious to one of ordinary skill in the art.
Regarding claim 3, the prior art teaches:
wherein the metallization structure electrically connects a selected one of the active components with a selected one of the first conductive pads such that the selected active component is laterally offset from the selected first conductive pad (This limitation is obvious for the same reason as claim 2 above. One of ordinary skill in the art using ordinary skill in the art would use the metallization structure (also known as metal layers) to direct and redirect the electrical connection between the devices and the pads).
Regarding claim 4, the prior art teaches:
wherein the inter-component spacing is at least approximately 10% less than the inter-pad spacing (this is an obvious optimization based upon the analysis contained in claims 2-3. One of ordinary skill in the art using routine skill in the art would have optimized the placement of the transistors in the device level of Lapedus and the TSV’s 304 in Hsu in order to minimize the die size, and to optimize the device placement for the circuits being designed for).
Regarding claim 5, Lapedus teaches:
wherein the inter-pad spacing is greater than approximately 10 micrometers and the inter-component spacing is less than approximately 8 micrometers (pg. 5 bottom of the page where the component contact spacing can be 7nm or so; pg. 8 where the m1 pitch is 42nm. Based upon figures 1-2, it would have been obvious that as one increases in height along the metal layers from the device layer to the top of the BEOL that the spacing would increase. This is because one would eventually need to accommodate solder balls or other external connection components.).
Regarding claim 6, Hsu teaches at least in figures 9 and 12:
wherein the active components comprise driver or receiver logic elements (Hsu does not limit what the device can be. It would have been obvious to one of ordinary skill in the art that the device layer of Hsu could include driver or receiver logic elements as these are standard elements included in semiconductor devices).
Regarding claim 7, Hsu teaches at least in figures 9 and 12:
wherein the first (504) and second conductive pads (801) comprise bond pad metal structures (¶ 0039, where 504 can be copper; ¶ 0042, where 801 can be copper).
Regarding claim 8, Hsu teaches at least in figures 9 and 12:
wherein the first and second conductive pads comprise copper (¶ 0039, where 504 can be copper; ¶ 0042, where 801 can be copper).
Regarding claim 9, Hsu teaches at least in figures 9 and 12:
wherein the first substrate (top of figure 9) comprises conductive vias (304; ¶ 0034, where 304 can be copper plated) extending entirely through the first substrate (figure 12 where 304 so extends all the way through) and each aligned with a respective one of the first conductive pads (Based upon the teachings of Hsu and Lapedus it would have been obvious that there would be multiple 304 extending through the top part of Hsu figure 9 which would interconnected with the Device+BEOL of Hsu. This would have been obvious because a semiconductor device circuit will obviously require more than the connections shown in Hsu.).
Regarding claim 10,
Claim 10 contains the same and/or similar subject matter as claims 1, 3, 5, and/or 9. Therefore, claim 10 is rejected for the same reasons as claims 1, 3, 5, and/or 9.
Regarding claim 11,
Claim 11 is obvious for the same reasons/rational as claims 3-5. This is because how one of ordinary skill in the art chooses to arrange and interconnect the devices in Hsu/Lapedus is a matter of ordinary skill in the art based upon the aforementioned design requirements as previously stated.).
Regarding claim 14,
Claim 14 is rejected for the same reasons as claim 6 above.
Regarding claim 15,
Claim 15 is rejected for the same reasons as claim 4 above.
Regarding claims 16-17,
Claim 16-17 are rejected for the same reasons as claim 5 above.
Regarding claim 18,
Claim 18 is rejected for the same reasons as claim 1 above.
Regarding claim 19,
Claim 19 is rejected for the same reasons as claim 2 and/or 3 above.
Claim(s) 12-13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, view of Lapedus, in view of Chen et al., "Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding", 2010 International Electron Devices Meeting, Date of Conference: 06-08 December 2010, Date Added to IEEE Xplore: 28 January 2011, DOI: 10.1109/IEDM.2010.5703283 (“Chen”)
Regarding claim 12, Hsu teaches at least in figures 9 and 12:
The two parts of figure 9 are bonded together as shown in figure 10 by having the metal 504 and 801 being bonded together (¶ 0045-51).
Hsu does not use the term hybrid bonding.
Chen teaches:
That hybrid bonding is metal to metal and oxide to oxide bonding. Chen teaches that the style of bonding shown in Hsu is called lock-n-key. Figure 1. It would have been obvious to one of ordinary skill in the art to use Chen’s hybrid bonding as Chen teaches this hybrid bonding performs better than previous methods of wafer bonding. Introduction.
Regarding claim 13, the prior art teaches:
wherein the first and second die (the two parts shown in figure 9) are bonded with a face-to-back hybrid bond (the two wafers of Hsu are so bonded together as taught by Chen).
Regarding claim 20, Chen teaches:
wherein the bonding comprises forming a first bond between the insulating material of the first die and the insulating material of the second die, and forming a second bond between the plurality of conductive pads of the first die and the plurality of conductive pads of the second die (this is the hybrid bonding as taught by Chen).
Conclusion
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/VINCENT WALL/ Primary Examiner, Art Unit 2898