DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed December 22, 2023.
Claims 1-20 are pending. Claims 1, 13 and 20 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on February 2, 2024.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it contains a phrase that can be implied (i.e. “The present application discloses”). A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. See MPEP 606.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 13-14 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wan (U.S. 2023/0168820).
Regarding independent claim 1, Wan discloses an operation method (Fig. 4) of a memory (Fig. 1), wherein the memory comprises:
a page buffer (Fig. 1: 110), comprising:
a first sensing circuit (Fig. 2: 112) coupled to a sensing node (Fig. 2: SO); and
a dynamic storage circuit (Fig. 2: 113) coupled to the first sensing circuit (Fig. 2: 112); and
a memory cell, configured to store one of a plurality of programmed states (see page 6, par. 0071); and wherein the operation method comprises:
storing first verification information into the first sensing circuit based on a first potential of the sensing node (Fig. 4: 403);
transmitting initial verification information in the dynamic storage circuit to the sensing node, the initial verification information comprising verification information corresponding to a verified programmed state among the plurality of programmed states (see page 7, par. 0077);
transmitting the first verification information from the first sensing circuit to the dynamic storage circuit (see page 7, par. 0077);
performing a clearing operation on the first sensing circuit (“RST_1=1, see page 7, par. 0077); and
storing second verification information or the initial verification information into the first sensing circuit based on a second potential of the sensing node (see page 7, par. 0080-0081),
wherein the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information (When the threshold voltage of the programming cell is greater than the first forced sensing voltage Vfc1, latch 112 store “1”. latch 112 may store “0” as the second latch information. Logic “1” is greater than logic “0”, see page 5, par. 0060).
Regarding claim 2, Wan discloses wherein the page buffer further comprises a second sensing circuit coupled to the sensing node (Fig. 2: 111), and the operation method further comprises:
storing third verification information into the second sensing circuit based on a third potential of the sensing node (see page 7, par. 0085-0086);
wherein the second potential of the sensing node corresponding to the second verification information is greater than the third potential of the sensing node corresponding to the third verification information (When a cell is programmed, the latch 111 may store “0”, and latch 112 may store “1” when using Vcf2 as shown in Figure 3. Logic “1” is greater than logic “0”, see pages 4-5, par. 0059).
Regarding claim 3, Wan discloses wherein the dynamic storage circuit corresponding to a first memory cell in a programmed state to be verified or a second memory cell in a verified programmed state that fails verification among the plurality of programmed states is in an initial state (see page 6, par. 0070-0071).
Regarding claim 5, Wan discloses wherein the transmitting the first verification information from the sensing circuit to the dynamic storage circuit comprises:
enabling a transmission channel between the first sensing circuit and the dynamic storage circuit, such that the first verification information in the first sensing circuit is transmitted to the dynamic storage circuit (Fig. 2: 114, see also page 7, par. 0077).
Regarding claim 6, Wan discloses wherein the performing a clearing operation on the first sensing circuit comprises:
resetting the first sensing circuit to restore the first sensing circuit into an initial state (“RST_1=1, see page 7, par. 0077).
Regarding independent claim 13, Wan discloses an operation method (Fig. 4) of a memory (Fig. 1), wherein the memory comprises:
a page buffer (Fig. 1: 110), comprising:
a first sensing circuit (Fig. 2: 112) coupled to a sensing node (Fig. 2: SO); and
a dynamic storage circuit (Fig. 2: 113) coupled to the first sensing circuit (Fig. 2: 112); and
a memory cell, configured to store one of a plurality of programmed states (see page 6, par. 0071); and wherein the operation method comprises:
latching first verification information into the first sensing circuit during a first sensing stage of a verify operation of the memory (Fig. 4: 403);
transmitting initial verification information in the dynamic storage circuit to the sensing node, the initial verification information comprising verification information corresponding to a verified programmed state among the plurality of programmed states comprised in the memory (see page 7, par. 0077);
enabling a transmission channel between the first sensing circuit and the dynamic storage circuit, transmitting the first verification information to the dynamic storage circuit (Fig. 2: 114, see also page 7, par. 0077);
performing a clearing operation on the first sensing circuit (“RST_1=1, see page 7, par. 0077); and
latching second verification information into the first sensing circuit during a second sensing stage of the verify operation (see page 7, par. 0080-0081),
wherein a first potential of the sensing node corresponding to the first verification information is greater than a second potential of the sensing node corresponding to the second verification information (When the threshold voltage of the programming cell is greater than the first forced sensing voltage Vfc1, latch 112 store “1”. latch 112 may store “0” as the second latch information. Logic “1” is greater than logic “0”, see page 5, par. 0060).
Regarding claim 14, Wan discloses wherein the page buffer further comprises a second sensing circuit coupled to the sensing node (Fig. 2: 111); and the operation method further comprises:
latching third verification information into the second sensing circuit during a third sensing stage of the verify operation (see page 7, par. 0085-0086), wherein the second potential of the sensing node corresponding to the second verification information is greater than a third potential of the sensing node corresponding to the third verification information (When a cell is programmed, the latch 111 may store “0”, and latch 112 may store “1” when using Vcf2 as shown in Figure 3. Logic “1” is greater than logic “0”, see pages 4-5, par. 0059).
Regarding independent claim 20, Wan discloses a memory (Fig. 1), comprising:
a memory array (Fig. 1: 120), comprising a memory cell configured to store one of a plurality of programmed states (see page 6, par. 0071);
a plurality of page buffers coupled to the memory array (Fig. 1: 110), each page buffer comprising a first sensing circuit (Fig. 2: 112) coupled to a sensing node (Fig. 2: SO) and a dynamic storage circuit (Fig. 2: 113) coupled to the first sensing circuit (Fig. 2: 112); and
a control logic (Fig. 1: 130-140) circuit coupled to the memory array (Fig. 1: 120) and the plurality of page buffers (Fig. 1: 110); wherein the control logic circuit is configured to:
store first verification information into the first sensing circuit based on a first potential of the sensing node (Fig. 4: 403);
transmit initial verification information in the dynamic storage circuit to the sensing node, the initial verification information comprising verification information corresponding to a verified programmed state among the plurality of programmed states (see page 7, par. 0077);
transmit the first verification information from the first sensing circuit to the dynamic storage circuit (see page 7, par. 0077);
perform a clearing operation on the first sensing circuit (“RST_1=1, see page 7, par. 0077); and
store second verification information or the initial verification information into the first sensing circuit based on a second potential of the sensing node (see page 7, par. 0080-0081),
wherein the first potential of the sensing node corresponding to the first verification information is greater than the second potential of the sensing node corresponding to the second verification information (When the threshold voltage of the programming cell is greater than the first forced sensing voltage Vfc1, latch 112 store “1”. latch 112 may store “0” as the second latch information. Logic “1” is greater than logic “0”, see page 5, par. 0060).
Allowable Subject Matter
Claims 4, 7-12 and 15-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 4, there is no teaching or suggestion in the prior art of record to provide the recited step of charging the sensing node corresponding to a third memory unit in the verified programmed state that passes verification among the plurality of programmed states based on the initial verification information, to transmit the initial verification information to the sensing node.
With respect to claim 7, there is no teaching or suggestion in the prior art of record to provide the recited steps of obtaining selected operation information based on data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit, the selected operation information being configured to select a first memory cell in a programmed state to be verified or a second memory cell in a verified programmed state that fails verification among the plurality of programmed states, storing the selected operation information into the second sensing circuit, and precharging the sensing nodes corresponding to the first memory cell and the second memory cell to a preset initial voltage based on the selected operation information.
With respect to claim 12, there is no teaching or suggestion in the prior art of record to provide the recited step of before the verify operation, performing a clearing operation on the first sensing circuit and the dynamic storage circuit.
With respect to claim 15, there is no teaching or suggestion in the prior art of record to provide the recited steps of during the precharging stage, latching selected operation information into the second sensing circuit, precharging the sensing node to a preset initial voltage based on the selected operation information, and during the first discharge state, discharging the sensing node from the preset initial voltage, and after a first preset duration, suspending discharging the sensing node, wherein the selected operation information is obtained based on data information in the at least one data latch circuit and the initial verification information in the dynamic storage circuit, and configured to select a first memory cell in a programmed state to be verified or a second memory cell in a verified programmed state that fails verification among the plurality of programmed states.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825