DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C.
103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 - 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsushita, Keiichi (US 9508809) herein referred to as Matsushita in view of Huang, Chih-Shu (US 20210083083) herein referred to as Huang.
As to claim(s) 1, Matsushita teaches a semiconductor transistor, comprising
a semiconductor epitaxial layer (Fig. 6B [col 3 lines 7-11] epitaxial layer 13 + 14 + 11), wherein the semiconductor epitaxial layer (epitaxial layer 13 + 14 + 11) comprises a channel layer (Fig. 6B channel layer 12 and 13) and a barrier layer (Fig. 6B barrier layer 14) sequentially stacked on a substrate (Fig. 6B substrate 11) and ([col 3 lines 21-23] “The barrier layer 14 made of, for example, aluminum gallium nitride (AlGaN) is stacked on the upper surface of the spacer layer 13.); wherein
at least one of a source region and a drain region ([col 3 lines 25-28] source and drain electrodes 17 and 18 have source and drain regions formed near the bottom of 17 and 18) of the semiconductor epitaxial layer (epitaxial layer 13 + 14 + 11)
ohmic metal ([col 4 line 48-49] source electrode 18 as an ohmic electrode) is disposed on the ion implantation region (Annotated Fig. 6B ion implantation region), and
the ohmic metal (18) is in ohmic contact with a non-groove region of the ion implantation region (Annotated Fig. 6B ion implantation region), a sidewall of the groove (Annotated Fig. 6B sidewall of the groove), and a bottom of the groove (Annotated Fig. 6B bottom of the groove); and wherein
an area of a vertical projection of the groove (Fig. 2C groove 15a/Fig. 6B 18a) on the substrate (Fig. 6B substrate 11) is greater than or equal to half of an area of a vertical projection of the ohmic metal on the substrate (Fig. 6B substrate 11); and
a depth of the groove (Annotated Fig. 6B depth of the groove, (Fig. 2C groove 15a/Fig. 6B 18a) is less than a depth of the ion implantation region (Annotated Fig. 6B depth of the ion implantation region).
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Matsushita does not appear to expressly disclose "an ion implantation region”
However, Huang does teach ion implementation into the source drain region. Huang [0140], discloses “multiple ion implantation is adopted to implant n-type silicon dopants below the drain and source electrodes.” Ion implantation is performed in the source/drain (S/D) regions to introduce specific dopant atoms so as to alter its electrical properties. This technique is used to create conductive, low-resistance regions that allow the transistor to operate efficiently, providing precise control over doping concentration, depth, and uniformity.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to implant multiple ions as in the Huang device, into the source/drain area of the Matsushita device, so as to control the depth and placement of the ohmic contact.
As to claim(s) 2 and 18, the Matsushita/Huang combination teaches the semiconductor transistor according to claim 1, and the manufacturing method for the semiconductor transistor according to claim 16, wherein
wherein
implanted ions in the ion implantation region (Annotated Fig. 6B ion implantation region) comprise at least one selected from the group consisting of silicon (Si) ions ([0140] “multiple ion implantation is adopted to implant n-type silicon dopants) and germanium (Ge) ions.
As to claim(s) 3, Matsushita/Huang combination teaches the semiconductor transistor according to claim 1, wherein
a position corresponding to a depth of ion implantation (Annotated Fig. 6B ion implantation depth) in the ion implantation region is located in the barrier layer (Fig. 6B barrier layer 14).
As to claim(s) 4, Matsushita/Huang combination teaches the semiconductor transistor according to claim 1, wherein
a position corresponding to a depth of ion implantation (Annotated Fig. 6B ion implantation depth) in the ion implantation region is located at a surface of the channel layer (Fig. 6B channel layer 12 and 13).
As to claim(s) 5 and 19, Matsushita/Huang combination teaches the semiconductor transistor according to claim 1, and the manufacturing method for the semiconductor transistor according to claim 16, wherein
wherein
the ion implantation region (Annotated Fig. 6B ion implantation region) penetrates through the barrier layer (Fig. 6B barrier layer 14) and extends to the channel layer (Fig. 6B channel layer 12 and 13).
As to claim(s) 6 and 20, Matsushita/Huang combination teaches the semiconductor transistor according to claim 5, and the manufacturing method for the semiconductor transistor according to claim 16,wherein
the groove (Fig. 2C groove 15a/Fig. 6B groove 18a) penetrates through the barrier layer (Fig. 6B barrier layer 14) and extends to the channel layer (Fig. 6B channel layer 12 and 13).
As to claim(s) 7, the semiconductor transistor according to claim 5, wherein
the depth of the ion implantation region is less than 500 nanometers (nm).
The Matsushita/Huang combination does not appear to expressly disclose " the depth of the ion implantation region is less than 500 nanometers (nm)” However, Huang [0197] does define the ion implantation regions below the drain and source electrodes. Ion implantation is performed in the source/drain (S/D) regions to introduce specific dopant atoms directly, so as to alter electrical properties.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the depth of the ion implantation region less than 500 nanometers in the Matsushita/Huang device so as to create shallow, highly conductive, and precisely controlled junctions using an industrially accepted implantation manner. If that leads to a depth of the ion implantation region of less than 500 nanometers, then that is the result of ordinary skill in the art, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )
Furthermore, the Applicant has not shown that the depth of 500 nm is novel and would not have been found through routine experimentation. It would have also been obvious to one having ordinary skill in the art at the time the invention was made to optimize the depth of the ion implantation region so as to be able to precisely control junctions.
As to claim(s) 8, The Matsushita/Huang combination teaches the semiconductor transistor according to claim 1, wherein
a shape of the vertical projection of the groove on the substrate is one of circular, square, rectangular, or irregular (Fig. 6B, Matsushita).
As to claim(s) 9 and 12, the semiconductor transistor according to claim 1, and the semiconductor transistor according to claim 10, wherein
a size of the vertical projection of the groove on the substrate is in a range from 1 micrometer (μm) to 100 μm.
The Matsushita/Huang combination does not appear to expressly disclose " a size of the vertical projection of the groove on the substrate is in a range from 1 micrometer (μm) to 100 μm.” However, in [col 2 lines 26-30] Matsushita does disclose a plurality of grooves penetrating from the upper surface of the barrier layer through the barrier layer and the spacer layer and reaching a region of a two-dimensional electron gas layer formed in a spacer-layer side of the buffer layer. The grooves must be long enough to penetrate the barrier and spacer layer.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make a size of the vertical projection of the groove on the substrate deep enough to provide adequate depth for ohmic metal contact to optimize electrical performance. If that leads to a depth within the range of 1 micrometer (μm) to 100 μm, then that is the result of ordinary skill in the art, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )Furthermore, the Applicant has not shown that a range from 1 micrometer (μm) to 100 μm is novel and would not have been found through routine experimentation.
As to claim(s) 10, Matsushita/Huang combination teaches the semiconductor transistor according to claim 1, wherein
the groove in the ion implantation region is at least two in number (Fig. 6B, Matsushita).
As to claim(s) 11, the semiconductor transistor according to claim 10,
the number of the at least two grooves is k, an area of a vertical projection of each of the at least two grooves on the substrate is a, the area of the vertical projection of the ohmic metal on the substrate is b, and 0.5≤(ka)/b<1.
The Matsushita/Huang combination does not appear to expressly disclose " the number of the at least two grooves is k, an area of a vertical projection of each of the at least two grooves on the substrate is a, the area of the vertical projection of the ohmic metal on the substrate is b, and 0.5≤(ka)/b<1”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make “k” the number of the at least two grooves, “a” an area of a vertical projection of each of the at least two grooves on the substrate, “b” the area of the vertical projection of the ohmic metal on the substrate, and 0.5≤(ka)/b<1 in the Matsushita/Huang device so as to create shallow, highly conductive, and precisely controlled junctions using an industrially accepted implantation manner.
Furthermore, the Applicant has not shown that the number of grooves and the area of the vertical projection of the ohmic metal on the substrate limitations is novel and would not have been found through routine experimentation. It would have also been obvious to one having ordinary skill in the art at the time the invention was made to optimize the number of grooves and the area of the vertical projection of the ohmic metal on the substrate limitations, so as to be able to precisely control junctions, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.)
As to claim(s) 13, the semiconductor transistor according to claim 10, wherein
a size of a groove of the at least two grooves proximate to a gate region is larger than a size of a groove of the at least two grooves facing away from the gate region.
The Matsushita/Huang combination does not appear to expressly disclose "a size of a groove of the at least two grooves proximate to a gate region is larger than a size of a groove of the at least two grooves facing away from the gate region.”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make a size of a groove of the at least two grooves proximate to a gate region is larger than a size of a groove of the at least two grooves facing away from the gate region primarily to provide adequate depth for ohmic metal contact to optimize electrical performance so as to use an industrially tested and accepted device.
The Applicants Fig. 5 and Fig. 7shows varying types of grooves. Although a gate region larger than a size of a groove of the at least two grooves facing away from the gate region is not taught, it would have been obvious to adjust the configuration of spacing, shapes, and sizing so as to optimize the configurations for the given requirements of the design. The Applicants [0054] discloses: “Without considering the performance optimization, the sizes of the grooves can also be changed at will.” Thus, it is apparent the optimization of the spacing produces no unexpected results. The Applicant has not shown that a size of a groove of the at least two grooves proximate to a gate region is larger than a size of a groove of the at least two grooves facing away from the gate region is novel and would not have been found through routine experimentation. Nonetheless, it would have also been obvious to one having ordinary skill in the art at the time the invention was made to optimize the size of a groove of the at least two grooves proximate to a gate region is larger than a size of a groove of the at least two grooves facing away from the gate region so as to be able to provide adequate area for ohmic contact, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )
As to claim(s) 14, the semiconductor transistor according to claim 10, wherein
a spacing between two adjacent grooves of the at least two grooves proximate to a gate region is smaller than a spacing between two adjacent grooves of the at least two grooves facing away from the gate region.
The Matsushita/Huang combination does not appear to expressly disclose "a spacing between two adjacent grooves of the at least two grooves proximate to a gate region is smaller than a spacing between two adjacent grooves of the at least two grooves facing away from the gate region”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make a spacing between two adjacent grooves of the at least two grooves proximate to a gate region is smaller than a spacing between two adjacent grooves of the at least two grooves facing away from the gate region to provide adequate depth for ohmic metal contact to optimize electrical performance so as to use an industrially tested and accepted device.
The Applicants Fig. 5 and Fig. 7shows varying types of grooves. Although a gate region smaller than a spacing between two adjacent grooves of the at least two grooves facing away from the gate region is not taught, it would have been obvious to adjust the configuration of spacing, shapes, and sizing so as to optimize the configurations for the given requirements of the design. The Applicants [0054] discloses: “Without considering the performance optimization, the sizes of the grooves can also be changed at will.” Thus, it is apparent the optimization of the spacing produces no unexpected results. The Applicant has not shown that a spacing between two adjacent grooves of the at least two grooves proximate to a gate region is smaller than a spacing between two adjacent grooves of the at least two grooves facing away from the gate region is novel and would not have been found through routine experimentation. Nonetheless, it would have also been obvious to one having ordinary skill in the art at the time the invention was made to optimize the spacing between two adjacent grooves of the at least two grooves proximate to a gate region is smaller than a spacing between two adjacent grooves of the at least two grooves facing away from the gate region so as to be able to provide adequate area for ohmic contact, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )
As to claim(s) 15 and 17, Matsushita/Huang combination teaches the semiconductor transistor according to claim 1 and the manufacturing method for the semiconductor transistor according to claim 16, wherein
the barrier layer is made of AlGaN, ([col 3 lines 21-22] “The barrier layer 14 made of, for example, aluminum gallium nitride (AlGaN) and the channel layer is made of GaN. ([col 3 lines 11-12] “The buffer layer 12 made of, for example, gallium nitride (GaN) is stacked on the substrate 11”).
As to claim(s) 16, Matsushita teaches the manufacturing method for a semiconductor transistor, comprising:
sequentially forming a substrate, a channel layer, and a barrier layer ([col 3 lines 7-10] “As illustrated in FIG. 1B, in the semiconductor device 1, as the semiconductor layers, the buffer layer 12, the spacer layer 13, and the barrier layer 14 are sequentially stacked on the substrate 11”);
etching the ion implantation region ([col 4 lines 62-64] “These grooves may be formed, for example, by forming a mask using photoresist, digging the grooves through etching such as RIE, and removing the mask.) to define a groove (Annotated Fig. 6B ion implantation region), wherein a depth of the groove (Annotated Fig. 6B depth of the groove is less than that of the ion implantation region (Annotated Fig. 6B depth of the ion implantation region); and
depositing ohmic metal ([col 4 lines 65-66] “as illustrated in FIG. 3A, the drain electrode 17 and the source electrode 18 are formed.) on the ion implantation region (Annotated Fig. 6B depth of the ion implantation region), wherein the ohmic metal (18) is in ohmic contact with a non-groove region of the ion implantation region (Annotated Fig. 6B ion implantation region), a sidewall of the groove (Annotated Fig. 6B sidewall of the groove), and a bottom of the groove (Annotated Fig. 6B bottom of the groove); and
an area of a vertical projection of the groove (Fig. 2C groove 15a/Fig. 6B 18a) on the substrate (Fig. 6B substrate 11) is greater than or equal to half of an area of a vertical projection of the ohmic metal (18) on the substrate (Fig. 6B substrate 11);.
Matsushita does not appear to expressly disclose "forming, by ion implantation, an ion implantation region in at least one of a source region and a drain region of the barrier layer”
However, Huang does teach ion implementation into the source drain region. Huang [0140], discloses “multiple ion implantation is adopted to implant n-type silicon dopants below the drain and source electrodes.” Ion implantation is performed in the source/drain (S/D) regions to introduce specific dopant atoms so as to alter its electrical properties. This technique is used to create conductive, low-resistance regions that allow the transistor to operate efficiently, providing precise control over doping concentration, depth, and uniformity.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to implant multiple ions as in the Huang device, into the source/drain area of the Matsushita device, so as to control the depth and placement of the ohmic contact. While claims don’t need to be performed in a particular order (i.e. etching and depositing) it would have been obvious to perform the implantation step before the depositing step, so as to have an even ion implantation depth route, allowing for more robust device.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
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