Prosecution Insights
Last updated: July 17, 2026
Application No. 18/395,593

POLYMERIC DIE PAD FOR DIE ISOLATION IN CHIP ON LEAD PACKAGE

Non-Final OA §102
Filed
Dec 24, 2023
Examiner
ISAAC, STANETTA D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
48%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
824 granted / 963 resolved
+17.6% vs TC avg
Minimal -37% lift
Without
With
+-37.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
47 currently pending
Career history
1022
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.7%
+22.7% vs TC avg
§102
35.6%
-4.4% vs TC avg
§112
1.4%
-38.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 963 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claim 1-11 in the reply filed on 2/17/26 is acknowledged. Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/17/26. Information Disclosure Statement The information disclosure statements (IDS) were submitted on 12/24/23 and 6/16/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noquil et al. (US PGPub 2021/0090980, hereinafter referred to as “Noquil”). Noquil discloses the semiconductor device as claimed. See figures 1A-6 and corresponding text, where Noquil teaches, in claim 1, a semiconductor package, comprising: (figures 1A-1C; [0019-0021]) a lead frame portion (110) including leads (112), the leads being electrically conductive and extending to an exterior of the semiconductor package; a polymeric die pad attached (191) to a plurality of the leads (112); and a semiconductor die (140) attached to the polymeric die pad (191); wherein: the polymeric die pad (191) is electrically non-conductive; and the polymeric die pad extends laterally past the semiconductor die (140) on all sides. Noquil teaches, in claim 2, wherein the polymeric die pad is attached to the plurality of the leads through a die pad adhesive (figures 1A-1C; [0019-0021]). Noquil teaches, in claim 3, wherein the die pad adhesive is coterminous with the polymeric die pad (figures 1A-1C; [0019-0021]). Noquil teaches, in claim 4, wherein the semiconductor die is attached to the polymeric die pad through a die attach paste (figures 1A-1C; [0019-0021]). Noquil teaches, in claim 5, wherein the die attach paste extends laterally past the semiconductor die (figures 1A-1C; [0019-0021]). Noquil teaches, in claim 6, wherein the die attach paste includes electrically conductive particles (figures 1A-1C; [0019-0021]). Noquil teaches, in claim 7, wherein the semiconductor die is attached to the polymeric die pad through a die attach film (figures 1A-1C; [0019-0021]). Noquil teaches, in claim 8, wherein the die attach film is coterminous with semiconductor die (figures 1A-1C; [0019-0021]). Noquil teaches, in claim 9, wherein the polymeric die pad includes polyimide (figures 1A-1C; [0019-0021]). Noquil teaches, in claim 10, wherein the semiconductor die is a first semiconductor die, and further including a second semiconductor die attached to the polymeric die pad (figures 1A-1C; [0019-0021]). Noquil teaches, in claim 11, wherein: (figures 1A-1C; [0019-0021]) the polymeric die pad is a first polymeric die pad; the plurality of the leads is a first plurality of the leads; and the semiconductor die is a first semiconductor die; and further including: a second polymeric die pad attached to a second plurality of the leads; and a second semiconductor die attached to the second polymeric die pad; wherein: the second polymeric die pad is electrically non-conductive; and the second polymeric die pad extends laterally past the second semiconductor die on all sides. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/Examiner, Art Unit 2898 May 16, 2026
Read full office action

Prosecution Timeline

Dec 24, 2023
Application Filed
May 20, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
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Patent 12672498
METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE
4y 11m to grant Granted Jun 30, 2026
Patent 12672367
SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE
2y 9m to grant Granted Jun 30, 2026
Patent 12667003
LIGHT-EMITTING PANEL, METHOD FOR FABRICATING SAME, AND DISPLAY DEVICE
3y 11m to grant Granted Jun 23, 2026
Patent 12648440
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4y 2m to grant Granted Jun 02, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
48%
With Interview (-37.1%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 963 resolved cases by this examiner. Grant probability derived from career allowance rate.

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