Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in Taiwan on 11/22/2023.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 12/24/2023 and 05/14/2024 has/have been considered by the examiner and made of record in the application file.
Drawings
The drawings are objected to because Figures 4 and 5 include values which are not clearly defined by the specification and create confusion as to what is being measured. The x-axis of Figures 4 and 5 are labelled as “Normalized offset distance (x/Lx) in the first direction” and the values extend from -1 to 0.2. The value “x” is defined in the specification as “the width of the first spacing s1 in the first direction d1” and the value “Lx” is defined as the first width of the contact window #132 in the first direction (see Figure 3 and [0027]-[0028]). Because both of these values are widths in the structure, it is unclear how a negative value, as provided on the graph, may exist. A width of a physical element or distance between two elements cannot have a negative value. While a distance in a direction may have a negative value with respect to an origin (i.e. a distance traversed in the negative x-direction may be negative), a width cannot be negative. There is no explanation provided in the specification to explain how these values can be negative or what they are normalized to as indicated by the axis titles.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for the width of the first/second spacing (x/y) being equal to 0.2 times the width of the first and/or second contact window (Lx and/or Ly) (see the rightmost data point(s) and dashed lines in Figures 4 and 5), does not reasonably provide enablement for the width of the first and/or second spacing (x and/or y) being greater than 0.2 times the width of the first and/or second contact window (Lx and/or Ly). The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims.
Enablement, or lack thereof, is best understood through a framework of factors, referred to as the Wands factors (see MPEP 2164.01(a)), to assess whether any necessary experimentation required by the specification is “reasonable” or is “undue”, several of which will be elaborated on in relation to the claimed invention below.
The breadth of the claims (MPEP 2164.08) – The claims include values of the width of the first and/or second spacing (x and/or y) being greater than 0.2 times the width of the first and/or second contact window (0.2·Lx and/or 0.2·Ly) with no upper limit. These limitations as provided in claims 3 and 4 effectively encompass an infinite breadth and could include values of 10x, 20x, etc. the width of the first and/or second contact window. This range is therefore outside of the scope of enablement provided by the instant application which provides only one example at 0.2·Lx or 0.2·Ly in either the figures or specification. “When a range is claimed, there must be reasonable enablement of the scope of the range.” (MPEP 2164.08)
The nature of the invention and the state of the prior art (MPEP 2164.05(a)) and the level of one of ordinary skill (MPEP 2164.05(b)) – The nature of the invention and prior art is such that it is understood that increasing the area over which a stress (physical or temperature based) is applied may mitigate the damage done by said stress by reducing the stress at any one point. One may reasonably interpret therefore that increasing the area of a contact or wiring line, by increasing the spacing between adjacent associated contact holes, may lead to a reduction in damage from received stress. However, the claimed range does not solely encompass an increase in area over which a stress may be applied. Instead, applicant has claimed that an increase in normalized offset distance relative to contact window width results in a reduced stress on the system. This encompasses contacts and/or wiring lines structures which may be smaller even then those which are common in the art but still meet the claimed ratio value for width of the first/second spacing to the width of the first and/or second contact window (Lx and/or Ly). This represents a more complex structure where very small contact structures, even with a large area relative to the contact window, may experience large amounts of stress over a small area. Furthermore, because only a single data point in the claimed range is provided, undue experimentation would be required to enable the full scope of the claims.
The level of predictability in the art and the amount of direction provided by the inventor (MPEP 2164.03)– The application provides only a single data point at the very start of the claimed range. No values beyond 0.2·Lx are provided in either the figures or discussed in the specification. In [0028] of the specification, the applicant claims that any value equal to or beyond 0.2·Lx will lead to a significant decrease in both the shear stress and the tensile stress. Because no data points are given for the values within this range other than the very first lower limit value, it is the examiner’s interpretation that the applicant has not provided sufficient direction for determining what the true limits are of this extensive range. Based on the examiner’s understanding of the technology, by increasing the value of the width of the first and/or second spacing (x and/or y) to being greater than 0.2 times the width of the first and/or second contact window (Lx and/or Ly), the area over which the stresses and temperature increases are exerted is increased (see [0028] and [0026]). This increase in area leads to an overall reduction in stress and less likelihood of peeling under the stress as stated in [0003] of the specification. However, the graphs provided in Figure 4 and 5 include negative values without explanation (see drawings objection above). If the art followed the predictions made above, the large negative values would also result in a reduced stress due to the larger areas, however, that is not shown to be the case. For these reasons the lack of predictability in the art based on the direction provided by the inventor(s) renders the claimed ranges to not be enabled to their full scope.
The existence of working examples (MPEP 2164.02) – The inventors/applicant have provided only a single working example at the lowest bound of their claimed range. No other examples are provided. The examiner notes here as well that while the lower bound of 0.2·Lx having a lower stress is shown by the graph, these represent normalized values according to the axis titles. No details are provided as to what the values are normalized to and no values are put on the actual lengths beyond the general ratio. Based on this specification alone, the examiner is left to interpret that any Lx and/or Ly and corresponding x and/or y value that meets the claimed criteria will be provided the same benefits of reduced stress and peeling issues. However, because no values at all are provided in the specification, it is the examiner’s interpretation that the scope is not enabled.
The quantity of experimentation needed to make or use the invention based on the content of the disclosure (MPEP 2164.06) – In order to make the claimed invention, a person of ordinary skill in the art (POSITA) would be required to perform undue experimentation. The POSITA would first need to experiment sufficiently to find the appropriate scale of this structure and determine the normalization factor used by the inventor(s) and/or applicant since no details are provided. After determining scale and appropriate normalization, significant experimentation would still be required to determine if there is any sort of an upper limit to the reported beneficial range. Figures 4 and 5 only show a decrease in stress between two data points with no further details. It is therefore required of the POSITA to determine if the decreasing stress levels off at a certain x-axis value or continues to drop all the way to zero stress at a sufficiently large value on the x-axis.
For these reasons, as detailed in the above Wands factors, claim(s) 3 and 4 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for the width of the first/second spacing (x/y) being equal to 0.2 times the width of the first and/or second contact window (Lx and/or Ly) (see the rightmost data point(s) and dashed lines in Figures 4 and 5), does not reasonably provide enablement for the width of the first and/or second spacing (x and/or y) being greater than 0.2 times the width of the first and/or second contact window (Lx and/or Ly).
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation “the first conductive pattern has an area laid between the first contact window and the second contact window, the area of the first conductive pattern is smaller than or equal to ten times an area of the first contact window”. This limitation first introduces a sub-area of the first conductive pattern which is located between the first and second contact windows. This sub-area is interpreted to be a portion of an overall area of the first conductive pattern. The second recitation of “the area of the first conductive pattern” then renders the claim indefinite as it is unclear which area is being referred to. It is unclear if the second recitation is referring to the sub-area which was earlier recited as being between the first and second contact window since applicant uses the phrase “the area” (first interpretation) or if the second recitation of “the area of the first conductive pattern” refers to the entire area of the first conductive pattern since the further limiting feature of “laid between the first contact window and the second contact window” is not provided in the second recitation (second interpretation). When this limitation is described in the specification ([0028], “the area of the first conductive pattern 140 is smaller than or equal to ten times the area of the first contact window 132”), it appears to be referencing the area of the entire first conductive pattern (second interpretation). Therefore, claim(s) 5 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this examination, the interpretation is made that first and second recitations of “area” are referencing the same region such that claim 5 may read as “the first conductive pattern has an area laid between the first contact window and the second contact window, the area of the first conductive pattern laid between the first contact window and the second contact window is smaller than or equal to ten times an area of the first contact window”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 5-7 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0054923 A1; Kim et al.; 02/2025; (“Kim”). An annotated version of Figure 2 from Kim is provided below and referenced in the following rejection.
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Regarding Claim 1. Kim discloses A pixel structure (Figure 2, display device where Figure 3 is a cross section of Figure 2 along the line III-III’, according to [0058]-[0059]), comprising:
a pixel driving circuit (#ACT2 and #GE2, Figure 2, gate electrode and active layer of a transistor which may be driving transistor according to [0101]);
a first insulating layer (#113, Figure 3, passivation layer which may be an insulating layer according to [0091]) disposed on the pixel driving circuit and having a first contact window (Figure 3, #113 is disposed on the combination of #ACT2 and #GE2 and has a contact window where #ST1/#SE2 passes through it), wherein the first contact window overlaps the pixel driving circuit (Figure 3, the contact window in #113 directly overlaps #ACT2 of the driving transistor);
a first conductive pattern (#ST2 and #SE2, Figure 3, second capacitor electrode and source electrode forming a continuous conductive pattern) disposed on the first insulating layer and electrically connected to the pixel driving circuit through the first contact window (Figure 3, the combination of #ST2 and #SE2 is disposed directly on #113 and is electrically connected to #ACT2 through the opening in #113);
a second insulating layer (#115, Figure 3, second passivation layer which may be an insulating material according to [0113]) disposed on the first insulating layer and the first conductive pattern (Figure 3, #115 is on #113 and the combination of #ST2 and #SE2 where “on” does not require direct contact according to [0013] of the instant application), wherein the second insulating layer has a second contact window (Figure 3, #115 has a contact window where #CE passes through it), and the second contact window overlaps the first conductive pattern (Figure 3, the opening in #115 at least partially overlaps with #ST2);
a second conductive pattern (#CE, Figure 3, connection electrode) disposed on the second insulating layer and electrically connected to the first conductive pattern through the second contact window (Figure 3, #CE is located on #115 and is electrically connected to #ST2 and #SE2 through the opening in #115);
a plurality of bonding pads (#121s and #122s, Figures 2 and 3, assembly wirings which are bonded to the light emitting device #130 according to [0158]) disposed on the second insulating layer (Figure 3, #121s and #122s are disposed on #115), wherein one of the bonding pads is connected to the second conductive pattern (Figure 3, #122s and #121s are physically connected to #CE where “connected” does not require direct connection according to [0013] of the instant application); and
a light-emitting element (#130, Figure 3, light emitting device) electrically connected to the plurality of bonding pads (Figures 2 and 3, #130s are electrically connected to the plurality of #122s);
wherein in a top view of the pixel structure (Figure 2), the plurality of bonding pads are arranged in a first direction (Figure 2, the plurality of #121s and #122s are arranged in the row direction), a second direction (Figure 2, column direction) is perpendicular to the first direction (Figure 2, column and row directions are perpendicular to one another), the first contact window and the second contact window have a first spacing in the first direction (Figures 2 and 3, the contact windows, labelled as the boxed x symbols in #CE and #SE2, in #115 and #113 along the line III-III’ are spaced apart in the row direction), and the first contact window and the second contact window have a second spacing in the second direction (Figures 2 and 3, the contact windows, labelled as the boxed x symbols in #CE and #SE2, in #115 and #113 along the line III-III’ are spaced apart in the column direction).
Regarding Claim 2. Kim discloses The pixel structure according to claim 1, wherein in the top view of the pixel structure (Figure 2), the first contact window and the second contact window are arranged in a third direction (Figure 2 annotated and Figure 3, the contact windows, labelled as the boxed x symbols in #CE and #SE2, in #115 and #113 along the line III-III’ arranged along a 3rd direction in the annotated Figure 2), and the third direction interlaces with the first direction and the second direction (Figure 2 annotated, the third direction interlaces with the row and column directions).
Regarding Claim 5. Kim discloses The pixel structure according to claim 1, wherein in the top view of the pixel structure, the first conductive pattern has an area laid between the first contact window and the second contact window (Figures 2 and 3, #SE2 and #ST2 have an area laid between the first contact window in #113 and the second contact window in #115), the area of the first conductive pattern laid between the first contact window and the second contact window is smaller than or equal to ten times an area of the first contact window (Figures 2 and 3, any arbitrarily sized area of #ST2 and #SE1 between the two contact holes may be selected as there are no defined bounds beyond that, this are may be selected as appropriate to be smaller than or equal to 10 times the area of the contact window in #113).
Regarding Claim 6. Kim discloses The pixel structure according to claim 1, wherein the first conductive pattern has a first part (Figures 2 and 3, #ST2, the portion of the second capacitor electrode which is overlapping with #ST1) connected with a second part (Figures 2 and 3, #SE2, the portion of the source electrode which is overlapping with #ACT2), the first part overlaps the second contact window (Figure 3, #ST2 overlaps at least partially with the contact window in #115) and extends in the first direction (Figure 3, #ST2, being a three-dimensional structure, at least partially extends in the row direction), the second part overlaps the first contact window (Figure 3, #SE2 overlaps at least partially with the contact window in #113) and extends in the second direction (Figure 3, #SE2, being a three-dimensional structure, at least partially extends in the column direction).
Regarding Claim 7. Kim discloses The pixel structure according to claim 6, wherein the second conductive pattern overlaps the first part of the first conductive pattern (Figure 3, #CE at least partially overlaps with #ST2), and does not overlap the second part of the first conductive pattern (Figure 3, #CE does not overlap with the portion of #SE2 which is over #ACT2).
Allowable Subject Matter
Claim(s) 3 and 4 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(a) as set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
As described above in the 35 U.S.C. 112(a) rejection of claims 3 and 4, the specification is enabling for the width of the first/second spacing (x/y) being equal to 0.2 times the width of the first and/or second contact window (Lx and/or Ly) (see the rightmost data point(s) and dashed lines in Figures 4 and 5). However, the specification does not reasonably provide enablement for the width of the first and/or second spacing (x and/or y) being greater than 0.2 times the width of the first and/or second contact window (Lx and/or Ly). No prior art was identified which teaches the width of the first/second spacing (x/y) being equal to 0.2 times the width of the first and/or second contact window (Lx and/or Ly). Therefore, depending on how applicant responds to the rejection of claims 3 and 4 under 35 U.S.C. 112(a), claims 3 and 4 may include allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2026/0006957 A1; Meng et al.; 01/2026 – Figures 14 and 15 teach details of spacing and appropriate gaps between contact windows of underlying vias and neighboring light emitters and driving transistor structures. However, no details appear to be provided for the spacings relative to the areas or dimensions of the underlying vias.
US 2025/0143045 A1; Choi et al.; 05/2025 – Figure 7 details a plurality of underlying via structures connecting a driving transistor to an LED structure through a plurality of bonding pads and the via structures are slightly offset from one another. However, no details appear to be provided for the spacings relative to the areas or dimensions of the underlying vias.
US 2024/0186472 A1; Yoon et al.; 06/2024 – Figures 1 and 2 provide a structure similar to that of the Kim reference relied upon in the rejection above.
US 2023/0238372 A1; Lee et al.; 07/2023 – Figures 6 and 7 detail a plurality of underlying via structures connecting a driving transistor to an LED structure through a plurality of bonding pads and the via structures are slightly offset from one another. However, no details appear to be provided for the spacings relative to the areas or dimensions of the underlying vias.
US 2021/0296537 A1; Lee et al.; 09/2021 – Figures 8 and 9 detail a plurality of underlying via structures connecting a driving transistor to an LED structure through a plurality of bonding pads and the via structures are slightly offset from one another. However, no details appear to be provided for the spacings relative to the areas or dimensions of the underlying vias.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE KIM can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TYLER J WIEGAND/Examiner, Art Unit 2812