DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 08/09/2026, in which claims 1, 8 were amended, claims 2, 15-18 were cancelled, claims 9-10 were withdrawn, claim 19 was added, has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application CN202310014562.0 filed on 01/05/2023. The foreign application is not in English. The certified copy of the foreign priority application CN202310014562.0, an English translation of the non-English language foreign application CN202310014562.0 and a statement that the translation is accurate in accordance with 37 CFR 1.55 have been received.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, claim 3 recites “spin-coating the second surface of the substrate with the varnish” while claim 1 on which claim 3 depends recites “disposing the substrate over the jig such that the plurality of conductive pillars are immersed in the varnish and the second surface of the substrate contacts the varnish.” It is unclear how spin-coating the second surface of the substrate with the varnish if the plurality of conductive pillars are immersed in the varnish and the second surface of the substrate contacts the varnish.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. (US Pub. 20200258803) in view of Chen et al. (US Pub. 20140346666) and Hosokawa (US Pub. 20240387104).
Regarding claim 1, Bang et al. discloses in Fig. 6E-6J a method for making a semiconductor device, comprising:
providing a substrate [114] having a first surface and a second surface opposite to the first surface, wherein a plurality of conductive pillars [121 and 122] are formed on the second surface of the substrate [114][Fig. 6G];
forming a polyimide layer [123] on the second surface of the substrate [114] to cover the plurality of conductive pillars [121 and 122][Fig. 6H, paragraph [0028]];
mounting a first electronic component [130] on the first surface of the substrate [114][Fig. 6J, paragraph [0058]]; and
forming a first encapsulant [150] on the first surface of the substrate [114] to cover the first electronic component [130][Fig. 6J, paragraph [0058]].
Bang et al. fails to disclose
wherein forming the polyimide layer on the second surface of the substrate comprises:
providing a jig configured for holding a varnish comprising polyimide material;
disposing the substrate over the jig such that the plurality of conductive pillars are immersed in the varnish and the second surface of the substrate contacts the varnish; and
heating the varnish with a heater disposed under the jig to perform imide- conversion, thereby forming the polyimide layer on the second surface of the substrate.
Chen et al. discloses in Fig. 8C-8D
wherein forming the polyimide layer on a second surface of a substrate [92] comprises:
providing a jig [96] configured for holding a varnish [M1] comprising polyimide [PI] material [paragraph [0065]];
disposing the substrate [92] over the jig [96] such that the plurality of conductive pillars [510b] are immersed in the varnish [M1] and the second surface of the substrate [92] contacts the varnish [M1]; and
heating the varnish [M1] to perform imide- conversion, thereby forming the polyimide layer [M2] on the second surface of the substrate [92][Fig. 8D, paragraph [0065]].
Hosokawa discloses in Fig. 1b, paragraph [0058]
heating the varnish [liquid resin 16] with a heater [18] disposed under the jig [container containing liquid resin 16].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen et al. and Hosokawa into the method of Bang et al. to include wherein forming the polyimide layer on the second surface of the substrate comprises: providing a jig configured for holding a varnish comprising polyimide material; disposing the substrate over the jig such that the plurality of conductive pillars are immersed in the varnish and the second surface of the substrate contacts the varnish; and heating the varnish with a heater disposed under the jig to perform imide- conversion, thereby forming the polyimide layer on the second surface of the substrate. The ordinary artisan would have been motivated to modify Bang et al. in the above manner for the purpose of providing suitable method for forming the polyimide layer on the second surface of the substrate. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 4, Bang et al. discloses in Fig. 6H, paragraph [0055]
planarizing the polyimide layer [123] before mounting the first electronic component [130] on the first surface of the substrate [114].
Regarding claim 14, Bang et al. discloses in Fig. 6G, paragraph [0053]-[0054] wherein the plurality of conductive pillars [121 and 122] comprises a copper pillar.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. (US Pub. 20200258803) in view of Chen et al. (US Pub. 20140346666) and Hosokawa (US Pub. 20240387104) as applied to claim 1 above and further in view of Lin et al. (US Pub. 20210327822)
Regarding claims 5-6, Bang et al. fails to disclose
wherein forming the first encapsulant comprises:
providing a molding apparatus comprising a top chase and a bottom chase, wherein a molding material is held in the bottom chase;
attaching the polyimide layer onto the top chase of the molding apparatus; and
moving the top chase and the bottom chase close to each other to compress the molding material to cover the first electronic component on the first surface of the substrate, thereby forming the first encapsulant on the first surface of the substrate;
separating the top chase and the bottom chase from each other; and
removing the substrate from the molding apparatus.
Lin et al. discloses in Fig. 4A-4D, Fig. 4H, paragraph [0044]-[0046]
wherein forming the first encapsulant [43] comprises:
providing a molding apparatus comprising a top chase [51] and a bottom chase [53], wherein a molding material [43] is held in the bottom chase [53];
attaching a substrate layer [bottom portion of 41] onto the top chase [51] of the molding apparatus; and
moving the top chase [51] and the bottom chase [53] close to each other to compress the molding material [43] to cover the first electronic component [45] on the first surface [411] of the substrate [upper portion of 41], thereby forming the first encapsulant [43] on the first surface [411] of the substrate [upper portion of 41];
separating the top chase [51] and the bottom chase [53] from each other; and
removing the substrate [41] from the molding apparatus.
Bang et al. discloses the substrate layer adjacent to the substrate [114] is the polyimide layer [123]. Applying Lin et al. method into Bang et al. would result to “attaching the polyimide layer onto the top chase of the molding apparatus.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lin et al. into the method of Bang et al. to include wherein forming the first encapsulant comprises: providing a molding apparatus comprising a top chase and a bottom chase, wherein a molding material is held in the bottom chase; attaching the polyimide layer onto the top chase of the molding apparatus; and moving the top chase and the bottom chase close to each other to compress the molding material to cover the first electronic component on the first surface of the substrate, thereby forming the first encapsulant on the first surface of the substrate; separating the top chase and the bottom chase from each other; and removing the substrate from the molding apparatus. The ordinary artisan would have been motivated to modify Bang et al. in the above manner for the purpose of providing detail description of a method for forming the first encapsulant [paragraph [0043]-[0046] of Lin et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. (US Pub. 20200258803) in view of Chen et al. (US Pub. 20140346666) and Hosokawa (US Pub. 20240387104) as applied to claim 1 above and further in view of Park (US Pub. 20130181342).
Regarding claim 7, Bang et al. fails to disclose
grinding the polyimide layer to expose the plurality of conductive pillars after forming the first encapsulant on the first surface of the substrate.
Park discloses in Fig. 4, Fig. 5, paragraph [0054], [0059], [0065],
grinding an encapsulant layer [40] to expose the plurality of conductive pillars [51] after forming the first encapsulant [30] on the first surface of the substrate [10].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Park into the method of Bang et al. to include grinding the polyimide layer to expose the plurality of conductive pillars after forming the first encapsulant on the first surface of the substrate. The ordinary artisan would have been motivated to modify Bang et al. in the above manner for the purpose of providing suitable order for performing the step of grinding the polyimide layer to expose the plurality of conductive pillars. Further, selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946). Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. (US Pub. 20200258803) in view of Chen et al. (US Pub. 20140346666), Hosokawa (US Pub. 20240387104) and Park (US Pub. 20130181342) as applied to claim 7 above and further in view of Siomkos et al. (US Pub. 20200075547).
Regarding claim 8, Bang et al. fails to disclose
mounting a second electronic component on a first set of the plurality of conductive pillars; and
forming a second encapsulant on the polyimide layer, wherein the second encapsulant covers the plurality of conductive pillars and the second electronic component.
Siomkos et al. discloses in Fig. 1, Fig. 4Fparagraph [0031]-[0036],
mounting a second electronic component [24] on a first set of the plurality of conductive pillars [48]; and
forming a second encapsulant [28] on the plurality of conductive pillars [48], wherein the second encapsulant [28] covers the plurality of bumps [34] and the second electronic component [24].
The combination of Siomkos et al. and Bang et al. would result to “forming a second encapsulant disposed on the polyimide layer.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Siomkos et al. into the method of Bang et al. to include mounting a second electronic component on a first set of the plurality of conductive pillars; and forming a second encapsulant on the polyimide layer, wherein the second encapsulant covers the plurality of conductive pillars and the second electronic component. The ordinary artisan would have been motivated to modify Bang et al. in the above manner for the purpose of providing a double-sided integrated circuit (IC) module to form a compact electronic device having various functionalities [paragraph [0001]-[0008] of Siomkos et al.].
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. (US Pub. 20200258803) in view of Chen et al. (US Pub. 20140346666), Hosokawa (US Pub. 20240387104), Park (US Pub. 20130181342) and Siomkos et al. (US Pub. 20200075547) as applied to claim 8 above and further in view of Lin et al. (US Pub. 20110278736), hereafter Lin736.
Regarding claims 11-13, Bang et al. fails to disclose
planarizing the second encapsulant to expose the second electronic component;
forming one or more cavities in the second encapsulant to expose top surfaces of a second set of the plurality of conductive pillars; and
forming a bump in each of the one or more cavities to electrically connect a respective conductive pillar;
wherein forming the bump in each of the one or more cavities comprises:
printing solder paste into the one or more cavities of the second encapsulant; and
reflowing the solder paste to form the bump;
forming an electromagnetic interference (EMI) shielding layer, wherein the EMI shielding layer at least covers the first encapsulant.
Siomkos et al. discloses in Fig. 2, Fig. 4F, paragraph [0031]-[0036], [0041]
planarizing the second encapsulant [28] to expose the second electronic component [24/50];
forming a bump [34 or 34a] to electrically connect a respective conductive pillar [48];
forming an electromagnetic interference (EMI) shielding layer [32], wherein the EMI shielding layer [32] at least covers the first encapsulant [30].
Lin736 discloses in Fig.13s, Fig. 18b, Fig. 20a-20b, Fig. 22b, paragraph [0150], [0153], [0193]-0194]
planarizing the second encapsulant [178, 286 or 586 or 504] to expose the second electronic component [276 or 584];
forming one or more cavities [582] in the second encapsulant [586] to expose top surfaces of a second set of the plurality of conductive pillars [302]; and
forming a bump [356] in each of the one or more cavities to electrically connect a respective conductive pillar [302];
wherein forming the bump [356] in each of the one or more cavities comprises:
printing solder paste into the one or more cavities of the second encapsulant [504]; and
reflowing the solder paste to form the bump [356].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Siomkos et al. and Lin736 into the method of Bang et al. to include planarizing the second encapsulant to expose the second electronic component; forming one or more cavities in the second encapsulant to expose top surfaces of a second set of the plurality of conductive pillars; and forming a bump in each of the one or more cavities to electrically connect a respective conductive pillar; wherein forming the bump in each of the one or more cavities comprises: printing solder paste into the one or more cavities of the second encapsulant; and reflowing the solder paste to form the bump; forming an electromagnetic interference (EMI) shielding layer, wherein the EMI shielding layer at least covers the first encapsulant. The ordinary artisan would have been motivated to modify Bang et al. in the above manner for the purpose of providing a shielded double-sided integrated circuit (IC) module includes an exposed semiconductor die on a bottom side to form a compact electronic device having various functionalities, having reduced electromagnetic interference; and providing a surface to which a heat exchange device can be coupled and providing suitable method for forming an interconnect structure for 3-D semiconductor devices [paragraph [0001]-[0008] of Siomkos et al.; paragraph [0013], [0153] of Lin736]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. (US Pub. 20200258803) in view of Chen et al. (US Pub. 20140346666) and Hosokawa (US Pub. 20240387104) as applied to claim 1 above and further in view of Chen (US Pub. 20190189565).
Regarding claim 19, Bang et al. fails to disclose
wherein the semiconductor device is double side molding (DSM) package, and the method further comprises:
mounting a third electronic component on the second surface of the substrate, wherein the third electronic component has a height smaller than that of the plurality of conductive pillars.
Chen discloses in Fig. 8, paragraph [0046]
wherein the semiconductor device is double side molding (DSM) package, and
the method further comprises:
mounting a third electronic component [261 or 262] on the second surface of the substrate, wherein the third electronic component [261 or 262] has a height smaller than that of the plurality of conductive pillars [291 and 293].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen into the method of Bang et al. to include wherein the semiconductor device is double side molding (DSM) package, and the method further comprises: mounting a third electronic component on the second surface of the substrate, wherein the third electronic component has a height smaller than that of the plurality of conductive pillars. The ordinary artisan would have been motivated to modify Bang et al. in the above manner for the purpose of providing suitable configuration of a semiconductor device package comprising electronic components with different functions being integrated into the package [paragraph [0038], [0046] of Chen].
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-8, 11-14, 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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