Prosecution Insights
Last updated: October 25, 2026
Application No. 18/395,650

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME

Final Rejection §103
Filed
Dec 25, 2023
Priority
Jan 05, 2023 — CN 202310014572.4
Examiner
TRAN, TAN N
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Jcet Stats Chippac Korea Limited
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
980 granted / 1128 resolved
+18.9% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
36 currently pending
Career history
1168
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
34.0%
-6.0% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1128 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 1. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 2. Claims 8, 11 – 13, 16 are rejected under 35 U.S.C. 103 as being unpatentable over SHIMAMURA et al. (20130271928) in view of Salmon et al. (20210407927). With regard to claim 8, SHIMAMURA et al. disclose a method for manufacturing an electronic device (for example, see figs. 5(A), 5(B), 5(C)) wherein the method comprises: providing a substrate (2) with at least one electronic component (31 or 32) and at least one metal bar (4; for example, see paragraph [0097]) mounted thereon; forming an encapsulant layer (5) on the substrate (2) to encapsulate the at least one electronic component (31 or 32) and the at least one metal bar (4) and expose (exposed from the encapsulant layer 5) a top surface of each of the at least one metal bar (4); forming at least one trench (concave part 52, fig. 5(B) functions as one trench) adjacent to and around the at least one metal bar (4), respectively, to expose an upper portion of a lateral surface (side surface) of each of the at least one metal bar (4) from the encapsulant layer (5); and forming a shielding layer (6) over the encapsulant layer (5) and the at least one metal bar (4), wherein the shielding layer (6) is in contact with the at least one metal bar (4). PNG media_image1.png 628 659 media_image1.png Greyscale SHIMAMURA et al. do not clearly disclose the bar protrudes above the encapsulant layer However, Salmon et al. discloses the bar (sidewall structure 328 of the layer 330 functions as a bar) protrudes above the encapsulant layer (338). (for example, see paragraph 0023], fig. 3B). PNG media_image2.png 548 774 media_image2.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SHIMAMURA et al.’s device to have the bar protrudes above the encapsulant layer as taught by Salmon et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. With regard to claim 11, SHIMAMURA et al. disclose forming the at least one trench (52) comprises: forming the at least one trench using laser ablation (for example, see paragraph [0082]). With regard to claim 12, SHIMAMURA et al. disclose each of the at least one trench (52) comprises a sloping surface that slopes towards the metal bar (4, fig. 5(B)). With regard to claim 13, SHIMAMURA et al. disclose the substrate (2) comprises a ground layer (a terminal layer 23a1, electrically connected to the ground potential, functions as a ground layer; for example, see paragraph [0103]), and each of the at least one metal bar (4) is electrically coupled to the ground layer (23a1). With regard to claim 16, SHIMAMURA et al. do not clearly disclose the at least one metal bar is higher than the at least one electronic component. 3. Claims 14, 15 are rejected under 35 U.S.C. 103 as being unpatentable over SHIMAMURA et al. (20130271928) in view of Salmon et al. (20210407927) and further in view of Rofougaran et al. (8811923). With regard to claims 14, 15, SHIMAMURA et al. and Salmon et al. do not clearly disclose the at least one electronic component comprises a wireless communication module; wherein the wireless communication module comprises a voltage-controlled oscillator circuit. However, Rofougaran et al. discloses the at least one electronic component (150) is a wireless communication module; wherein the wireless communication module (150) comprises a voltage-controlled oscillator circuit (165). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SHIMAMURA et al. and Salmon et al.’s device to have the at least one electronic component comprises a wireless communication module; wherein the wireless communication module comprises a voltage-controlled oscillator circuit as taught by Rofougaran et al. in order to generate a clock signal efficiency for use by various circuitry for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. Allowable Subject Matter 4. Claims 9, 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 9, 10 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as forming the encapsulant layer on the substrate comprises: attaching a film on the top surface of each of the at least one metal bar or on a mold chase; placing the mold chase over the substrate to form a molding chamber between the mold chase and the substrate, wherein the mold chase comprises at least one cavity accommodating the at least one metal bar, respectively, and the film is between the mold chase and the top surface of each of the at least one metal bar; injecting into the molding chamber an encapsulant material; solidifying the encapsulant material; and detaching the films from the at least one metal bar to expose the respective top surface of the at least one metal bar as recited in claim as recited in claim 9. Response to Amendment 5. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Conclusion 6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TAN N TRAN/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Dec 25, 2023
Application Filed
Jun 18, 2026
Non-Final Rejection mailed — §103
Sep 17, 2026
Response Filed
Oct 06, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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DRIVING SUBSTRATES AND DISPLAY PANELS
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Patent 12765388
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Patent 12740260
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+9.9%)
2y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1128 resolved cases by this examiner. Grant probability derived from career allowance rate.

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