DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 11-17 in the reply filed on 12/25/2023 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-14 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20220254784 A1, hereinafter Lee)
With regards to claim 11, Lee discloses a semiconductor structure, (FIGS. 1B and 20B-20C) comprising:
a base; (base 2000)
a plurality of active structures (access lines 2077 and oxide 2063) arranged on a surface of the base, wherein the plurality of active structures are spaced from each other along a first direction and a second direction, (D1 and D3) the plurality of active structures comprise a plurality of oxide semiconductor layers (oxide 2063 directly contacting line 2077) and a plurality of initial active layers (access lines 2077) both arranged along a third direction, (D2) and each of the plurality of oxide semiconductor layers is in contact with a respective one of the plurality of initial active layers, the first direction is perpendicular to the surface of the base, (See FIG. 20C) the second direction is parallel to the surface of the base, and the third direction is parallel to the surface of the base and is perpendicular to the second direction; (See FIG. 20C) and
a plurality of first isolation layers, (dielectric fill 2039) wherein the plurality of first isolation layers are arranged between the plurality of active structures adjacent to each other in the first direction, a projection of each of the plurality of first isolation layers on the surface of the base overlaps with a projection of a respective one of the plurality of active structures on the surface of the base. (see FIGS. 20B-C)
With regards to claim 12, Lee discloses the semiconductor structure according to claim 11, further comprising:
a plurality of word lines, (word lines 2303) wherein each of the plurality of word lines surrounds a part of a surface of a respective one of the plurality of oxide semiconductor layers, and each of the plurality of word lines extends along one of the first direction and the second direction; (see FIGS. 20B and 20C, showing the surrounding of at least part of layer 2063)
a plurality of bit lines, (digit line 2041) wherein each of the plurality of bit lines surrounds a part of a surface of a respective one of the plurality of oxide semiconductor layers, each of the plurality of bit lines is spaced from a respective one of the plurality of word lines, and each of the plurality of bit lines extends along another one of the first direction and the second direction; (See FIGS 20B-C) and
a plurality of capacitors, (capacitors comprising electrodes 2061-2062 and dielectric 2063 between the electrodes) wherein each of the plurality of capacitors is in contact with a respective one of the plurality of initial active layers, the plurality of capacitors extend along the first direction and are spaced apart from each other along the second direction and the third direction.
With regards to claim 13, Lee discloses the semiconductor structure according to claim 12, wherein the plurality of capacitors comprises:
a plurality of lower electrode plates, (plates 2061) wherein each of the plurality of lower electrode plates covers a part of a surface of the respective one of the plurality of initial active layers;
a plurality of capacitive dielectric layers, (dielectric 2063) wherein each of the plurality of capacitive dielectric layers covers a surface of a respective one of the plurality of lower electrode plates, and each of the plurality of capacitive dielectric layers also covers a part of the surface of the respective one of the plurality of initial active layers away from a respective one of the plurality of lower electrode plates; and
a plurality of upper electrode plates, (electrodes 2062) wherein the plurality of upper electrode plates cover surfaces of the plurality of capacitive dielectric layers. (See FIG. 20C)
With regards to claim 14, Lee discloses the semiconductor structure according to claim 12, wherein each of the plurality of word lines extends along the second direction, the plurality of word lines comprises:
a plurality of first word lines, (digit lines 2041) wherein each of the plurality of first word lines surrounds a part of a surface of a respective one of the plurality of oxide semiconductor layers; and
a plurality of second word lines, (digit lines 2042) wherein each of the plurality of second word lines covers a side wall of a respective one of the plurality of first word lines. (See FIG. 20C)
With regards to claim 16, Lee discloses the semiconductor structure according to claim 11, wherein a thickness of each of the plurality of active structures in the first direction ranges from 15 nm to 25 nm. (Paragraph [0082]: “In one embodiment, the silicon 432 can be deposited to have a thickness (t2), e.g., vertical height, in a range of five (5) nm to thirty (30) nm.” Where the silicon 432 is formed into the access line 2077, and the range is within the range of cited, See FIGS. 4-20C)
Allowable Subject Matter
Claims 15 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. CHOI et al. (US 11410951 B2) – horizontal access devices.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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