DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 7-10, 12, 15, 16, and 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Palapra et al. (U.S. Patent Application Publication Number 2020/0014613), Ryan (U.S. Patent Application Publication Number 2019/0335252), and Sufleta (U.S. Patent Application Publication Number 2017/0214566).
Regarding Claims 1 and 10, Palapra discloses a system (Figure 1, item 100) comprising:
a networking switch (Figure 1, item 114-1, paragraph 0023; i.e., an aggregation switch), including an internal port (Figure 1; i.e., an internal port that connects to core switch 118), a plurality of external ports (Figure 1; i.e., see plural external ports that connect to other devices 108 and 114), and a switch fabric (paragraph 0023); and
processing circuitry (Figure 1, item 118-1 and Figure 2, item 200, paragraph 0032; i.e., a processor 200 [Figure 2] can be located within core switch 118 [Figure 1]) coupled to the networking switch (i.e., via link 116) and configured to:
receive a reset request (paragraph 0013; i.e., one or more processors may communicate with the target switch to orchestrate the temporary removal from the computer system; this removal involves the target switch restarting/resetting [paragraph 0014]; therefore, it is considered equivalent to the claimed “reset request”); and
isolate the networking switch from the other components (Figure 1, items 110) in the system by placing the internal port in a non-forwarding state (paragraph 0014; i.e., the target switch that is selected to be restarted cannot forward data packets when it is offline) in response to the reset request (paragraph 0031; i.e., after the switch 114-1 [the “target switch” discussed in the reference] receives the reset request, it is temporarily removed from the network 100 [Figure 1], thereby isolating it from other components in the system, including user devices 110).
Palapra does not expressly disclose wherein the system is an integrated system-on-a-chip (SoC);
wherein the processing circuitry is configured to enable the internal port to communicate data packets between the networking switch and other components in the system, by placing the internal port in a forwarding state; and
wherein the networking switch is configured to switch network routing flows at its external ports, using its switch fabric, while its internal port is in a non-forwarding state.
In the same field of endeavor (e.g., network switching techniques), Ryan teaches wherein the system is an integrated system-on-a-chip (SoC) (Figure 2, item 109, paragraph 0034; i.e., SoC 109 can include a switch controller and processing circuitry).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Ryan’s teachings of network switching techniques with the teachings of Palapra, for the purpose of providing a device that gives reduced size and weight, increased power efficiency, improved performance, lower manufacturing costs, and enhanced reliability, which are well known advantages of systems on a chip.
Also in the same field of endeavor (e.g., network switching techniques), Sufleta teaches wherein the processing circuitry (Figure 3B, item 150, paragraph 0026; i.e., network packets may be processed in the tool 150, which may be integrated into switch 120) is configured to enable the internal port (Figure 3B, items 164a/b) to communicate data packets between the networking switch and other components in the system, by placing the internal port in a forwarding state (Figure 3B, paragraph 0045; i.e., in the normal operating state [the claimed “forwarding state”], the internal port 164a/b is enabled so network packets received from source node 110 are received at switch 120, processed at tool 150, and forwarded on to destination node 112); and
wherein the networking switch is configured to switch network routing flows at its external ports (Figure 3C, items 160 and 162, paragraph 0046; i.e., “Fig. 3C illustrates packet routing through system 300 when network switch appliance 120 is operating in a second state”), using its switch fabric (Figure 3B, items 126a, 124, and 126b, paragraph 0045; i.e., the combination of items 126a, 124, and 126b is considered equivalent to the claimed “switch fabric”), while its internal port is in a non-forwarding state (Figure 3C, paragraph 0046; i.e., the tool 150 can be isolated from the network when there is a failure in switch 120, which causes the network flows to simply be forwarded from source port 160 to destination port 162; although a portion of the equated “switch fabric” [i.e., items 124 and 126b] is bypassed, another portion of the equated switch fabric [i.e., item 126a] continues to be used in the non-forwarding state).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Sufleta’s teachings of network switching techniques with the teachings of Palapra, for the purpose of reducing the chances of bottleneck in the switch as well as preventing data loss during the system upgrade.
Regarding Claims 4, 12, and 20, Palapra discloses wherein to isolate the networking switch, the processing circuitry is configured to electrically isolate (paragraph 0029; i.e., the target switch is taken offline) the networking switch from the other components in the system while the other components are rebooting (paragraph 0014; i.e., any of the switches 108-118 can be selected as the “target switch”; therefore, it is possible that when one of the switches 114 is taken offline, another of the switches 108 or 118 could be rebooting at the same time).
Regarding Claim 7, Palapra discloses wherein the processing circuitry is configured to receive the reset request from a source; and send an acknowledgment to the source of the reset request (paragraphs 0013-0014; i.e., the target switch may initially receive the request to shut down from another switch, but subsequently transmits a notification to all connected switches [which would presumably include the switch that sent the original shutdown request] that it will be shutting down soon).
Regarding Claim 8, Palapra discloses wherein the processing circuitry is configured to reboot the other components in the system while the networking switch is isolated and in response to the reset request (paragraph 0014; i.e., any of the switches 108-118 can be selected as the “target switch”; therefore, it is possible that when one of the switches 114 is taken offline, another of the switches 108 or 118 could be rebooting at the same time).
Regarding Claims 9 and 15, Palapra discloses wherein the networking switch includes an internal port coupled to the processing circuitry, and wherein the processing circuitry is configured to set the internal port to a forwarding state after rebooting the other components in the system (paragraph 0014; i.e., after the target switch reboots, it is once again able to communicate data between the various other components in the system 100).
Regarding Claim 16, Palapra discloses a device comprising:
a first processing circuit (Figure 1, item 114-2 and Figure 2, item 200, paragraph 0032; i.e., a processor 200 [Figure 2] can be located within aggregation switch 114-2 [Figure 1]); and
a second processing circuit (Figure 1, item 114-1, paragraph 0023; i.e., the processor [paragraph 0032] located within aggregation switch 114-1) coupled to the first processing circuit (i.e., via link 116)
a networking switch (Figure 1, item 114-1, paragraph 0023; i.e., an aggregation switch), including an internal port (Figure 1; i.e., an internal port that connects to core switch 118) coupled to the first processing circuit, a plurality of external ports (Figure 1; i.e., see plural external ports that connect to other devices 108 and 114), and a switch fabric (paragraph 0023);
wherein the second processing circuit is configured to:
receive a reset request (paragraph 0013; i.e., one or more processors [e.g., from a core switch 118-1] may communicate with the target switch [e.g., aggregation switch 114-1] to orchestrate the temporary removal from the computer system; this removal involves the target switch restarting/resetting [paragraph 0014]; therefore, it is considered equivalent to the claimed “reset request”);
isolate the networking switch (Figure 1, item 114-1) from the first processing circuit by placing the internal port in a non-forwarding state (paragraph 0014; i.e., the target switch that is selected to be restarted cannot forward data packets when it is offline) in response to the reset request (paragraph 0031; i.e., after the switch 114-1 [the “target switch” discussed in the reference] receives the reset request, it is temporarily removed from the network 100 [Figure 1], thereby isolating it from other components in the system, including user devices 110 and other switches 114 and 118); and
reboot the first processing circuit while the networking switch is isolated from the first processing circuit (paragraph 0014; i.e., any of the switches 108-118 can be selected as the “target switch” to be restarted/rebooted; therefore, it is possible that when one of the switches 114-1 is taken offline, another of the switches 114-2 could be rebooting at the same time).
Palapra does not expressly disclose wherein the device is an integrated circuit device;
wherein the internal port is enabled to communicate data packets between the networking switch and the first processing circuit while in a forwarding state; and
wherein the networking switch is configured to switch network routing flows at its external ports, using its switch fabric, while its internal port is in a non-forwarding state.
In the same field of endeavor, Ryan teaches wherein the device is an integrated circuit device (Figure 2, item 109, paragraph 0034; i.e., integrated circuit 109 can include a switch controller and processing circuitry).
Also in the same field of endeavor, Sufleta teaches wherein the internal port (Figure 3B, items 164a/b) is enabled to communicate data packets between the networking switch and the first processing circuit while in a forwarding state (Figure 3B, paragraph 0045; i.e., in the normal operating state [the claimed “forwarding state”], the internal port 164a/b is enabled so network packets received from source node 110 are received at switch 120, processed at tool 150, and forwarded on to destination node 112); and
wherein the networking switch is configured to switch network routing flows at its external ports (Figure 3C, items 160 and 162, paragraph 0046; i.e., “Fig. 3C illustrates packet routing through system 300 when network switch appliance 120 is operating in a second state”), using its switch fabric (Figure 3B, items 126a, 124, and 126b, paragraph 0045; i.e., the combination of items 126a, 124, and 126b is considered equivalent to the claimed “switch fabric”), while its internal port is in a non-forwarding state (Figure 3C, paragraph 0046; i.e., the switching fabric 124 and tool 150 can be isolated from the network when there is a failure in switch 120, which causes the network flows to simply be forwarded from source port 160 to destination port 162; although a portion of the equated “switch fabric” [i.e., items 124 and 126b] is bypassed, another portion of the equated switch fabric [i.e., item 126a] continues to be used in the non-forwarding state).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 16.
Regarding Claims 21-23, Sufleta teaches a memory coupled to the networking switch and capable of storing a setting, wherein the networking switch is configured to switch the network routing flows at its external ports, using its switch fabric and responsive to the setting, while its internal port is in the non-forwarding state (paragraph 0043; i.e., registers may used to set the switch to allow for desired operation).
Claims 3 and 18 is rejected under 35 U.S.C. 103 as being unpatentable over Palapra, Ryan, and Sufleta as applied to Claims 1 and 16, and further in view of Uner et al. (U.S. Patent Application Publication Number 2016/0048693).
Regarding Claims 3 and 18, Palapra, Ryan, and Sufleta do not expressly disclose wherein the processing circuitry is configured to save startup configuration information and state information in response to the reset request.
In the same field of endeavor (e.g., device reset techniques), Uner teaches wherein the processing circuitry is configured to save startup configuration information and state information in response to the reset request (paragraph 0048; i.e., mode-specific elements of the device to be rebooted may be paused and saved).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Uner’s teachings of device reset techniques with the teachings of Palapra, Ryan, and Sufleta, for the purpose of preventing data loss when the target switch is reset.
Allowable Subject Matter
Claims 5, 6, 13, 14, and 19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claims 5, 13, and 19, the prior art of record does not teach “wherein the networking switch includes an internal port coupled to the processing circuitry, and wherein the processing circuitry is configured to: bypass a register configuration for the networking switch in response to the reset request; and purge classifier entries and routing tables for the internal port.”
All claims that are not specifically addressed are allowable due to a dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses systems for isolating a networking switch during a reboot.
Response to Arguments
Applicant's arguments filed 4/20/26 have been fully considered but they are not persuasive.
Regarding Claim 1, Applicant argues “Sufleta discloses that during a ‘failure or power loss state the relays of bypass switch 126a are closed and form a physical communications bridge (i.e. electrical pathway) to pass packets between network ports 160 and 162, thereby bypassing switching fabric 124.’ Accordingly, and as tentatively agreed during phone interview with the Examiner, Sufleta does not disclose the above-quoted limitations of amended claim 1.” Response, page 9. However, upon further consideration it has been determined that Sufleta does in fact teach the argued feature. Specifically, Sufleta states “Fig. 3C illustrates packet routing through system 300 when network switch appliance 120 is operating in a second state.” Sufleta, paragraph 0046. Sufleta therefore considers the bypassing of switching fabric 124 to still include packet routing. Therefore, the passing of network packets directly from node 100 through ports 160 and 162 and bypass switch 126a to node 112 includes “network routing flows” (i.e., flows of packets as they pass through switch appliance 120) as required by the amended claim. Accordingly, it can be seen that Sufleta does in fact teach the argued limitation.
Therefore, the claims stand as previously rejected.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN, ESQ. whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
Prosecution Insights