Prosecution Insights
Last updated: October 25, 2026
Application No. 18/395,755

PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF

Final Rejection §102§103
Filed
Dec 26, 2023
Priority
Nov 08, 2023 — TW 112142987
Examiner
TRAN, TAN N
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Unimicron Technology Corp.
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
980 granted / 1128 resolved
+18.9% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
36 currently pending
Career history
1168
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
34.0%
-6.0% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1128 resolved cases

Office Action

§102 §103
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 – 4, 8 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by KIM (2022/0359358). With regard to claim 1, KIM discloses a package substrate (for example, see fig. 2), comprising: a core layer (400), having a first surface (400a) and a second surface (400b) opposite each other, and at least one opening (400T) and a plurality of conductive through vias (415) connecting the first surface (400a) and the second surface (400b); at least one functional component (340), disposed in the at least one opening (400T) of the core layer (400), wherein the at least one opening (400T) exposes at least one action surface (a top surface) of the at least one functional component (340); at least one spacer (referred to as “420A” by examiner’s annotation shown in fig. 2 below; wherein the spacer 420A including conductive layers 350, an adhesive layer 450; a mold layer 460 and connection pads 352), directly disposed on (on the bottom surface) the at least one functional component (340) and having at least one bottom surface (referred to as “350A” by examiner’s annotation shown in fig. 2 below) relatively away from the at least one functional component (340), wherein the bottom surface of the at least one spacer (420A) is equal to or higher than the second surface (400b) of the core layer (400), and the at least one spacer (420A) is at least one thermal interface material (adhesive interface material 450 of the spacer 420A as annotated below, made of insulating polymer functions as a thermal interface material by restricting the movement of heat through microscopic structural barriers, low intrinsic conductivity and trapped gas pockets), or at least one copper block (conductive pads 352 of the spacer 420A made of copper material, for example, see paragraph [0042], functions as thermal material). a filler (460), filled in the at least one opening (400T) and having a third surface (referred to as “460A1” by examiner’s annotation shown in fig. 2 below) and a fourth surface (referred to as “460A2” by examiner’s annotation shown in fig. 2 below) opposite each other, wherein the filler (460) covers the at least one functional component (340) and the at least one spacer (420A) and completely fills a gap (referred to as “G” by examiner’s annotation shown in fig. 2 below) between the at least one opening (400T), the at least one functional component (340), and the at least one spacer (420A), the third surface (460A1) exposes the at least one action surface (the top surface) of the at least one functional component (340), and the fourth surface (460A2) exposes the at least one bottom surface (350A) of the at least one spacer (420A); a first build-up structure (200), disposed on the first surface (400a) of the core layer (400) and the third surface (460A1) of the filler (460) and electrically connected to the at least one functional component (340) and the conductive through vias (415); and a second build-up structure (250), disposed on the second surface of the core layer (400) and the fourth surface (460A2) of the filler (460), contacting the at least one bottom surface (350A) of the at least one spacer (420A), and electrically connected to the conductive through vias (415). PNG media_image1.png 553 716 media_image1.png Greyscale With regard to claim 2, KIM discloses there is a first height difference between the third surface (460A1) of the filler (460) and the first surface (the bottom portion surface of the conductive portion 342) of the core layer (400), and there is a second height difference between the fourth surface (460A2) of the filler (460) and the second surface (the bottom portion surface of the conductive portion 352) of the core layer (400). PNG media_image1.png 553 716 media_image1.png Greyscale With regard to claim 3, KIM discloses an orthographic projection of the at least one spacer (420A) on (on the bottom surface) the at least one functional component (340) is smaller than the at least one functional component (340). With regard to claim 4, KIM discloses wherein when viewed in cross section, a shape of the at least one spacer (420A) comprises a rectangle. With regard to claim 8, KIM discloses wherein the at least one spacer (referred to as “420A” by examiner’s annotation shown in fig. 2 below; wherein the spacer 420A including conductive layers 350, adhesive layer 450, conductive pads 352) comprises at least one first spacer (450) and at least one second spacer (350), and the at least one first spacer (450) is located between the at least one functional component (340) and the at least one second spacer (350). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over KIM (2022/0359358) in view of KURAMOCHI (2025/0149527). With regard to claim 5, KIM does not clearly disclose the core layer has a first thickness, the at least one functional component has at least one second thickness, and a difference between the first thickness and the at least one second thickness is at least more than 100 microns. However, KURAMOCHI discloses the core layer (22) has a first thickness, the at least one functional component (32) has at least one second thickness, and a difference between the first thickness and the at least one second thickness is at least more than 100 microns. (a thickness of the core layer 22 is 2.0 mm = 2000 micrometer. The thickness of the at least one functional component 32 appears is a half thickness of the core layer 22, and to be about 1.0 mm = 1000 micrometer. Therefore, a difference between the first thickness and the at least one second thickness is at least more than 1000 microns). However, since the patent drawings are not labeled as “to scale,” one cannot be certain that the thickness of the at least one functional component 32 appears is a half thickness of the core layer 22, and to be about 1.0 mm = 1000 micrometer as seemingly shown [see MPEP 2125]. It would have been obvious to one having ordinary skill in the art at the time of the claimed invention to form a difference between the first thickness and the at least one second thickness is at least more than 1000 microns, because Fig. 2 suggests a difference between the first thickness and the at least one second thickness is at least more than 1000 microns and a prima facie case of obviousness exists where device dimensions of the prior art are such that one of ordinary skill in the art would have expected them to have the same performance {MPEP 2144.04(IV)(A)} PNG media_image2.png 479 678 media_image2.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the KIM’s device to have the core layer has a first thickness, the at least one functional component has at least one second thickness, and a difference between the first thickness and the at least one second thickness is at least more than 100 microns as taught by KURAMOCHI in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over KIM (2022/0359358) in view of Nickerson et al. (11705383). With regard to claim 6, KIM does not clearly disclose the at least one functional component is separated from an inner wall of the at least one opening by at least one spacing, and the at least one spacing is at least more than 20 microns. However, KURAMOCHI discloses the at least one functional component (134) is separated from an inner wall (referred to as “141A” by examiner’s annotation shown in fig. 2 below) of the at least one opening (141) by at least one spacing (D), and the at least one spacing (D) is at least more than 500 microns (for example, column 4, lines 60, 61, figs. 1, 5). PNG media_image3.png 438 685 media_image3.png Greyscale PNG media_image4.png 392 604 media_image4.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the KIM’s device to have the at least one functional component is separated from an inner wall of the at least one opening by at least one spacing, and the at least one spacing is 500 microns as taught by Nickerson et al. in order to minimize the signal interference and secure a high electrical connection efficiency for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. Response to Amendment 6. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Conclusion 7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. 8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TAN N TRAN/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Dec 26, 2023
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102, §103
Sep 02, 2026
Response Filed
Oct 01, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+9.9%)
2y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1128 resolved cases by this examiner. Grant probability derived from career allowance rate.

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