Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-8, in the reply filed on 04/23/2026 is acknowledged. Claims 9-15 are cancelled. Claims 1-8 are examined below.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Taiwan on 09/23/2023. It is noted, however, that applicant has not filed a certified copy of the TW112136478 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20230116927 A1) in view of Yoo (US 20210028098 A1).
Re: Independent Claim 1, Lee discloses a display module, comprising:
a light-emitting element having a first surface and a second surface opposite to each other and further comprising a lead disposed on the first surface (Lee teaches, in Fig. 3B, light emitting elements, namely micro LED chips R/G/B. Lee further teaches that each micro LED chip R/G/B includes a connecting pad P exposed at a surface of the micro LED chip. The connection pad P corresponds to the claimed lead disposed on a first surface of the light emitting element, and the opposite surface of the micro LED chip corresponds to the claimed second surface);
a molding layer laterally surrounding the light-emitting element and having a first surface and a second surface opposite to each other, wherein the first surface of the molding layer is adjacent to the first surface of the light-emitting element (Lee teaches, in Fig. 3B, molding portion 330 surrounding micro LED chip R/G/B; molding portion 330 have first surface on which connection pad P of each micro LED chip R/G/B is exposed. Thus, molding portion 330 has a first surface adjacent to the pad-side first surface of the micro LED chip and a second opposite surface as shown in Fig. 3B. Examiner’s Note: the specification of Lee (US 20210375833 A1) calls the molding portion 230. However, that’s an error and should be molding portion 330 as correctly shown in Fig. 3B (also see issued patent Lee (US11658162B2)));
Regarding the limitation “a metal contact covering the lead of the light-emitting element”, Lee does not show in Fig. 3B a metal contact covering the lead. However, Lee teaches, in Fig. 1G and ¶¶ [0057] - [0058], circuit 142 (an electrical coupling path) of PCB 140 is electrically coupled to pad P, covering connecting pad P of each micro LED chip R/G/B through conductive material 141 (e.g., metal such as copper). Thus 141 is the claimed metal contact.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the Fig. 3 structure with the metal-contact arrangement of fig. 1G because both embodiments are directed to Lee’s micro LED display manufacturing process using micro LED chips R/G/B having exposed connecting pads P. Further, Lee teaches the need to electrically couple pad P of each micro LED chip R/G/B to PCB circuitry, and fig. 1G provides a known FOPLP redistribution structure for doing so using via 140a, conductive material 141, and circuit 142. Applying the fig. 1G interconnect structure to the fig. 3B pad-covered layer structure would have predictably provided electrical connection between the exposed micro LED pads P and PCB 140.
Lee further teaches
an insulating layer covering the metal contact and the molding layer (Lee teaches, in Fig. 3B, photosensitive layer 322 covering the molding portion 330 and metal contact layer 141 in the modified structure of fig. 3B as taught by structure of Lee’s fig. 1G as explained above. The photosensitive layer is a photosensitive polymer material (see ¶ [0063]), thus, an insulating layer).
Regarding the limitation “an array substrate disposed on the insulating layer and having a pad configured to be electrically connected to the metal contact”, Lee, in fig. 3B, teaches photosensitive layer 322 formed on upper face 330a of molding portion 330, wherein the photosensitive layer 322 covers connecting pad P of each micro Led chip R/G/B and is formed to fix a location for disposing PCB. Lee further teaches, in Figs. 1I and 1J and ¶ [0066], that micro LED array package 14 is laminated on PCB 160, which may be a substrate having a TFT structure, and includes connecting pad 161 exposed at one face 160a. Pad P of each micro LED chip is electrically coupled to connecting pad 161 of PCB 160 through first conductive structure 150. Thus, PCB 160 corresponds to the claimed array substrate, and solder pad 161 corresponds to the claimed pad configured to be electrically connected to the metal contact. To the extent Fig. 3B and Figs. 1I-1J are separate embodiments, it would have been obvious to use the PCB/TFT substrate and pad-connection arrangement of Figs. 1I-1J with the Fig. 3B photosensitive-layer structure because Fig. 3B expressly teaches forming photosensitive layer 322 to fix a location for disposing PCB 140, and Figs. 1I-1J provide Lee’s disclosed electrical connection between the micro LED package and PCB/TFT substrate.
Lee is silent regarding
the first surface of the molding layer is a coarse surface.
However, Yoo teaches the first surface of the molding layer is a coarse surface (Yoo teaches, in Fig. 1 and ¶ [0062], that in fan-out semiconductor packaging, a molding layer 250 surrounding a semiconductor chip and conductive post 160 may have a top surface 251 with greater roughness than top surface 161 of the conductive post. Yoo further teaches, in ¶ [0072], forming an upper redistribution insulating layer 411 on the molding layer and conductive post. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide Lee’s pad-side first surface 330a of molding portion 330 with Yoo’s roughened top surface configuration, in order to improve adhesion/reliability between the molding layer and the overlying insulating/substrate-connection structure while maintaining a smoother metal contact surface for electrical connection).
Re: Claim 2, Lee and Yoo disclose all the limitations of claim 1 on which this claim depends.
Yoo further teaches
wherein a roughness of the first surface of the molding layer is greater than a roughness of the second surface of the molding layer (Yoo teaches, in ¶ [0125], that the top surface 251 of molding layer 250 is subjected to a polishing process and has increased roughness, and that the roughness of top surface 251 of molding layer 250 is greater than the roughness of other exposed package surfaces. Because Yoo’s roughening treatment is applied to the exposed top surface of the molding layer and not to the opposite bottom surface facing the underlying support structure, the treated first surface would predictably have a greater roughness than the untreated opposite second surface of the molding layer. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide Lee’s pad-side upper face 330a of molding portion 330 with Yoo’s roughened top-surface configuration, in order to improve adhesion between the molding portion and an overlying insulating/substrate connection structure).
Re: Claim 3, Lee and Yoo disclose all the limitations of claim 1 on which this claim depends.
Yoo further teaches
wherein a roughness of the first surface of the molding layer is greater than a roughness of a surface of the metal contact (Yoo teaches, in ¶ [0125], that the top surface 251 of molding layer 250 is subjected to a polishing process and has increased roughness, and that the roughness of top surface 251 of molding layer 250 is greater than the roughness of the top surface 161 of conductive post 160. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide Lee’s pad-side upper face 330a of molding portion 330 and Lee’s metal contact material 141 with Yoo’s known roughness arrangement, in order to improve adhesion between the molding portion and an overlying insulating/substrate connection structure).
Re: Claim 4, Lee and Yoo disclose all the limitations of claim 1 on which this claim depends.
Yoo further teaches
wherein a roughness of the first surface of the molding layer is greater than a roughness of the second surface of the light-emitting element (Yoo teaches, in ¶ [0125], that the top surface 251 of molding layer 250 is subjected to a polishing process and has increased roughness. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide Lee’s pad-side upper face 330a of molding portion 330 with Yoo’s roughened molding-layer surface configuration in order to improve adhesion between the molding portion and an overlying insulating/substrate connection structure. Because the roughening treatment is applied to the molding-layer surface and not to the opposite second surface of Lee’s micro LED chip R/G/B, the treated first surface of the molding layer would predictably have greater roughness than the second surface of the light-emitting element).
Re: Claim 5, Lee and Yoo disclose all the limitations of claim 1 on which this claim depends.
Lee further teaches
wherein the molding layer covers the first surface of the light-emitting element (Lee, in Figs. 1F and 1G, teaches molding layer 130 covers the first surface of the micro LED chip R/G/B), and the lead of the light-emitting element passes through the molding layer and contacts the metal contact (Lee teaches, in Fig. 1G, connecting pad P passes through molding layer 130 and contacts the metal contact 141).
Claim(s) 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20230116927 A1) in view of Yoo (US 20210028098 A1) further in view of Tsai (US 20150179591 A1).
Re: Claim 6, Lee and Yoo disclose all the limitations of claim 5 on which this claim depends.
Lee and Yoo are silent regarding
wherein the lead of the light-emitting element protrudes from the first surface of the molding layer.
However, Tsai teaches
wherein the lead of the light-emitting element protrudes from the first surface of the molding layer (Tsai teaches, in Fig. 2A and ¶ [0024], a molded semiconductor package in which protruding redistribution layer bond pad 16 projects above a top surface of molding compound 38. Tsai further teaches that a central portion of redistribution layer bond pad 16 protrudes upwardly while outer portions of bond pad 16 are embedded in molding compound 38).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure Lee’s connecting pad P using Tsai’s protruding bond-pad arrangement such that connecting pas P protrudes from the first surface of molding portion 330 in order to provide an exposed, raised electrical terminal that facilitates reliable electrical contact between the micro LED chip pad P and overlying metal contact structure, including conductive material 141 and circuit/interconnect 142.
Re: Claim 7, Lee, Yoo and Tsai disclose all the limitations of claim 6 on which this claim depends.
Tsai further teaches
wherein the metal contact extends from an upper surface of the lead, through a side surface of the lead, to the first surface of the molding layer (Tsai teaches, in Fig. 1, solder joint 54 (claimed metal contact) extends from upper surface of bond pad 16, through side surface of bond pad 16. Fig. 1 further shows that solder joint 54 is extending to top surface of molding compound 38.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee’s connecting pad P and conductive material 141/circuit interconnect 142 using Tsai’s bond-pad and solder-contact configuration, such that the metal contact extends from an upper surface of the lead/connecting pad P, through a side surface of the lead/connecting pad , to the first surface of molding portion 330 in order to increase the contact area between the LED connecting pad and the overlying metal contact, improve reliability on the protruding pad, and provide a stronger electrical and mechanical connection between the micro LED chip and the substrate interconnect structure).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20230116927 A1) in view of Yoo (US 20210028098 A1) further in view of Oh (US 20230059891 A1).
Re: Claim 8, Lee and Yoo disclose all the limitations of claim 1 on which this claim depends.
Lee further teaches
the metal contact is configured to receive a second driving signal (Lee teaches, in ¶ [0057], conductive material 141 and circuit/interconnect 142 formed on the PCB 140 may be electrically coupled to connecting pad P of each of the micro LED chips R/G/B. For this reason, it would be obvious that conductive material 141 and circuit/interconnect 142 are capable of receiving/conducting an electrical signal used to operate the micro LED pixel. Accordingly, the claimed “metal contact is configured to receive a second driving signal” is met by a conductive path electrically coupled to the LED pad in a display module and capable of receiving such a signal).
Lee and Yoo are silent regarding
further comprising a touch sensing electrode disposed on the second surface of the molding layer, wherein the touch sensing electrode is configured to receive a first driving signal, and the second driving signal is different from the first driving signal,
However, Oh teaches
further comprising a touch sensing electrode disposed on the second surface of the molding layer, wherein the touch sensing electrode is configured to receive a first driving signal, and the second driving signal is different from the first driving signal (Oh teaches, in Figs. 1-2, a touch display device 100 including display panel 110 and touch electrodes TE. Oh teaches, in ¶ [0091], that touch electrodes TE may be disposed on encapsulation layer ENCAP of the display panel, and that in a self-capacitance touch scheme, each touch electrode TE serves as both touch driving electrode and the touch sensing electrode. Oh further teaches that a touch driving signal is suppled to touch electrode TE through a touch line.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide Oh’s touch electrode TE on the opposite second surface of Lee’s molding portion 330 in order to integrate touch-sensing functionality into Lee’s micro LED display module without requiring a separate external touch panel. In the modified structure, touch electrode TE receives a first driving signal, namely the touch driving signal, while Lee’s conductive material 141 and circuit/interconnect 142, which are electrically coupled to pad P of the micro LED chips R/G/B, are capable of receiving /conducting a second driving signal for operating the micro LED chips. The second driving signal is different from the first driving signal because the first signal is used for touch sensing, whereas the second signal is used for light-emission/display operation).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BIPANA ADHIKARI DAWADI/ Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
Prosecution Insights